2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 * device name digital output 7-bit I2C slave address (pin selectable)
5 * ---------------------------------------------------------------------
6 * MMA8451Q 14 bit 0x1c / 0x1d
7 * MMA8452Q 12 bit 0x1c / 0x1d
8 * MMA8453Q 10 bit 0x1c / 0x1d
9 * MMA8652FC 12 bit 0x1d
10 * MMA8653FC 10 bit 0x1d
11 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 * This file is subject to the terms and conditions of version 2 of
17 * the GNU General Public License. See the file COPYING in the main
18 * directory of this archive for more details.
20 * TODO: orientation events
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pm_runtime.h>
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
65 #define MMA8452_TRANSIENT_SRC 0x1e
66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
69 #define MMA8452_TRANSIENT_THS 0x1f
70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
71 #define MMA8452_TRANSIENT_COUNT 0x20
72 #define MMA8452_CTRL_REG1 0x2a
73 #define MMA8452_CTRL_ACTIVE BIT(0)
74 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
75 #define MMA8452_CTRL_DR_SHIFT 3
76 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
77 #define MMA8452_CTRL_REG2 0x2b
78 #define MMA8452_CTRL_REG2_RST BIT(6)
79 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
80 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
81 #define MMA8452_CTRL_REG4 0x2d
82 #define MMA8452_CTRL_REG5 0x2e
83 #define MMA8452_OFF_X 0x2f
84 #define MMA8452_OFF_Y 0x30
85 #define MMA8452_OFF_Z 0x31
87 #define MMA8452_MAX_REG 0x31
89 #define MMA8452_INT_DRDY BIT(0)
90 #define MMA8452_INT_FF_MT BIT(2)
91 #define MMA8452_INT_TRANS BIT(5)
93 #define MMA8451_DEVICE_ID 0x1a
94 #define MMA8452_DEVICE_ID 0x2a
95 #define MMA8453_DEVICE_ID 0x3a
96 #define MMA8652_DEVICE_ID 0x4a
97 #define MMA8653_DEVICE_ID 0x5a
98 #define FXLS8471_DEVICE_ID 0x6a
100 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
102 struct mma8452_data {
103 struct i2c_client *client;
107 const struct mma_chip_info *chip_info;
111 * struct mma_chip_info - chip specific data
112 * @chip_id: WHO_AM_I register's value
113 * @channels: struct iio_chan_spec matching the device's
115 * @num_channels: number of channels
116 * @mma_scales: scale factors for converting register values
117 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
118 * per mode: m/s^2 and micro m/s^2
119 * @ev_cfg: event config register address
120 * @ev_cfg_ele: latch bit in event config register
121 * @ev_cfg_chan_shift: number of the bit to enable events in X
122 * direction; in event config register
123 * @ev_src: event source register address
124 * @ev_src_xe: bit in event source register that indicates
125 * an event in X direction
126 * @ev_src_ye: bit in event source register that indicates
127 * an event in Y direction
128 * @ev_src_ze: bit in event source register that indicates
129 * an event in Z direction
130 * @ev_ths: event threshold register address
131 * @ev_ths_mask: mask for the threshold value
132 * @ev_count: event count (period) register address
134 * Since not all chips supported by the driver support comparing high pass
135 * filtered data for events (interrupts), different interrupt sources are
136 * used for different chips and the relevant registers are included here.
138 struct mma_chip_info {
140 const struct iio_chan_spec *channels;
142 const int mma_scales[3][2];
145 u8 ev_cfg_chan_shift;
162 static int mma8452_drdy(struct mma8452_data *data)
166 while (tries-- > 0) {
167 int ret = i2c_smbus_read_byte_data(data->client,
171 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
177 dev_err(&data->client->dev, "data not ready\n");
182 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
188 ret = pm_runtime_get_sync(&client->dev);
190 pm_runtime_mark_last_busy(&client->dev);
191 ret = pm_runtime_put_autosuspend(&client->dev);
195 dev_err(&client->dev,
196 "failed to change power state to %d\n", on);
198 pm_runtime_put_noidle(&client->dev);
207 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
209 int ret = mma8452_drdy(data);
214 ret = mma8452_set_runtime_pm_state(data->client, true);
218 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
219 3 * sizeof(__be16), (u8 *)buf);
221 ret = mma8452_set_runtime_pm_state(data->client, false);
226 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
232 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
233 vals[n][0], vals[n][1]);
235 /* replace trailing space by newline */
241 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
245 if (val == vals[n][0] && val2 == vals[n][1])
251 static int mma8452_get_odr_index(struct mma8452_data *data)
253 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
254 MMA8452_CTRL_DR_SHIFT;
257 static const int mma8452_samp_freq[8][2] = {
258 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
259 {6, 250000}, {1, 560000}
262 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
263 static const int mma8452_transient_time_step_us[4][8] = {
264 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
265 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
266 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
267 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
270 /* Datasheet table "High-Pass Filter Cutoff Options" */
271 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
273 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
274 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
275 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
276 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
277 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
278 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
279 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
280 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
282 { /* low noise low power */
283 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
284 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
285 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
286 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
287 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
288 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
289 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
290 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
292 { /* high resolution */
293 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
294 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
295 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
296 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
297 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
298 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
299 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
300 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
304 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
305 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
306 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
307 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
308 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
309 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
310 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
314 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
315 static const u16 mma8452_os_ratio[4][8] = {
316 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
317 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
318 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
319 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
320 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
323 static int mma8452_get_power_mode(struct mma8452_data *data)
327 reg = i2c_smbus_read_byte_data(data->client,
332 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
333 MMA8452_CTRL_REG2_MODS_SHIFT);
336 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
337 struct device_attribute *attr,
340 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
341 ARRAY_SIZE(mma8452_samp_freq));
344 static ssize_t mma8452_show_scale_avail(struct device *dev,
345 struct device_attribute *attr,
348 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
349 to_i2c_client(dev)));
351 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
352 ARRAY_SIZE(data->chip_info->mma_scales));
355 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
356 struct device_attribute *attr,
359 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
360 struct mma8452_data *data = iio_priv(indio_dev);
363 i = mma8452_get_odr_index(data);
364 j = mma8452_get_power_mode(data);
368 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
369 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
372 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
373 struct device_attribute *attr,
376 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
377 struct mma8452_data *data = iio_priv(indio_dev);
378 int i = mma8452_get_odr_index(data);
383 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
384 if (val == mma8452_os_ratio[j][i])
387 val = mma8452_os_ratio[j][i];
389 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
396 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
397 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
398 mma8452_show_scale_avail, NULL, 0);
399 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
400 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
401 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
402 mma8452_show_os_ratio_avail, NULL, 0);
404 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
407 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
408 ARRAY_SIZE(mma8452_samp_freq),
412 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
414 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
415 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
418 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
423 i = mma8452_get_odr_index(data);
424 j = mma8452_get_power_mode(data);
428 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
429 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
432 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
436 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
440 i = mma8452_get_odr_index(data);
441 j = mma8452_get_power_mode(data);
445 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
446 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
447 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
452 static int mma8452_read_raw(struct iio_dev *indio_dev,
453 struct iio_chan_spec const *chan,
454 int *val, int *val2, long mask)
456 struct mma8452_data *data = iio_priv(indio_dev);
461 case IIO_CHAN_INFO_RAW:
462 ret = iio_device_claim_direct_mode(indio_dev);
466 mutex_lock(&data->lock);
467 ret = mma8452_read(data, buffer);
468 mutex_unlock(&data->lock);
469 iio_device_release_direct_mode(indio_dev);
473 *val = sign_extend32(be16_to_cpu(
474 buffer[chan->scan_index]) >> chan->scan_type.shift,
475 chan->scan_type.realbits - 1);
478 case IIO_CHAN_INFO_SCALE:
479 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
480 *val = data->chip_info->mma_scales[i][0];
481 *val2 = data->chip_info->mma_scales[i][1];
483 return IIO_VAL_INT_PLUS_MICRO;
484 case IIO_CHAN_INFO_SAMP_FREQ:
485 i = mma8452_get_odr_index(data);
486 *val = mma8452_samp_freq[i][0];
487 *val2 = mma8452_samp_freq[i][1];
489 return IIO_VAL_INT_PLUS_MICRO;
490 case IIO_CHAN_INFO_CALIBBIAS:
491 ret = i2c_smbus_read_byte_data(data->client,
497 *val = sign_extend32(ret, 7);
500 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
501 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
502 ret = mma8452_read_hp_filter(data, val, val2);
510 return IIO_VAL_INT_PLUS_MICRO;
511 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
512 ret = mma8452_get_power_mode(data);
516 i = mma8452_get_odr_index(data);
518 *val = mma8452_os_ratio[ret][i];
525 static int mma8452_standby(struct mma8452_data *data)
527 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
528 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
531 static int mma8452_active(struct mma8452_data *data)
533 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
537 /* returns >0 if active, 0 if in standby and <0 on error */
538 static int mma8452_is_active(struct mma8452_data *data)
542 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
546 return reg & MMA8452_CTRL_ACTIVE;
549 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
554 mutex_lock(&data->lock);
556 is_active = mma8452_is_active(data);
562 /* config can only be changed when in standby */
564 ret = mma8452_standby(data);
569 ret = i2c_smbus_write_byte_data(data->client, reg, val);
574 ret = mma8452_active(data);
581 mutex_unlock(&data->lock);
586 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
590 reg = i2c_smbus_read_byte_data(data->client,
595 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
596 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
598 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
601 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
602 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
605 const struct mma_chip_info *chip = data->chip_info;
607 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
611 return !(val & MMA8452_FF_MT_CFG_OAE);
614 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
617 const struct mma_chip_info *chip = data->chip_info;
619 if ((state && mma8452_freefall_mode_enabled(data)) ||
620 (!state && !(mma8452_freefall_mode_enabled(data))))
623 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
628 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
629 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
630 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
631 val &= ~MMA8452_FF_MT_CFG_OAE;
633 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
634 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
635 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
636 val |= MMA8452_FF_MT_CFG_OAE;
639 return mma8452_change_config(data, chip->ev_cfg, val);
642 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
647 i = mma8452_get_hp_filter_index(data, val, val2);
651 reg = i2c_smbus_read_byte_data(data->client,
652 MMA8452_HP_FILTER_CUTOFF);
656 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
659 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
662 static int mma8452_write_raw(struct iio_dev *indio_dev,
663 struct iio_chan_spec const *chan,
664 int val, int val2, long mask)
666 struct mma8452_data *data = iio_priv(indio_dev);
669 ret = iio_device_claim_direct_mode(indio_dev);
674 case IIO_CHAN_INFO_SAMP_FREQ:
675 i = mma8452_get_samp_freq_index(data, val, val2);
680 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
681 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
683 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
686 case IIO_CHAN_INFO_SCALE:
687 i = mma8452_get_scale_index(data, val, val2);
693 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
696 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
699 case IIO_CHAN_INFO_CALIBBIAS:
700 if (val < -128 || val > 127) {
705 ret = mma8452_change_config(data,
706 MMA8452_OFF_X + chan->scan_index,
710 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
711 if (val == 0 && val2 == 0) {
712 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
714 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
715 ret = mma8452_set_hp_filter_frequency(data, val, val2);
720 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
724 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
725 ret = mma8452_get_odr_index(data);
727 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
728 if (mma8452_os_ratio[i][ret] == val) {
729 ret = mma8452_set_power_mode(data, i);
739 iio_device_release_direct_mode(indio_dev);
743 static int mma8452_read_thresh(struct iio_dev *indio_dev,
744 const struct iio_chan_spec *chan,
745 enum iio_event_type type,
746 enum iio_event_direction dir,
747 enum iio_event_info info,
750 struct mma8452_data *data = iio_priv(indio_dev);
751 int ret, us, power_mode;
754 case IIO_EV_INFO_VALUE:
755 ret = i2c_smbus_read_byte_data(data->client,
756 data->chip_info->ev_ths);
760 *val = ret & data->chip_info->ev_ths_mask;
764 case IIO_EV_INFO_PERIOD:
765 ret = i2c_smbus_read_byte_data(data->client,
766 data->chip_info->ev_count);
770 power_mode = mma8452_get_power_mode(data);
774 us = ret * mma8452_transient_time_step_us[power_mode][
775 mma8452_get_odr_index(data)];
776 *val = us / USEC_PER_SEC;
777 *val2 = us % USEC_PER_SEC;
779 return IIO_VAL_INT_PLUS_MICRO;
781 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
782 ret = i2c_smbus_read_byte_data(data->client,
783 MMA8452_TRANSIENT_CFG);
787 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
791 ret = mma8452_read_hp_filter(data, val, val2);
796 return IIO_VAL_INT_PLUS_MICRO;
803 static int mma8452_write_thresh(struct iio_dev *indio_dev,
804 const struct iio_chan_spec *chan,
805 enum iio_event_type type,
806 enum iio_event_direction dir,
807 enum iio_event_info info,
810 struct mma8452_data *data = iio_priv(indio_dev);
814 case IIO_EV_INFO_VALUE:
815 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
818 return mma8452_change_config(data, data->chip_info->ev_ths,
821 case IIO_EV_INFO_PERIOD:
822 ret = mma8452_get_power_mode(data);
826 steps = (val * USEC_PER_SEC + val2) /
827 mma8452_transient_time_step_us[ret][
828 mma8452_get_odr_index(data)];
830 if (steps < 0 || steps > 0xff)
833 return mma8452_change_config(data, data->chip_info->ev_count,
836 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
837 reg = i2c_smbus_read_byte_data(data->client,
838 MMA8452_TRANSIENT_CFG);
842 if (val == 0 && val2 == 0) {
843 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
845 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
846 ret = mma8452_set_hp_filter_frequency(data, val, val2);
851 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
858 static int mma8452_read_event_config(struct iio_dev *indio_dev,
859 const struct iio_chan_spec *chan,
860 enum iio_event_type type,
861 enum iio_event_direction dir)
863 struct mma8452_data *data = iio_priv(indio_dev);
864 const struct mma_chip_info *chip = data->chip_info;
868 case IIO_EV_DIR_FALLING:
869 return mma8452_freefall_mode_enabled(data);
870 case IIO_EV_DIR_RISING:
871 if (mma8452_freefall_mode_enabled(data))
874 ret = i2c_smbus_read_byte_data(data->client,
875 data->chip_info->ev_cfg);
879 return !!(ret & BIT(chan->scan_index +
880 chip->ev_cfg_chan_shift));
886 static int mma8452_write_event_config(struct iio_dev *indio_dev,
887 const struct iio_chan_spec *chan,
888 enum iio_event_type type,
889 enum iio_event_direction dir,
892 struct mma8452_data *data = iio_priv(indio_dev);
893 const struct mma_chip_info *chip = data->chip_info;
896 ret = mma8452_set_runtime_pm_state(data->client, state);
901 case IIO_EV_DIR_FALLING:
902 return mma8452_set_freefall_mode(data, state);
903 case IIO_EV_DIR_RISING:
904 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
909 if (mma8452_freefall_mode_enabled(data)) {
910 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
911 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
912 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
913 val |= MMA8452_FF_MT_CFG_OAE;
915 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
917 if (mma8452_freefall_mode_enabled(data))
920 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
923 val |= chip->ev_cfg_ele;
925 return mma8452_change_config(data, chip->ev_cfg, val);
931 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
933 struct mma8452_data *data = iio_priv(indio_dev);
934 s64 ts = iio_get_time_ns(indio_dev);
937 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
941 if (mma8452_freefall_mode_enabled(data)) {
942 iio_push_event(indio_dev,
943 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
944 IIO_MOD_X_AND_Y_AND_Z,
951 if (src & data->chip_info->ev_src_xe)
952 iio_push_event(indio_dev,
953 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
958 if (src & data->chip_info->ev_src_ye)
959 iio_push_event(indio_dev,
960 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
965 if (src & data->chip_info->ev_src_ze)
966 iio_push_event(indio_dev,
967 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
973 static irqreturn_t mma8452_interrupt(int irq, void *p)
975 struct iio_dev *indio_dev = p;
976 struct mma8452_data *data = iio_priv(indio_dev);
977 const struct mma_chip_info *chip = data->chip_info;
981 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
985 if (src & MMA8452_INT_DRDY) {
986 iio_trigger_poll_chained(indio_dev->trig);
990 if ((src & MMA8452_INT_TRANS &&
991 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
992 (src & MMA8452_INT_FF_MT &&
993 chip->ev_src == MMA8452_FF_MT_SRC)) {
994 mma8452_transient_interrupt(indio_dev);
1001 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1003 struct iio_poll_func *pf = p;
1004 struct iio_dev *indio_dev = pf->indio_dev;
1005 struct mma8452_data *data = iio_priv(indio_dev);
1006 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
1009 ret = mma8452_read(data, (__be16 *)buffer);
1013 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1014 iio_get_time_ns(indio_dev));
1017 iio_trigger_notify_done(indio_dev->trig);
1022 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1023 unsigned reg, unsigned writeval,
1027 struct mma8452_data *data = iio_priv(indio_dev);
1029 if (reg > MMA8452_MAX_REG)
1033 return mma8452_change_config(data, reg, writeval);
1035 ret = i2c_smbus_read_byte_data(data->client, reg);
1044 static const struct iio_event_spec mma8452_freefall_event[] = {
1046 .type = IIO_EV_TYPE_MAG,
1047 .dir = IIO_EV_DIR_FALLING,
1048 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1049 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1050 BIT(IIO_EV_INFO_PERIOD) |
1051 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1055 static const struct iio_event_spec mma8652_freefall_event[] = {
1057 .type = IIO_EV_TYPE_MAG,
1058 .dir = IIO_EV_DIR_FALLING,
1059 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1060 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1061 BIT(IIO_EV_INFO_PERIOD)
1065 static const struct iio_event_spec mma8452_transient_event[] = {
1067 .type = IIO_EV_TYPE_MAG,
1068 .dir = IIO_EV_DIR_RISING,
1069 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1070 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1071 BIT(IIO_EV_INFO_PERIOD) |
1072 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1076 static const struct iio_event_spec mma8452_motion_event[] = {
1078 .type = IIO_EV_TYPE_MAG,
1079 .dir = IIO_EV_DIR_RISING,
1080 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1081 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1082 BIT(IIO_EV_INFO_PERIOD)
1087 * Threshold is configured in fixed 8G/127 steps regardless of
1088 * currently selected scale for measurement.
1090 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1092 static struct attribute *mma8452_event_attributes[] = {
1093 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1097 static struct attribute_group mma8452_event_attribute_group = {
1098 .attrs = mma8452_event_attributes,
1101 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1102 .type = IIO_ACCEL, \
1104 .channel2 = modifier, \
1106 .event_spec = mma8452_freefall_event, \
1107 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1110 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1111 .type = IIO_ACCEL, \
1113 .channel2 = modifier, \
1115 .event_spec = mma8652_freefall_event, \
1116 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1119 #define MMA8452_CHANNEL(axis, idx, bits) { \
1120 .type = IIO_ACCEL, \
1122 .channel2 = IIO_MOD_##axis, \
1123 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1124 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1125 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1126 BIT(IIO_CHAN_INFO_SCALE) | \
1127 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1128 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1129 .scan_index = idx, \
1132 .realbits = (bits), \
1133 .storagebits = 16, \
1134 .shift = 16 - (bits), \
1135 .endianness = IIO_BE, \
1137 .event_spec = mma8452_transient_event, \
1138 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1141 #define MMA8652_CHANNEL(axis, idx, bits) { \
1142 .type = IIO_ACCEL, \
1144 .channel2 = IIO_MOD_##axis, \
1145 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1146 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1147 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1148 BIT(IIO_CHAN_INFO_SCALE) | \
1149 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1150 .scan_index = idx, \
1153 .realbits = (bits), \
1154 .storagebits = 16, \
1155 .shift = 16 - (bits), \
1156 .endianness = IIO_BE, \
1158 .event_spec = mma8452_motion_event, \
1159 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1162 static const struct iio_chan_spec mma8451_channels[] = {
1163 MMA8452_CHANNEL(X, idx_x, 14),
1164 MMA8452_CHANNEL(Y, idx_y, 14),
1165 MMA8452_CHANNEL(Z, idx_z, 14),
1166 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1167 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1170 static const struct iio_chan_spec mma8452_channels[] = {
1171 MMA8452_CHANNEL(X, idx_x, 12),
1172 MMA8452_CHANNEL(Y, idx_y, 12),
1173 MMA8452_CHANNEL(Z, idx_z, 12),
1174 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1175 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1178 static const struct iio_chan_spec mma8453_channels[] = {
1179 MMA8452_CHANNEL(X, idx_x, 10),
1180 MMA8452_CHANNEL(Y, idx_y, 10),
1181 MMA8452_CHANNEL(Z, idx_z, 10),
1182 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1183 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1186 static const struct iio_chan_spec mma8652_channels[] = {
1187 MMA8652_CHANNEL(X, idx_x, 12),
1188 MMA8652_CHANNEL(Y, idx_y, 12),
1189 MMA8652_CHANNEL(Z, idx_z, 12),
1190 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1191 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1194 static const struct iio_chan_spec mma8653_channels[] = {
1195 MMA8652_CHANNEL(X, idx_x, 10),
1196 MMA8652_CHANNEL(Y, idx_y, 10),
1197 MMA8652_CHANNEL(Z, idx_z, 10),
1198 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1199 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1211 static const struct mma_chip_info mma_chip_info_table[] = {
1213 .chip_id = MMA8451_DEVICE_ID,
1214 .channels = mma8451_channels,
1215 .num_channels = ARRAY_SIZE(mma8451_channels),
1217 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1218 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1220 * The userspace interface uses m/s^2 and we declare micro units
1221 * So scale factor for 12 bit here is given by:
1222 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1224 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1225 .ev_cfg = MMA8452_TRANSIENT_CFG,
1226 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1227 .ev_cfg_chan_shift = 1,
1228 .ev_src = MMA8452_TRANSIENT_SRC,
1229 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1230 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1231 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1232 .ev_ths = MMA8452_TRANSIENT_THS,
1233 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1234 .ev_count = MMA8452_TRANSIENT_COUNT,
1237 .chip_id = MMA8452_DEVICE_ID,
1238 .channels = mma8452_channels,
1239 .num_channels = ARRAY_SIZE(mma8452_channels),
1240 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1241 .ev_cfg = MMA8452_TRANSIENT_CFG,
1242 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1243 .ev_cfg_chan_shift = 1,
1244 .ev_src = MMA8452_TRANSIENT_SRC,
1245 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1246 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1247 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1248 .ev_ths = MMA8452_TRANSIENT_THS,
1249 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1250 .ev_count = MMA8452_TRANSIENT_COUNT,
1253 .chip_id = MMA8453_DEVICE_ID,
1254 .channels = mma8453_channels,
1255 .num_channels = ARRAY_SIZE(mma8453_channels),
1256 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1257 .ev_cfg = MMA8452_TRANSIENT_CFG,
1258 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1259 .ev_cfg_chan_shift = 1,
1260 .ev_src = MMA8452_TRANSIENT_SRC,
1261 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1262 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1263 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1264 .ev_ths = MMA8452_TRANSIENT_THS,
1265 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1266 .ev_count = MMA8452_TRANSIENT_COUNT,
1269 .chip_id = MMA8652_DEVICE_ID,
1270 .channels = mma8652_channels,
1271 .num_channels = ARRAY_SIZE(mma8652_channels),
1272 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1273 .ev_cfg = MMA8452_FF_MT_CFG,
1274 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1275 .ev_cfg_chan_shift = 3,
1276 .ev_src = MMA8452_FF_MT_SRC,
1277 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1278 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1279 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1280 .ev_ths = MMA8452_FF_MT_THS,
1281 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1282 .ev_count = MMA8452_FF_MT_COUNT,
1285 .chip_id = MMA8653_DEVICE_ID,
1286 .channels = mma8653_channels,
1287 .num_channels = ARRAY_SIZE(mma8653_channels),
1288 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1289 .ev_cfg = MMA8452_FF_MT_CFG,
1290 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1291 .ev_cfg_chan_shift = 3,
1292 .ev_src = MMA8452_FF_MT_SRC,
1293 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1294 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1295 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1296 .ev_ths = MMA8452_FF_MT_THS,
1297 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1298 .ev_count = MMA8452_FF_MT_COUNT,
1301 .chip_id = FXLS8471_DEVICE_ID,
1302 .channels = mma8451_channels,
1303 .num_channels = ARRAY_SIZE(mma8451_channels),
1304 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1305 .ev_cfg = MMA8452_TRANSIENT_CFG,
1306 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1307 .ev_cfg_chan_shift = 1,
1308 .ev_src = MMA8452_TRANSIENT_SRC,
1309 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1310 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1311 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1312 .ev_ths = MMA8452_TRANSIENT_THS,
1313 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1314 .ev_count = MMA8452_TRANSIENT_COUNT,
1318 static struct attribute *mma8452_attributes[] = {
1319 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1320 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1321 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1322 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1326 static const struct attribute_group mma8452_group = {
1327 .attrs = mma8452_attributes,
1330 static const struct iio_info mma8452_info = {
1331 .attrs = &mma8452_group,
1332 .read_raw = &mma8452_read_raw,
1333 .write_raw = &mma8452_write_raw,
1334 .event_attrs = &mma8452_event_attribute_group,
1335 .read_event_value = &mma8452_read_thresh,
1336 .write_event_value = &mma8452_write_thresh,
1337 .read_event_config = &mma8452_read_event_config,
1338 .write_event_config = &mma8452_write_event_config,
1339 .debugfs_reg_access = &mma8452_reg_access_dbg,
1340 .driver_module = THIS_MODULE,
1343 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1345 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1348 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1349 struct mma8452_data *data = iio_priv(indio_dev);
1352 ret = mma8452_set_runtime_pm_state(data->client, state);
1356 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1361 reg |= MMA8452_INT_DRDY;
1363 reg &= ~MMA8452_INT_DRDY;
1365 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1368 static const struct iio_trigger_ops mma8452_trigger_ops = {
1369 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1370 .validate_device = iio_trigger_validate_own_device,
1371 .owner = THIS_MODULE,
1374 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1376 struct mma8452_data *data = iio_priv(indio_dev);
1377 struct iio_trigger *trig;
1380 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1386 trig->dev.parent = &data->client->dev;
1387 trig->ops = &mma8452_trigger_ops;
1388 iio_trigger_set_drvdata(trig, indio_dev);
1390 ret = iio_trigger_register(trig);
1394 indio_dev->trig = trig;
1399 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1401 if (indio_dev->trig)
1402 iio_trigger_unregister(indio_dev->trig);
1405 static int mma8452_reset(struct i2c_client *client)
1410 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1411 MMA8452_CTRL_REG2_RST);
1415 for (i = 0; i < 10; i++) {
1416 usleep_range(100, 200);
1417 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1419 continue; /* I2C comm reset */
1422 if (!(ret & MMA8452_CTRL_REG2_RST))
1429 static const struct of_device_id mma8452_dt_ids[] = {
1430 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1431 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1432 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1433 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1434 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1435 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1438 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1440 static int mma8452_probe(struct i2c_client *client,
1441 const struct i2c_device_id *id)
1443 struct mma8452_data *data;
1444 struct iio_dev *indio_dev;
1446 const struct of_device_id *match;
1448 match = of_match_device(mma8452_dt_ids, &client->dev);
1450 dev_err(&client->dev, "unknown device model\n");
1454 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1458 data = iio_priv(indio_dev);
1459 data->client = client;
1460 mutex_init(&data->lock);
1461 data->chip_info = match->data;
1463 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1468 case MMA8451_DEVICE_ID:
1469 case MMA8452_DEVICE_ID:
1470 case MMA8453_DEVICE_ID:
1471 case MMA8652_DEVICE_ID:
1472 case MMA8653_DEVICE_ID:
1473 case FXLS8471_DEVICE_ID:
1474 if (ret == data->chip_info->chip_id)
1480 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1481 match->compatible, data->chip_info->chip_id);
1483 i2c_set_clientdata(client, indio_dev);
1484 indio_dev->info = &mma8452_info;
1485 indio_dev->name = id->name;
1486 indio_dev->dev.parent = &client->dev;
1487 indio_dev->modes = INDIO_DIRECT_MODE;
1488 indio_dev->channels = data->chip_info->channels;
1489 indio_dev->num_channels = data->chip_info->num_channels;
1490 indio_dev->available_scan_masks = mma8452_scan_masks;
1492 ret = mma8452_reset(client);
1496 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1497 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1503 * By default set transient threshold to max to avoid events if
1504 * enabling without configuring threshold.
1506 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1507 MMA8452_TRANSIENT_THS_MASK);
1513 * Although we enable the interrupt sources once and for
1514 * all here the event detection itself is not enabled until
1515 * userspace asks for it by mma8452_write_event_config()
1517 int supported_interrupts = MMA8452_INT_DRDY |
1520 int enabled_interrupts = MMA8452_INT_TRANS |
1524 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1526 if (irq2 == client->irq) {
1527 dev_dbg(&client->dev, "using interrupt line INT2\n");
1529 ret = i2c_smbus_write_byte_data(client,
1531 supported_interrupts);
1535 dev_dbg(&client->dev, "using interrupt line INT1\n");
1538 ret = i2c_smbus_write_byte_data(client,
1540 enabled_interrupts);
1544 ret = mma8452_trigger_setup(indio_dev);
1549 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1550 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1551 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1554 goto trigger_cleanup;
1556 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1557 mma8452_trigger_handler, NULL);
1559 goto trigger_cleanup;
1562 ret = devm_request_threaded_irq(&client->dev,
1564 NULL, mma8452_interrupt,
1565 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1566 client->name, indio_dev);
1568 goto buffer_cleanup;
1571 ret = pm_runtime_set_active(&client->dev);
1573 goto buffer_cleanup;
1575 pm_runtime_enable(&client->dev);
1576 pm_runtime_set_autosuspend_delay(&client->dev,
1577 MMA8452_AUTO_SUSPEND_DELAY_MS);
1578 pm_runtime_use_autosuspend(&client->dev);
1580 ret = iio_device_register(indio_dev);
1582 goto buffer_cleanup;
1584 ret = mma8452_set_freefall_mode(data, false);
1586 goto buffer_cleanup;
1591 iio_triggered_buffer_cleanup(indio_dev);
1594 mma8452_trigger_cleanup(indio_dev);
1599 static int mma8452_remove(struct i2c_client *client)
1601 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1603 iio_device_unregister(indio_dev);
1605 pm_runtime_disable(&client->dev);
1606 pm_runtime_set_suspended(&client->dev);
1607 pm_runtime_put_noidle(&client->dev);
1609 iio_triggered_buffer_cleanup(indio_dev);
1610 mma8452_trigger_cleanup(indio_dev);
1611 mma8452_standby(iio_priv(indio_dev));
1617 static int mma8452_runtime_suspend(struct device *dev)
1619 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1620 struct mma8452_data *data = iio_priv(indio_dev);
1623 mutex_lock(&data->lock);
1624 ret = mma8452_standby(data);
1625 mutex_unlock(&data->lock);
1627 dev_err(&data->client->dev, "powering off device failed\n");
1634 static int mma8452_runtime_resume(struct device *dev)
1636 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1637 struct mma8452_data *data = iio_priv(indio_dev);
1640 ret = mma8452_active(data);
1644 ret = mma8452_get_odr_index(data);
1645 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1647 usleep_range(sleep_val * 1000, 20000);
1649 msleep_interruptible(sleep_val);
1655 #ifdef CONFIG_PM_SLEEP
1656 static int mma8452_suspend(struct device *dev)
1658 return mma8452_standby(iio_priv(i2c_get_clientdata(
1659 to_i2c_client(dev))));
1662 static int mma8452_resume(struct device *dev)
1664 return mma8452_active(iio_priv(i2c_get_clientdata(
1665 to_i2c_client(dev))));
1669 static const struct dev_pm_ops mma8452_pm_ops = {
1670 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1671 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1672 mma8452_runtime_resume, NULL)
1675 static const struct i2c_device_id mma8452_id[] = {
1676 { "mma8451", mma8451 },
1677 { "mma8452", mma8452 },
1678 { "mma8453", mma8453 },
1679 { "mma8652", mma8652 },
1680 { "mma8653", mma8653 },
1681 { "fxls8471", fxls8471 },
1684 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1686 static struct i2c_driver mma8452_driver = {
1689 .of_match_table = of_match_ptr(mma8452_dt_ids),
1690 .pm = &mma8452_pm_ops,
1692 .probe = mma8452_probe,
1693 .remove = mma8452_remove,
1694 .id_table = mma8452_id,
1696 module_i2c_driver(mma8452_driver);
1698 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1699 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1700 MODULE_LICENSE("GPL");