2 * This file is part of STM32 ADC driver
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE.
16 * See the GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/timer/stm32-timer-trigger.h>
29 #include <linux/iio/trigger.h>
30 #include <linux/iio/trigger_consumer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/platform_device.h>
38 #include "stm32-adc-core.h"
40 /* STM32F4 - Registers for each ADC instance */
41 #define STM32F4_ADC_SR 0x00
42 #define STM32F4_ADC_CR1 0x04
43 #define STM32F4_ADC_CR2 0x08
44 #define STM32F4_ADC_SMPR1 0x0C
45 #define STM32F4_ADC_SMPR2 0x10
46 #define STM32F4_ADC_HTR 0x24
47 #define STM32F4_ADC_LTR 0x28
48 #define STM32F4_ADC_SQR1 0x2C
49 #define STM32F4_ADC_SQR2 0x30
50 #define STM32F4_ADC_SQR3 0x34
51 #define STM32F4_ADC_JSQR 0x38
52 #define STM32F4_ADC_JDR1 0x3C
53 #define STM32F4_ADC_JDR2 0x40
54 #define STM32F4_ADC_JDR3 0x44
55 #define STM32F4_ADC_JDR4 0x48
56 #define STM32F4_ADC_DR 0x4C
58 /* STM32F4_ADC_SR - bit fields */
59 #define STM32F4_STRT BIT(4)
60 #define STM32F4_EOC BIT(1)
62 /* STM32F4_ADC_CR1 - bit fields */
63 #define STM32F4_RES_SHIFT 24
64 #define STM32F4_RES_MASK GENMASK(25, 24)
65 #define STM32F4_SCAN BIT(8)
66 #define STM32F4_EOCIE BIT(5)
68 /* STM32F4_ADC_CR2 - bit fields */
69 #define STM32F4_SWSTART BIT(30)
70 #define STM32F4_EXTEN_SHIFT 28
71 #define STM32F4_EXTEN_MASK GENMASK(29, 28)
72 #define STM32F4_EXTSEL_SHIFT 24
73 #define STM32F4_EXTSEL_MASK GENMASK(27, 24)
74 #define STM32F4_EOCS BIT(10)
75 #define STM32F4_DDS BIT(9)
76 #define STM32F4_DMA BIT(8)
77 #define STM32F4_ADON BIT(0)
79 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
80 #define STM32_ADC_TIMEOUT_US 100000
81 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
83 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
85 /* External trigger enable */
86 enum stm32_adc_exten {
88 STM32_EXTEN_HWTRIG_RISING_EDGE,
89 STM32_EXTEN_HWTRIG_FALLING_EDGE,
90 STM32_EXTEN_HWTRIG_BOTH_EDGES,
93 /* extsel - trigger mux selection value */
94 enum stm32_adc_extsel {
114 * struct stm32_adc_trig_info - ADC trigger info
115 * @name: name of the trigger, corresponding to its source
116 * @extsel: trigger selection
118 struct stm32_adc_trig_info {
120 enum stm32_adc_extsel extsel;
124 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
125 * @reg: register offset
126 * @mask: bitfield mask
129 struct stm32_adc_regs {
136 * struct stm32_adc - private data of each ADC IIO instance
137 * @common: reference to ADC block common data
138 * @offset: ADC instance register offset in ADC block
139 * @completion: end of single conversion completion
140 * @buffer: data buffer
141 * @clk: clock for this adc instance
142 * @irq: interrupt for this adc instance
144 * @bufi: data buffer index
145 * @num_conv: expected number of scan conversions
146 * @res: data resolution (e.g. RES bitfield value)
147 * @trigger_polarity: external trigger polarity (e.g. exten)
148 * @dma_chan: dma channel
149 * @rx_buf: dma rx buffer cpu address
150 * @rx_dma_buf: dma rx buffer bus address
151 * @rx_buf_sz: dma rx buffer size
154 struct stm32_adc_common *common;
156 struct completion completion;
157 u16 buffer[STM32_ADC_MAX_SQ];
160 spinlock_t lock; /* interrupt lock */
162 unsigned int num_conv;
164 u32 trigger_polarity;
165 struct dma_chan *dma_chan;
167 dma_addr_t rx_dma_buf;
168 unsigned int rx_buf_sz;
172 * struct stm32_adc_chan_spec - specification of stm32 adc channel
173 * @type: IIO channel type
174 * @channel: channel number (single ended)
175 * @name: channel name (single ended)
177 struct stm32_adc_chan_spec {
178 enum iio_chan_type type;
183 /* Input definitions common for all STM32F4 instances */
184 static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
185 { IIO_VOLTAGE, 0, "in0" },
186 { IIO_VOLTAGE, 1, "in1" },
187 { IIO_VOLTAGE, 2, "in2" },
188 { IIO_VOLTAGE, 3, "in3" },
189 { IIO_VOLTAGE, 4, "in4" },
190 { IIO_VOLTAGE, 5, "in5" },
191 { IIO_VOLTAGE, 6, "in6" },
192 { IIO_VOLTAGE, 7, "in7" },
193 { IIO_VOLTAGE, 8, "in8" },
194 { IIO_VOLTAGE, 9, "in9" },
195 { IIO_VOLTAGE, 10, "in10" },
196 { IIO_VOLTAGE, 11, "in11" },
197 { IIO_VOLTAGE, 12, "in12" },
198 { IIO_VOLTAGE, 13, "in13" },
199 { IIO_VOLTAGE, 14, "in14" },
200 { IIO_VOLTAGE, 15, "in15" },
203 static const unsigned int stm32f4_adc_resolutions[] = {
204 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
209 * stm32f4_sq - describe regular sequence registers
210 * - L: sequence len (register & bit field)
211 * - SQ1..SQ16: sequence entries (register & bit field)
213 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
214 /* L: len bit field description to be kept as first element */
215 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
216 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
217 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
218 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
219 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
220 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
221 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
222 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
223 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
224 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
225 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
226 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
227 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
228 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
229 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
230 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
231 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
232 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
235 /* STM32F4 external trigger sources for all instances */
236 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
237 { TIM1_CH1, STM32_EXT0 },
238 { TIM1_CH2, STM32_EXT1 },
239 { TIM1_CH3, STM32_EXT2 },
240 { TIM2_CH2, STM32_EXT3 },
241 { TIM2_CH3, STM32_EXT4 },
242 { TIM2_CH4, STM32_EXT5 },
243 { TIM2_TRGO, STM32_EXT6 },
244 { TIM3_CH1, STM32_EXT7 },
245 { TIM3_TRGO, STM32_EXT8 },
246 { TIM4_CH4, STM32_EXT9 },
247 { TIM5_CH1, STM32_EXT10 },
248 { TIM5_CH2, STM32_EXT11 },
249 { TIM5_CH3, STM32_EXT12 },
250 { TIM8_CH1, STM32_EXT13 },
251 { TIM8_TRGO, STM32_EXT14 },
256 * STM32 ADC registers access routines
257 * @adc: stm32 adc instance
258 * @reg: reg offset in adc instance
260 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
261 * for adc1, adc2 and adc3.
263 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
265 return readl_relaxed(adc->common->base + adc->offset + reg);
268 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
270 return readw_relaxed(adc->common->base + adc->offset + reg);
273 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
275 writel_relaxed(val, adc->common->base + adc->offset + reg);
278 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
282 spin_lock_irqsave(&adc->lock, flags);
283 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
284 spin_unlock_irqrestore(&adc->lock, flags);
287 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
291 spin_lock_irqsave(&adc->lock, flags);
292 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
293 spin_unlock_irqrestore(&adc->lock, flags);
297 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
298 * @adc: stm32 adc instance
300 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
302 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
306 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
307 * @adc: stm32 adc instance
309 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
311 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
314 static void stm32_adc_set_res(struct stm32_adc *adc)
316 u32 val = stm32_adc_readl(adc, STM32F4_ADC_CR1);
318 val = (val & ~STM32F4_RES_MASK) | (adc->res << STM32F4_RES_SHIFT);
319 stm32_adc_writel(adc, STM32F4_ADC_CR1, val);
323 * stm32_adc_start_conv() - Start conversions for regular channels.
324 * @adc: stm32 adc instance
325 * @dma: use dma to transfer conversion result
327 * Start conversions for regular channels.
328 * Also take care of normal or DMA mode. Circular DMA may be used for regular
329 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
330 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
332 static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma)
334 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
337 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
338 STM32F4_DMA | STM32F4_DDS);
340 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
342 /* Wait for Power-up time (tSTAB from datasheet) */
345 /* Software start ? (e.g. trigger detection disabled ?) */
346 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
347 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
350 static void stm32_adc_stop_conv(struct stm32_adc *adc)
352 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
353 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
355 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
356 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
357 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
361 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
362 * @indio_dev: IIO device
363 * @scan_mask: channels to be converted
365 * Conversion sequence :
366 * Configure ADC scan sequence based on selected channels in scan_mask.
367 * Add channels to SQR registers, from scan_mask LSB to MSB, then
368 * program sequence len.
370 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
371 const unsigned long *scan_mask)
373 struct stm32_adc *adc = iio_priv(indio_dev);
374 const struct iio_chan_spec *chan;
378 for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
379 chan = indio_dev->channels + bit;
381 * Assign one channel per SQ entry in regular
382 * sequence, starting with SQ1.
385 if (i > STM32_ADC_MAX_SQ)
388 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
389 __func__, chan->channel, i);
391 val = stm32_adc_readl(adc, stm32f4_sq[i].reg);
392 val &= ~stm32f4_sq[i].mask;
393 val |= chan->channel << stm32f4_sq[i].shift;
394 stm32_adc_writel(adc, stm32f4_sq[i].reg, val);
401 val = stm32_adc_readl(adc, stm32f4_sq[0].reg);
402 val &= ~stm32f4_sq[0].mask;
403 val |= ((i - 1) << stm32f4_sq[0].shift);
404 stm32_adc_writel(adc, stm32f4_sq[0].reg, val);
410 * stm32_adc_get_trig_extsel() - Get external trigger selection
413 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
415 static int stm32_adc_get_trig_extsel(struct iio_trigger *trig)
419 /* lookup triggers registered by stm32 timer trigger driver */
420 for (i = 0; stm32f4_adc_trigs[i].name; i++) {
422 * Checking both stm32 timer trigger type and trig name
423 * should be safe against arbitrary trigger names.
425 if (is_stm32_timer_trigger(trig) &&
426 !strcmp(stm32f4_adc_trigs[i].name, trig->name)) {
427 return stm32f4_adc_trigs[i].extsel;
435 * stm32_adc_set_trig() - Set a regular trigger
436 * @indio_dev: IIO device
439 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
440 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
441 * - if HW trigger enabled, set source & polarity
443 static int stm32_adc_set_trig(struct iio_dev *indio_dev,
444 struct iio_trigger *trig)
446 struct stm32_adc *adc = iio_priv(indio_dev);
447 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
452 ret = stm32_adc_get_trig_extsel(trig);
456 /* set trigger source and polarity (default to rising edge) */
458 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
461 spin_lock_irqsave(&adc->lock, flags);
462 val = stm32_adc_readl(adc, STM32F4_ADC_CR2);
463 val &= ~(STM32F4_EXTEN_MASK | STM32F4_EXTSEL_MASK);
464 val |= exten << STM32F4_EXTEN_SHIFT;
465 val |= extsel << STM32F4_EXTSEL_SHIFT;
466 stm32_adc_writel(adc, STM32F4_ADC_CR2, val);
467 spin_unlock_irqrestore(&adc->lock, flags);
472 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
473 const struct iio_chan_spec *chan,
476 struct stm32_adc *adc = iio_priv(indio_dev);
478 adc->trigger_polarity = type;
483 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
484 const struct iio_chan_spec *chan)
486 struct stm32_adc *adc = iio_priv(indio_dev);
488 return adc->trigger_polarity;
491 static const char * const stm32_trig_pol_items[] = {
492 "rising-edge", "falling-edge", "both-edges",
495 static const struct iio_enum stm32_adc_trig_pol = {
496 .items = stm32_trig_pol_items,
497 .num_items = ARRAY_SIZE(stm32_trig_pol_items),
498 .get = stm32_adc_get_trig_pol,
499 .set = stm32_adc_set_trig_pol,
503 * stm32_adc_single_conv() - Performs a single conversion
504 * @indio_dev: IIO device
506 * @res: conversion result
508 * The function performs a single conversion on a given channel:
509 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
511 * - Start conversion, then wait for interrupt completion.
513 static int stm32_adc_single_conv(struct iio_dev *indio_dev,
514 const struct iio_chan_spec *chan,
517 struct stm32_adc *adc = iio_priv(indio_dev);
522 reinit_completion(&adc->completion);
526 /* Program chan number in regular sequence (SQ1) */
527 val = stm32_adc_readl(adc, stm32f4_sq[1].reg);
528 val &= ~stm32f4_sq[1].mask;
529 val |= chan->channel << stm32f4_sq[1].shift;
530 stm32_adc_writel(adc, stm32f4_sq[1].reg, val);
532 /* Set regular sequence len (0 for 1 conversion) */
533 stm32_adc_clr_bits(adc, stm32f4_sq[0].reg, stm32f4_sq[0].mask);
535 /* Trigger detection disabled (conversion can be launched in SW) */
536 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
538 stm32_adc_conv_irq_enable(adc);
540 stm32_adc_start_conv(adc, false);
542 timeout = wait_for_completion_interruptible_timeout(
543 &adc->completion, STM32_ADC_TIMEOUT);
546 } else if (timeout < 0) {
549 *res = adc->buffer[0];
553 stm32_adc_stop_conv(adc);
555 stm32_adc_conv_irq_disable(adc);
560 static int stm32_adc_read_raw(struct iio_dev *indio_dev,
561 struct iio_chan_spec const *chan,
562 int *val, int *val2, long mask)
564 struct stm32_adc *adc = iio_priv(indio_dev);
568 case IIO_CHAN_INFO_RAW:
569 ret = iio_device_claim_direct_mode(indio_dev);
572 if (chan->type == IIO_VOLTAGE)
573 ret = stm32_adc_single_conv(indio_dev, chan, val);
576 iio_device_release_direct_mode(indio_dev);
579 case IIO_CHAN_INFO_SCALE:
580 *val = adc->common->vref_mv;
581 *val2 = chan->scan_type.realbits;
582 return IIO_VAL_FRACTIONAL_LOG2;
589 static irqreturn_t stm32_adc_isr(int irq, void *data)
591 struct stm32_adc *adc = data;
592 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
593 u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR);
595 if (status & STM32F4_EOC) {
596 /* Reading DR also clears EOC status flag */
597 adc->buffer[adc->bufi] = stm32_adc_readw(adc, STM32F4_ADC_DR);
598 if (iio_buffer_enabled(indio_dev)) {
600 if (adc->bufi >= adc->num_conv) {
601 stm32_adc_conv_irq_disable(adc);
602 iio_trigger_poll(indio_dev->trig);
605 complete(&adc->completion);
614 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
615 * @indio_dev: IIO device
618 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
619 * driver, -EINVAL otherwise.
621 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
622 struct iio_trigger *trig)
624 return stm32_adc_get_trig_extsel(trig) < 0 ? -EINVAL : 0;
627 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
629 struct stm32_adc *adc = iio_priv(indio_dev);
630 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
633 * dma cyclic transfers are used, buffer is split into two periods.
635 * - always one buffer (period) dma is working on
636 * - one buffer (period) driver can push with iio_trigger_poll().
638 watermark = min(watermark, val * (unsigned)(sizeof(u16)));
639 adc->rx_buf_sz = watermark * 2;
644 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
645 const unsigned long *scan_mask)
647 struct stm32_adc *adc = iio_priv(indio_dev);
650 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
652 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
659 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
660 const struct of_phandle_args *iiospec)
664 for (i = 0; i < indio_dev->num_channels; i++)
665 if (indio_dev->channels[i].channel == iiospec->args[0])
672 * stm32_adc_debugfs_reg_access - read or write register value
674 * To read a value from an ADC register:
675 * echo [ADC reg offset] > direct_reg_access
676 * cat direct_reg_access
678 * To write a value in a ADC register:
679 * echo [ADC_reg_offset] [value] > direct_reg_access
681 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
682 unsigned reg, unsigned writeval,
685 struct stm32_adc *adc = iio_priv(indio_dev);
688 stm32_adc_writel(adc, reg, writeval);
690 *readval = stm32_adc_readl(adc, reg);
695 static const struct iio_info stm32_adc_iio_info = {
696 .read_raw = stm32_adc_read_raw,
697 .validate_trigger = stm32_adc_validate_trigger,
698 .hwfifo_set_watermark = stm32_adc_set_watermark,
699 .update_scan_mode = stm32_adc_update_scan_mode,
700 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
701 .of_xlate = stm32_adc_of_xlate,
702 .driver_module = THIS_MODULE,
705 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
707 struct dma_tx_state state;
708 enum dma_status status;
710 status = dmaengine_tx_status(adc->dma_chan,
711 adc->dma_chan->cookie,
713 if (status == DMA_IN_PROGRESS) {
714 /* Residue is size in bytes from end of buffer */
715 unsigned int i = adc->rx_buf_sz - state.residue;
718 /* Return available bytes */
720 size = i - adc->bufi;
722 size = adc->rx_buf_sz + i - adc->bufi;
730 static void stm32_adc_dma_buffer_done(void *data)
732 struct iio_dev *indio_dev = data;
734 iio_trigger_poll_chained(indio_dev->trig);
737 static int stm32_adc_dma_start(struct iio_dev *indio_dev)
739 struct stm32_adc *adc = iio_priv(indio_dev);
740 struct dma_async_tx_descriptor *desc;
747 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
748 adc->rx_buf_sz, adc->rx_buf_sz / 2);
750 /* Prepare a DMA cyclic transaction */
751 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
753 adc->rx_buf_sz, adc->rx_buf_sz / 2,
759 desc->callback = stm32_adc_dma_buffer_done;
760 desc->callback_param = indio_dev;
762 cookie = dmaengine_submit(desc);
763 ret = dma_submit_error(cookie);
765 dmaengine_terminate_all(adc->dma_chan);
769 /* Issue pending DMA requests */
770 dma_async_issue_pending(adc->dma_chan);
775 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
777 struct stm32_adc *adc = iio_priv(indio_dev);
780 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
782 dev_err(&indio_dev->dev, "Can't set trigger\n");
786 ret = stm32_adc_dma_start(indio_dev);
788 dev_err(&indio_dev->dev, "Can't start dma\n");
792 ret = iio_triggered_buffer_postenable(indio_dev);
796 /* Reset adc buffer index */
800 stm32_adc_conv_irq_enable(adc);
802 stm32_adc_start_conv(adc, !!adc->dma_chan);
808 dmaengine_terminate_all(adc->dma_chan);
810 stm32_adc_set_trig(indio_dev, NULL);
815 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
817 struct stm32_adc *adc = iio_priv(indio_dev);
820 stm32_adc_stop_conv(adc);
822 stm32_adc_conv_irq_disable(adc);
824 ret = iio_triggered_buffer_predisable(indio_dev);
826 dev_err(&indio_dev->dev, "predisable failed\n");
829 dmaengine_terminate_all(adc->dma_chan);
831 if (stm32_adc_set_trig(indio_dev, NULL))
832 dev_err(&indio_dev->dev, "Can't clear trigger\n");
837 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
838 .postenable = &stm32_adc_buffer_postenable,
839 .predisable = &stm32_adc_buffer_predisable,
842 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
844 struct iio_poll_func *pf = p;
845 struct iio_dev *indio_dev = pf->indio_dev;
846 struct stm32_adc *adc = iio_priv(indio_dev);
848 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
850 if (!adc->dma_chan) {
851 /* reset buffer index */
853 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
856 int residue = stm32_adc_dma_residue(adc);
858 while (residue >= indio_dev->scan_bytes) {
859 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
861 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
863 residue -= indio_dev->scan_bytes;
864 adc->bufi += indio_dev->scan_bytes;
865 if (adc->bufi >= adc->rx_buf_sz)
870 iio_trigger_notify_done(indio_dev->trig);
872 /* re-enable eoc irq */
874 stm32_adc_conv_irq_enable(adc);
879 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
880 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
882 .name = "trigger_polarity_available",
883 .shared = IIO_SHARED_BY_ALL,
884 .read = iio_enum_available_read,
885 .private = (uintptr_t)&stm32_adc_trig_pol,
890 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
892 struct device_node *node = indio_dev->dev.of_node;
893 struct stm32_adc *adc = iio_priv(indio_dev);
897 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
898 res = stm32f4_adc_resolutions[0];
900 for (i = 0; i < ARRAY_SIZE(stm32f4_adc_resolutions); i++)
901 if (res == stm32f4_adc_resolutions[i])
903 if (i >= ARRAY_SIZE(stm32f4_adc_resolutions)) {
904 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
908 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
914 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
915 struct iio_chan_spec *chan,
916 const struct stm32_adc_chan_spec *channel,
919 struct stm32_adc *adc = iio_priv(indio_dev);
921 chan->type = channel->type;
922 chan->channel = channel->channel;
923 chan->datasheet_name = channel->name;
924 chan->scan_index = scan_index;
926 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
927 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
928 chan->scan_type.sign = 'u';
929 chan->scan_type.realbits = stm32f4_adc_resolutions[adc->res];
930 chan->scan_type.storagebits = 16;
931 chan->ext_info = stm32_adc_ext_info;
934 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
936 struct device_node *node = indio_dev->dev.of_node;
937 struct property *prop;
939 struct iio_chan_spec *channels;
940 int scan_index = 0, num_channels;
943 num_channels = of_property_count_u32_elems(node, "st,adc-channels");
944 if (num_channels < 0 ||
945 num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
946 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
947 return num_channels < 0 ? num_channels : -EINVAL;
950 channels = devm_kcalloc(&indio_dev->dev, num_channels,
951 sizeof(struct iio_chan_spec), GFP_KERNEL);
955 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
956 if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
957 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
960 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
961 &stm32f4_adc123_channels[val],
966 indio_dev->num_channels = scan_index;
967 indio_dev->channels = channels;
972 static int stm32_adc_dma_request(struct iio_dev *indio_dev)
974 struct stm32_adc *adc = iio_priv(indio_dev);
975 struct dma_slave_config config;
978 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
982 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
983 STM32_DMA_BUFFER_SIZE,
984 &adc->rx_dma_buf, GFP_KERNEL);
990 /* Configure DMA channel to read data register */
991 memset(&config, 0, sizeof(config));
992 config.src_addr = (dma_addr_t)adc->common->phys_base;
993 config.src_addr += adc->offset + STM32F4_ADC_DR;
994 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
996 ret = dmaengine_slave_config(adc->dma_chan, &config);
1003 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1004 adc->rx_buf, adc->rx_dma_buf);
1006 dma_release_channel(adc->dma_chan);
1011 static int stm32_adc_probe(struct platform_device *pdev)
1013 struct iio_dev *indio_dev;
1014 struct stm32_adc *adc;
1017 if (!pdev->dev.of_node)
1020 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1024 adc = iio_priv(indio_dev);
1025 adc->common = dev_get_drvdata(pdev->dev.parent);
1026 spin_lock_init(&adc->lock);
1027 init_completion(&adc->completion);
1029 indio_dev->name = dev_name(&pdev->dev);
1030 indio_dev->dev.parent = &pdev->dev;
1031 indio_dev->dev.of_node = pdev->dev.of_node;
1032 indio_dev->info = &stm32_adc_iio_info;
1033 indio_dev->modes = INDIO_DIRECT_MODE;
1035 platform_set_drvdata(pdev, adc);
1037 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1039 dev_err(&pdev->dev, "missing reg property\n");
1043 adc->irq = platform_get_irq(pdev, 0);
1045 dev_err(&pdev->dev, "failed to get irq\n");
1049 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1050 0, pdev->name, adc);
1052 dev_err(&pdev->dev, "failed to request IRQ\n");
1056 adc->clk = devm_clk_get(&pdev->dev, NULL);
1057 if (IS_ERR(adc->clk)) {
1058 dev_err(&pdev->dev, "Can't get clock\n");
1059 return PTR_ERR(adc->clk);
1062 ret = clk_prepare_enable(adc->clk);
1064 dev_err(&pdev->dev, "clk enable failed\n");
1068 ret = stm32_adc_of_get_resolution(indio_dev);
1070 goto err_clk_disable;
1071 stm32_adc_set_res(adc);
1073 ret = stm32_adc_chan_of_init(indio_dev);
1075 goto err_clk_disable;
1077 ret = stm32_adc_dma_request(indio_dev);
1079 goto err_clk_disable;
1081 ret = iio_triggered_buffer_setup(indio_dev,
1082 &iio_pollfunc_store_time,
1083 &stm32_adc_trigger_handler,
1084 &stm32_adc_buffer_setup_ops);
1086 dev_err(&pdev->dev, "buffer setup failed\n");
1087 goto err_dma_disable;
1090 ret = iio_device_register(indio_dev);
1092 dev_err(&pdev->dev, "iio dev register failed\n");
1093 goto err_buffer_cleanup;
1099 iio_triggered_buffer_cleanup(indio_dev);
1102 if (adc->dma_chan) {
1103 dma_free_coherent(adc->dma_chan->device->dev,
1104 STM32_DMA_BUFFER_SIZE,
1105 adc->rx_buf, adc->rx_dma_buf);
1106 dma_release_channel(adc->dma_chan);
1109 clk_disable_unprepare(adc->clk);
1114 static int stm32_adc_remove(struct platform_device *pdev)
1116 struct stm32_adc *adc = platform_get_drvdata(pdev);
1117 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1119 iio_device_unregister(indio_dev);
1120 iio_triggered_buffer_cleanup(indio_dev);
1121 if (adc->dma_chan) {
1122 dma_free_coherent(adc->dma_chan->device->dev,
1123 STM32_DMA_BUFFER_SIZE,
1124 adc->rx_buf, adc->rx_dma_buf);
1125 dma_release_channel(adc->dma_chan);
1127 clk_disable_unprepare(adc->clk);
1132 static const struct of_device_id stm32_adc_of_match[] = {
1133 { .compatible = "st,stm32f4-adc" },
1136 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
1138 static struct platform_driver stm32_adc_driver = {
1139 .probe = stm32_adc_probe,
1140 .remove = stm32_adc_remove,
1142 .name = "stm32-adc",
1143 .of_match_table = stm32_adc_of_match,
1146 module_platform_driver(stm32_adc_driver);
1148 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
1149 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
1150 MODULE_LICENSE("GPL v2");
1151 MODULE_ALIAS("platform:stm32-adc");