2 * Texas Instruments ADS7950 SPI ADC driver
4 * Copyright 2016 David Lechner <david@lechnology.com>
6 * Based on iio/ad7923.c:
7 * Copyright 2011 Analog Devices Inc
8 * Copyright 2012 CS Systemes d'Information
10 * And also on hwmon/ads79xx.c
11 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation version 2.
18 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
19 * kind, whether express or implied; without even the implied warranty
20 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
24 #include <linux/bitops.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/spi/spi.h>
34 #include <linux/iio/buffer.h>
35 #include <linux/iio/iio.h>
36 #include <linux/iio/sysfs.h>
37 #include <linux/iio/trigger_consumer.h>
38 #include <linux/iio/triggered_buffer.h>
40 #define TI_ADS7950_CR_MANUAL BIT(12)
41 #define TI_ADS7950_CR_WRITE BIT(11)
42 #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)
43 #define TI_ADS7950_CR_RANGE_5V BIT(6)
45 #define TI_ADS7950_MAX_CHAN 16
47 #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
49 /* val = value, dec = left shift, bits = number of bits of the mask */
50 #define TI_ADS7950_EXTRACT(val, dec, bits) \
51 (((val) >> (dec)) & ((1 << (bits)) - 1))
53 struct ti_ads7950_state {
54 struct spi_device *spi;
55 struct spi_transfer ring_xfer[TI_ADS7950_MAX_CHAN + 2];
56 struct spi_transfer scan_single_xfer[3];
57 struct spi_message ring_msg;
58 struct spi_message scan_single_msg;
60 struct regulator *reg;
62 unsigned int settings;
65 * DMA (thus cache coherency maintenance) requires the
66 * transfer buffers to live in their own cache lines.
68 __be16 rx_buf[TI_ADS7950_MAX_CHAN + TI_ADS7950_TIMESTAMP_SIZE]
69 ____cacheline_aligned;
70 __be16 tx_buf[TI_ADS7950_MAX_CHAN];
73 struct ti_ads7950_chip_info {
74 const struct iio_chan_spec *channels;
75 unsigned int num_channels;
93 #define TI_ADS7950_V_CHAN(index, bits) \
95 .type = IIO_VOLTAGE, \
98 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
99 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
101 .datasheet_name = "CH##index", \
102 .scan_index = index, \
107 .shift = 12 - (bits), \
108 .endianness = IIO_BE, \
112 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
113 const struct iio_chan_spec name ## _channels[] = { \
114 TI_ADS7950_V_CHAN(0, bits), \
115 TI_ADS7950_V_CHAN(1, bits), \
116 TI_ADS7950_V_CHAN(2, bits), \
117 TI_ADS7950_V_CHAN(3, bits), \
118 IIO_CHAN_SOFT_TIMESTAMP(4), \
121 #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
122 const struct iio_chan_spec name ## _channels[] = { \
123 TI_ADS7950_V_CHAN(0, bits), \
124 TI_ADS7950_V_CHAN(1, bits), \
125 TI_ADS7950_V_CHAN(2, bits), \
126 TI_ADS7950_V_CHAN(3, bits), \
127 TI_ADS7950_V_CHAN(4, bits), \
128 TI_ADS7950_V_CHAN(5, bits), \
129 TI_ADS7950_V_CHAN(6, bits), \
130 TI_ADS7950_V_CHAN(7, bits), \
131 IIO_CHAN_SOFT_TIMESTAMP(8), \
134 #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
135 const struct iio_chan_spec name ## _channels[] = { \
136 TI_ADS7950_V_CHAN(0, bits), \
137 TI_ADS7950_V_CHAN(1, bits), \
138 TI_ADS7950_V_CHAN(2, bits), \
139 TI_ADS7950_V_CHAN(3, bits), \
140 TI_ADS7950_V_CHAN(4, bits), \
141 TI_ADS7950_V_CHAN(5, bits), \
142 TI_ADS7950_V_CHAN(6, bits), \
143 TI_ADS7950_V_CHAN(7, bits), \
144 TI_ADS7950_V_CHAN(8, bits), \
145 TI_ADS7950_V_CHAN(9, bits), \
146 TI_ADS7950_V_CHAN(10, bits), \
147 TI_ADS7950_V_CHAN(11, bits), \
148 IIO_CHAN_SOFT_TIMESTAMP(12), \
151 #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
152 const struct iio_chan_spec name ## _channels[] = { \
153 TI_ADS7950_V_CHAN(0, bits), \
154 TI_ADS7950_V_CHAN(1, bits), \
155 TI_ADS7950_V_CHAN(2, bits), \
156 TI_ADS7950_V_CHAN(3, bits), \
157 TI_ADS7950_V_CHAN(4, bits), \
158 TI_ADS7950_V_CHAN(5, bits), \
159 TI_ADS7950_V_CHAN(6, bits), \
160 TI_ADS7950_V_CHAN(7, bits), \
161 TI_ADS7950_V_CHAN(8, bits), \
162 TI_ADS7950_V_CHAN(9, bits), \
163 TI_ADS7950_V_CHAN(10, bits), \
164 TI_ADS7950_V_CHAN(11, bits), \
165 TI_ADS7950_V_CHAN(12, bits), \
166 TI_ADS7950_V_CHAN(13, bits), \
167 TI_ADS7950_V_CHAN(14, bits), \
168 TI_ADS7950_V_CHAN(15, bits), \
169 IIO_CHAN_SOFT_TIMESTAMP(16), \
172 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
173 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
174 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
175 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
176 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
177 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
178 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
179 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
180 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
181 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
182 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
183 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
185 static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
187 .channels = ti_ads7950_channels,
188 .num_channels = ARRAY_SIZE(ti_ads7950_channels),
191 .channels = ti_ads7951_channels,
192 .num_channels = ARRAY_SIZE(ti_ads7951_channels),
195 .channels = ti_ads7952_channels,
196 .num_channels = ARRAY_SIZE(ti_ads7952_channels),
199 .channels = ti_ads7953_channels,
200 .num_channels = ARRAY_SIZE(ti_ads7953_channels),
203 .channels = ti_ads7954_channels,
204 .num_channels = ARRAY_SIZE(ti_ads7954_channels),
207 .channels = ti_ads7955_channels,
208 .num_channels = ARRAY_SIZE(ti_ads7955_channels),
211 .channels = ti_ads7956_channels,
212 .num_channels = ARRAY_SIZE(ti_ads7956_channels),
215 .channels = ti_ads7957_channels,
216 .num_channels = ARRAY_SIZE(ti_ads7957_channels),
219 .channels = ti_ads7958_channels,
220 .num_channels = ARRAY_SIZE(ti_ads7958_channels),
223 .channels = ti_ads7959_channels,
224 .num_channels = ARRAY_SIZE(ti_ads7959_channels),
227 .channels = ti_ads7960_channels,
228 .num_channels = ARRAY_SIZE(ti_ads7960_channels),
231 .channels = ti_ads7961_channels,
232 .num_channels = ARRAY_SIZE(ti_ads7961_channels),
237 * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
240 static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
241 const unsigned long *active_scan_mask)
243 struct ti_ads7950_state *st = iio_priv(indio_dev);
247 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
248 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(i) | st->settings;
249 st->tx_buf[len++] = cpu_to_be16(cmd);
252 /* Data for the 1st channel is not returned until the 3rd transfer */
254 for (i = 0; i < len; i++) {
256 st->ring_xfer[i].tx_buf = &st->tx_buf[i];
258 st->ring_xfer[i].rx_buf = &st->rx_buf[i - 2];
259 st->ring_xfer[i].len = 2;
260 st->ring_xfer[i].cs_change = 1;
262 /* make sure last transfer's cs_change is not set */
263 st->ring_xfer[len - 1].cs_change = 0;
265 spi_message_init_with_transfers(&st->ring_msg, st->ring_xfer, len);
270 static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
272 struct iio_poll_func *pf = p;
273 struct iio_dev *indio_dev = pf->indio_dev;
274 struct ti_ads7950_state *st = iio_priv(indio_dev);
277 ret = spi_sync(st->spi, &st->ring_msg);
281 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
282 iio_get_time_ns(indio_dev));
285 iio_trigger_notify_done(indio_dev->trig);
290 static int ti_ads7950_scan_direct(struct ti_ads7950_state *st, unsigned int ch)
294 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(ch) | st->settings;
295 st->tx_buf[0] = cpu_to_be16(cmd);
297 ret = spi_sync(st->spi, &st->scan_single_msg);
301 return be16_to_cpu(st->rx_buf[0]);
304 static int ti_ads7950_get_range(struct ti_ads7950_state *st)
308 vref = regulator_get_voltage(st->reg);
314 if (st->settings & TI_ADS7950_CR_RANGE_5V)
320 static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
321 struct iio_chan_spec const *chan,
322 int *val, int *val2, long m)
324 struct ti_ads7950_state *st = iio_priv(indio_dev);
328 case IIO_CHAN_INFO_RAW:
330 ret = iio_device_claim_direct_mode(indio_dev);
334 ret = ti_ads7950_scan_direct(st, chan->address);
335 iio_device_release_direct_mode(indio_dev);
339 if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
342 *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
343 chan->scan_type.realbits);
346 case IIO_CHAN_INFO_SCALE:
347 ret = ti_ads7950_get_range(st);
352 *val2 = (1 << chan->scan_type.realbits) - 1;
354 return IIO_VAL_FRACTIONAL;
360 static const struct iio_info ti_ads7950_info = {
361 .read_raw = &ti_ads7950_read_raw,
362 .update_scan_mode = ti_ads7950_update_scan_mode,
363 .driver_module = THIS_MODULE,
366 static int ti_ads7950_probe(struct spi_device *spi)
368 struct ti_ads7950_state *st;
369 struct iio_dev *indio_dev;
370 const struct ti_ads7950_chip_info *info;
373 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
377 st = iio_priv(indio_dev);
379 spi_set_drvdata(spi, indio_dev);
382 st->settings = TI_ADS7950_CR_MANUAL | TI_ADS7950_CR_RANGE_5V;
384 info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
386 indio_dev->name = spi_get_device_id(spi)->name;
387 indio_dev->dev.parent = &spi->dev;
388 indio_dev->modes = INDIO_DIRECT_MODE;
389 indio_dev->channels = info->channels;
390 indio_dev->num_channels = info->num_channels;
391 indio_dev->info = &ti_ads7950_info;
394 * Setup default message. The sample is read at the end of the first
395 * transfer, then it takes one full cycle to convert the sample and one
396 * more cycle to send the value. The conversion process is driven by
397 * the SPI clock, which is why we have 3 transfers. The middle one is
398 * just dummy data sent while the chip is converting the sample that
399 * was read at the end of the first transfer.
402 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
403 st->scan_single_xfer[0].len = 2;
404 st->scan_single_xfer[0].cs_change = 1;
405 st->scan_single_xfer[1].tx_buf = &st->tx_buf[0];
406 st->scan_single_xfer[1].len = 2;
407 st->scan_single_xfer[1].cs_change = 1;
408 st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
409 st->scan_single_xfer[2].len = 2;
411 spi_message_init_with_transfers(&st->scan_single_msg,
412 st->scan_single_xfer, 3);
414 st->reg = devm_regulator_get(&spi->dev, "vref");
415 if (IS_ERR(st->reg)) {
416 dev_err(&spi->dev, "Failed get get regulator \"vref\"\n");
417 return PTR_ERR(st->reg);
420 ret = regulator_enable(st->reg);
422 dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
426 ret = iio_triggered_buffer_setup(indio_dev, NULL,
427 &ti_ads7950_trigger_handler, NULL);
429 dev_err(&spi->dev, "Failed to setup triggered buffer\n");
430 goto error_disable_reg;
433 ret = iio_device_register(indio_dev);
435 dev_err(&spi->dev, "Failed to register iio device\n");
436 goto error_cleanup_ring;
442 iio_triggered_buffer_cleanup(indio_dev);
444 regulator_disable(st->reg);
449 static int ti_ads7950_remove(struct spi_device *spi)
451 struct iio_dev *indio_dev = spi_get_drvdata(spi);
452 struct ti_ads7950_state *st = iio_priv(indio_dev);
454 iio_device_unregister(indio_dev);
455 iio_triggered_buffer_cleanup(indio_dev);
456 regulator_disable(st->reg);
461 static const struct spi_device_id ti_ads7950_id[] = {
462 { "ads7950", TI_ADS7950 },
463 { "ads7951", TI_ADS7951 },
464 { "ads7952", TI_ADS7952 },
465 { "ads7953", TI_ADS7953 },
466 { "ads7954", TI_ADS7954 },
467 { "ads7955", TI_ADS7955 },
468 { "ads7956", TI_ADS7956 },
469 { "ads7957", TI_ADS7957 },
470 { "ads7958", TI_ADS7958 },
471 { "ads7959", TI_ADS7959 },
472 { "ads7960", TI_ADS7960 },
473 { "ads7961", TI_ADS7961 },
476 MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
478 static struct spi_driver ti_ads7950_driver = {
482 .probe = ti_ads7950_probe,
483 .remove = ti_ads7950_remove,
484 .id_table = ti_ads7950_id,
486 module_spi_driver(ti_ads7950_driver);
488 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
489 MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
490 MODULE_LICENSE("GPL v2");