2 * Freescale Vybrid vf610 ADC driver
4 * Copyright 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/completion.h>
31 #include <linux/of_irq.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/of_platform.h>
34 #include <linux/err.h>
36 #include <linux/iio/iio.h>
37 #include <linux/iio/sysfs.h>
38 #include <linux/iio/driver.h>
40 /* This will be the driver name the kernel reports */
41 #define DRIVER_NAME "vf610-adc"
43 /* Vybrid/IMX ADC registers */
44 #define VF610_REG_ADC_HC0 0x00
45 #define VF610_REG_ADC_HC1 0x04
46 #define VF610_REG_ADC_HS 0x08
47 #define VF610_REG_ADC_R0 0x0c
48 #define VF610_REG_ADC_R1 0x10
49 #define VF610_REG_ADC_CFG 0x14
50 #define VF610_REG_ADC_GC 0x18
51 #define VF610_REG_ADC_GS 0x1c
52 #define VF610_REG_ADC_CV 0x20
53 #define VF610_REG_ADC_OFS 0x24
54 #define VF610_REG_ADC_CAL 0x28
55 #define VF610_REG_ADC_PCTL 0x30
57 /* Configuration register field define */
58 #define VF610_ADC_MODE_BIT8 0x00
59 #define VF610_ADC_MODE_BIT10 0x04
60 #define VF610_ADC_MODE_BIT12 0x08
61 #define VF610_ADC_MODE_MASK 0x0c
62 #define VF610_ADC_BUSCLK2_SEL 0x01
63 #define VF610_ADC_ALTCLK_SEL 0x02
64 #define VF610_ADC_ADACK_SEL 0x03
65 #define VF610_ADC_ADCCLK_MASK 0x03
66 #define VF610_ADC_CLK_DIV2 0x20
67 #define VF610_ADC_CLK_DIV4 0x40
68 #define VF610_ADC_CLK_DIV8 0x60
69 #define VF610_ADC_CLK_MASK 0x60
70 #define VF610_ADC_ADLSMP_LONG 0x10
71 #define VF610_ADC_ADSTS_MASK 0x300
72 #define VF610_ADC_ADLPC_EN 0x80
73 #define VF610_ADC_ADHSC_EN 0x400
74 #define VF610_ADC_REFSEL_VALT 0x100
75 #define VF610_ADC_REFSEL_VBG 0x1000
76 #define VF610_ADC_ADTRG_HARD 0x2000
77 #define VF610_ADC_AVGS_8 0x4000
78 #define VF610_ADC_AVGS_16 0x8000
79 #define VF610_ADC_AVGS_32 0xC000
80 #define VF610_ADC_AVGS_MASK 0xC000
81 #define VF610_ADC_OVWREN 0x10000
83 /* General control register field define */
84 #define VF610_ADC_ADACKEN 0x1
85 #define VF610_ADC_DMAEN 0x2
86 #define VF610_ADC_ACREN 0x4
87 #define VF610_ADC_ACFGT 0x8
88 #define VF610_ADC_ACFE 0x10
89 #define VF610_ADC_AVGEN 0x20
90 #define VF610_ADC_ADCON 0x40
91 #define VF610_ADC_CAL 0x80
93 /* Other field define */
94 #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
95 #define VF610_ADC_AIEN (0x1 << 7)
96 #define VF610_ADC_CONV_DISABLE 0x1F
97 #define VF610_ADC_HS_COCO0 0x1
98 #define VF610_ADC_CALF 0x2
99 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
102 VF610_ADCIOC_BUSCLK_SET,
103 VF610_ADCIOC_ALTCLK_SET,
104 VF610_ADCIOC_ADACK_SET,
108 VF610_ADCIOC_VR_VREF_SET,
109 VF610_ADCIOC_VR_VALT_SET,
110 VF610_ADCIOC_VR_VBG_SET,
121 enum conversion_mode_sel {
122 VF610_ADC_CONV_NORMAL,
123 VF610_ADC_CONV_HIGH_SPEED,
124 VF610_ADC_CONV_LOW_POWER,
127 struct vf610_adc_feature {
128 enum clk_sel clk_sel;
129 enum vol_ref vol_ref;
130 enum conversion_mode_sel conv_mode;
147 struct regulator *vref;
149 u32 max_adck_rate[3];
150 struct vf610_adc_feature adc_feature;
152 u32 sample_freq_avail[5];
154 struct completion completion;
157 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
159 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
161 struct vf610_adc_feature *adc_feature = &info->adc_feature;
162 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
165 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
168 /* calculate clk divider which is within specification */
169 divisor = ipg_rate / adck_rate;
170 adc_feature->clk_div = 1 << fls(divisor + 1);
172 /* fall-back value using a safe divisor */
173 adc_feature->clk_div = 8;
177 * Calculate ADC sample frequencies
178 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
179 * which is the same as bus clock.
181 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
182 * SFCAdder: fixed to 6 ADCK cycles
183 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
184 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
185 * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
187 adck_rate = ipg_rate / info->adc_feature.clk_div;
188 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
189 info->sample_freq_avail[i] =
190 adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3));
193 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
195 struct vf610_adc_feature *adc_feature = &info->adc_feature;
197 /* set default Configuration for ADC controller */
198 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
199 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
201 adc_feature->calibration = true;
202 adc_feature->ovwren = true;
204 adc_feature->res_mode = 12;
205 adc_feature->sample_rate = 1;
207 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
209 vf610_adc_calculate_rates(info);
212 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
214 struct vf610_adc_feature *adc_feature = &info->adc_feature;
218 switch (adc_feature->clk_sel) {
219 case VF610_ADCIOC_ALTCLK_SET:
220 cfg_data |= VF610_ADC_ALTCLK_SEL;
222 case VF610_ADCIOC_ADACK_SET:
223 cfg_data |= VF610_ADC_ADACK_SEL;
229 /* low power set for calibration */
230 cfg_data |= VF610_ADC_ADLPC_EN;
232 /* enable high speed for calibration */
233 cfg_data |= VF610_ADC_ADHSC_EN;
235 /* voltage reference */
236 switch (adc_feature->vol_ref) {
237 case VF610_ADCIOC_VR_VREF_SET:
239 case VF610_ADCIOC_VR_VALT_SET:
240 cfg_data |= VF610_ADC_REFSEL_VALT;
242 case VF610_ADCIOC_VR_VBG_SET:
243 cfg_data |= VF610_ADC_REFSEL_VBG;
246 dev_err(info->dev, "error voltage reference\n");
249 /* data overwrite enable */
250 if (adc_feature->ovwren)
251 cfg_data |= VF610_ADC_OVWREN;
253 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
254 writel(gc_data, info->regs + VF610_REG_ADC_GC);
257 static void vf610_adc_calibration(struct vf610_adc *info)
261 if (!info->adc_feature.calibration)
264 /* enable calibration interrupt */
265 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
266 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
268 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
269 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
271 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
272 dev_err(info->dev, "Timeout for adc calibration\n");
274 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
275 if (adc_gc & VF610_ADC_CALF)
276 dev_err(info->dev, "ADC calibration failed\n");
278 info->adc_feature.calibration = false;
281 static void vf610_adc_cfg_set(struct vf610_adc *info)
283 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
286 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
288 cfg_data &= ~VF610_ADC_ADLPC_EN;
289 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
290 cfg_data |= VF610_ADC_ADLPC_EN;
292 cfg_data &= ~VF610_ADC_ADHSC_EN;
293 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
294 cfg_data |= VF610_ADC_ADHSC_EN;
296 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
299 static void vf610_adc_sample_set(struct vf610_adc *info)
301 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
302 int cfg_data, gc_data;
304 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
305 gc_data = readl(info->regs + VF610_REG_ADC_GC);
307 /* resolution mode */
308 cfg_data &= ~VF610_ADC_MODE_MASK;
309 switch (adc_feature->res_mode) {
311 cfg_data |= VF610_ADC_MODE_BIT8;
314 cfg_data |= VF610_ADC_MODE_BIT10;
317 cfg_data |= VF610_ADC_MODE_BIT12;
320 dev_err(info->dev, "error resolution mode\n");
324 /* clock select and clock divider */
325 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
326 switch (adc_feature->clk_div) {
330 cfg_data |= VF610_ADC_CLK_DIV2;
333 cfg_data |= VF610_ADC_CLK_DIV4;
336 cfg_data |= VF610_ADC_CLK_DIV8;
339 switch (adc_feature->clk_sel) {
340 case VF610_ADCIOC_BUSCLK_SET:
341 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
344 dev_err(info->dev, "error clk divider\n");
350 /* Use the short sample mode */
351 cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK);
353 /* update hardware average selection */
354 cfg_data &= ~VF610_ADC_AVGS_MASK;
355 gc_data &= ~VF610_ADC_AVGEN;
356 switch (adc_feature->sample_rate) {
357 case VF610_ADC_SAMPLE_1:
359 case VF610_ADC_SAMPLE_4:
360 gc_data |= VF610_ADC_AVGEN;
362 case VF610_ADC_SAMPLE_8:
363 gc_data |= VF610_ADC_AVGEN;
364 cfg_data |= VF610_ADC_AVGS_8;
366 case VF610_ADC_SAMPLE_16:
367 gc_data |= VF610_ADC_AVGEN;
368 cfg_data |= VF610_ADC_AVGS_16;
370 case VF610_ADC_SAMPLE_32:
371 gc_data |= VF610_ADC_AVGEN;
372 cfg_data |= VF610_ADC_AVGS_32;
376 "error hardware sample average select\n");
379 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
380 writel(gc_data, info->regs + VF610_REG_ADC_GC);
383 static void vf610_adc_hw_init(struct vf610_adc *info)
385 /* CFG: Feature set */
386 vf610_adc_cfg_post_set(info);
387 vf610_adc_sample_set(info);
389 /* adc calibration */
390 vf610_adc_calibration(info);
392 /* CFG: power and speed set */
393 vf610_adc_cfg_set(info);
396 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
397 const struct iio_chan_spec *chan,
400 struct vf610_adc *info = iio_priv(indio_dev);
402 mutex_lock(&indio_dev->mlock);
403 info->adc_feature.conv_mode = mode;
404 vf610_adc_calculate_rates(info);
405 vf610_adc_hw_init(info);
406 mutex_unlock(&indio_dev->mlock);
411 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
412 const struct iio_chan_spec *chan)
414 struct vf610_adc *info = iio_priv(indio_dev);
416 return info->adc_feature.conv_mode;
419 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
422 static const struct iio_enum vf610_conversion_mode = {
423 .items = vf610_conv_modes,
424 .num_items = ARRAY_SIZE(vf610_conv_modes),
425 .get = vf610_get_conversion_mode,
426 .set = vf610_set_conversion_mode,
429 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
430 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
434 #define VF610_ADC_CHAN(_idx, _chan_type) { \
435 .type = (_chan_type), \
438 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
439 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
440 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
441 .ext_info = vf610_ext_info, \
444 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
445 .type = (_chan_type), \
447 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
450 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
451 VF610_ADC_CHAN(0, IIO_VOLTAGE),
452 VF610_ADC_CHAN(1, IIO_VOLTAGE),
453 VF610_ADC_CHAN(2, IIO_VOLTAGE),
454 VF610_ADC_CHAN(3, IIO_VOLTAGE),
455 VF610_ADC_CHAN(4, IIO_VOLTAGE),
456 VF610_ADC_CHAN(5, IIO_VOLTAGE),
457 VF610_ADC_CHAN(6, IIO_VOLTAGE),
458 VF610_ADC_CHAN(7, IIO_VOLTAGE),
459 VF610_ADC_CHAN(8, IIO_VOLTAGE),
460 VF610_ADC_CHAN(9, IIO_VOLTAGE),
461 VF610_ADC_CHAN(10, IIO_VOLTAGE),
462 VF610_ADC_CHAN(11, IIO_VOLTAGE),
463 VF610_ADC_CHAN(12, IIO_VOLTAGE),
464 VF610_ADC_CHAN(13, IIO_VOLTAGE),
465 VF610_ADC_CHAN(14, IIO_VOLTAGE),
466 VF610_ADC_CHAN(15, IIO_VOLTAGE),
467 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
471 static int vf610_adc_read_data(struct vf610_adc *info)
475 result = readl(info->regs + VF610_REG_ADC_R0);
477 switch (info->adc_feature.res_mode) {
494 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
496 struct vf610_adc *info = (struct vf610_adc *)dev_id;
499 coco = readl(info->regs + VF610_REG_ADC_HS);
500 if (coco & VF610_ADC_HS_COCO0) {
501 info->value = vf610_adc_read_data(info);
502 complete(&info->completion);
508 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
509 struct device_attribute *attr, char *buf)
511 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
515 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
516 len += scnprintf(buf + len, PAGE_SIZE - len,
517 "%u ", info->sample_freq_avail[i]);
519 /* replace trailing space by newline */
525 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
527 static struct attribute *vf610_attributes[] = {
528 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
532 static const struct attribute_group vf610_attribute_group = {
533 .attrs = vf610_attributes,
536 static int vf610_read_raw(struct iio_dev *indio_dev,
537 struct iio_chan_spec const *chan,
542 struct vf610_adc *info = iio_priv(indio_dev);
547 case IIO_CHAN_INFO_RAW:
548 case IIO_CHAN_INFO_PROCESSED:
549 mutex_lock(&indio_dev->mlock);
550 reinit_completion(&info->completion);
552 hc_cfg = VF610_ADC_ADCHC(chan->channel);
553 hc_cfg |= VF610_ADC_AIEN;
554 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
555 ret = wait_for_completion_interruptible_timeout
556 (&info->completion, VF610_ADC_TIMEOUT);
558 mutex_unlock(&indio_dev->mlock);
562 mutex_unlock(&indio_dev->mlock);
566 switch (chan->type) {
572 * Calculate in degree Celsius times 1000
573 * Using sensor slope of 1.84 mV/°C and
574 * V at 25°C of 696 mV
576 *val = 25000 - ((int)info->value - 864) * 1000000 / 1840;
579 mutex_unlock(&indio_dev->mlock);
583 mutex_unlock(&indio_dev->mlock);
586 case IIO_CHAN_INFO_SCALE:
587 *val = info->vref_uv / 1000;
588 *val2 = info->adc_feature.res_mode;
589 return IIO_VAL_FRACTIONAL_LOG2;
591 case IIO_CHAN_INFO_SAMP_FREQ:
592 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
603 static int vf610_write_raw(struct iio_dev *indio_dev,
604 struct iio_chan_spec const *chan,
609 struct vf610_adc *info = iio_priv(indio_dev);
613 case IIO_CHAN_INFO_SAMP_FREQ:
615 i < ARRAY_SIZE(info->sample_freq_avail);
617 if (val == info->sample_freq_avail[i]) {
618 info->adc_feature.sample_rate = i;
619 vf610_adc_sample_set(info);
631 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
632 unsigned reg, unsigned writeval,
635 struct vf610_adc *info = iio_priv(indio_dev);
637 if ((readval == NULL) ||
638 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
641 *readval = readl(info->regs + reg);
646 static const struct iio_info vf610_adc_iio_info = {
647 .driver_module = THIS_MODULE,
648 .read_raw = &vf610_read_raw,
649 .write_raw = &vf610_write_raw,
650 .debugfs_reg_access = &vf610_adc_reg_access,
651 .attrs = &vf610_attribute_group,
654 static const struct of_device_id vf610_adc_match[] = {
655 { .compatible = "fsl,vf610-adc", },
658 MODULE_DEVICE_TABLE(of, vf610_adc_match);
660 static int vf610_adc_probe(struct platform_device *pdev)
662 struct vf610_adc *info;
663 struct iio_dev *indio_dev;
664 struct resource *mem;
668 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
670 dev_err(&pdev->dev, "Failed allocating iio device\n");
674 info = iio_priv(indio_dev);
675 info->dev = &pdev->dev;
677 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
678 info->regs = devm_ioremap_resource(&pdev->dev, mem);
679 if (IS_ERR(info->regs))
680 return PTR_ERR(info->regs);
682 irq = platform_get_irq(pdev, 0);
684 dev_err(&pdev->dev, "no irq resource?\n");
688 ret = devm_request_irq(info->dev, irq,
690 dev_name(&pdev->dev), info);
692 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
696 info->clk = devm_clk_get(&pdev->dev, "adc");
697 if (IS_ERR(info->clk)) {
698 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
700 return PTR_ERR(info->clk);
703 info->vref = devm_regulator_get(&pdev->dev, "vref");
704 if (IS_ERR(info->vref))
705 return PTR_ERR(info->vref);
707 ret = regulator_enable(info->vref);
711 info->vref_uv = regulator_get_voltage(info->vref);
713 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
714 info->max_adck_rate, 3);
716 platform_set_drvdata(pdev, indio_dev);
718 init_completion(&info->completion);
720 indio_dev->name = dev_name(&pdev->dev);
721 indio_dev->dev.parent = &pdev->dev;
722 indio_dev->dev.of_node = pdev->dev.of_node;
723 indio_dev->info = &vf610_adc_iio_info;
724 indio_dev->modes = INDIO_DIRECT_MODE;
725 indio_dev->channels = vf610_adc_iio_channels;
726 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
728 ret = clk_prepare_enable(info->clk);
731 "Could not prepare or enable the clock.\n");
732 goto error_adc_clk_enable;
735 vf610_adc_cfg_init(info);
736 vf610_adc_hw_init(info);
738 ret = iio_device_register(indio_dev);
740 dev_err(&pdev->dev, "Couldn't register the device.\n");
741 goto error_iio_device_register;
747 error_iio_device_register:
748 clk_disable_unprepare(info->clk);
749 error_adc_clk_enable:
750 regulator_disable(info->vref);
755 static int vf610_adc_remove(struct platform_device *pdev)
757 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
758 struct vf610_adc *info = iio_priv(indio_dev);
760 iio_device_unregister(indio_dev);
761 regulator_disable(info->vref);
762 clk_disable_unprepare(info->clk);
767 #ifdef CONFIG_PM_SLEEP
768 static int vf610_adc_suspend(struct device *dev)
770 struct iio_dev *indio_dev = dev_get_drvdata(dev);
771 struct vf610_adc *info = iio_priv(indio_dev);
774 /* ADC controller enters to stop mode */
775 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
776 hc_cfg |= VF610_ADC_CONV_DISABLE;
777 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
779 clk_disable_unprepare(info->clk);
780 regulator_disable(info->vref);
785 static int vf610_adc_resume(struct device *dev)
787 struct iio_dev *indio_dev = dev_get_drvdata(dev);
788 struct vf610_adc *info = iio_priv(indio_dev);
791 ret = regulator_enable(info->vref);
795 ret = clk_prepare_enable(info->clk);
799 vf610_adc_hw_init(info);
804 regulator_disable(info->vref);
809 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
811 static struct platform_driver vf610_adc_driver = {
812 .probe = vf610_adc_probe,
813 .remove = vf610_adc_remove,
816 .of_match_table = vf610_adc_match,
817 .pm = &vf610_adc_pm_ops,
821 module_platform_driver(vf610_adc_driver);
823 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
824 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
825 MODULE_LICENSE("GPL v2");