2 * Copyright (C) 2012 Invensense, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 #include <linux/i2c.h>
14 #include <linux/i2c-mux.h>
15 #include <linux/kfifo.h>
16 #include <linux/spinlock.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/regmap.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/kfifo_buf.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/triggered_buffer.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/platform_data/invensense_mpu6050.h>
28 * struct inv_mpu6050_reg_map - Notable registers.
29 * @sample_rate_div: Divider applied to gyro output rate.
30 * @lpf: Configures internal low pass filter.
31 * @user_ctrl: Enables/resets the FIFO.
32 * @fifo_en: Determines which data will appear in FIFO.
33 * @gyro_config: gyro config register.
34 * @accl_config: accel config register
35 * @fifo_count_h: Upper byte of FIFO count.
36 * @fifo_r_w: FIFO register.
37 * @raw_gyro: Address of first gyro register.
38 * @raw_accl: Address of first accel register.
39 * @temperature: temperature register
40 * @int_enable: Interrupt enable register.
41 * @pwr_mgmt_1: Controls chip's power state and clock source.
42 * @pwr_mgmt_2: Controls power state of individual sensors.
43 * @int_pin_cfg; Controls interrupt pin configuration.
44 * @accl_offset: Controls the accelerometer calibration offset.
45 * @gyro_offset: Controls the gyroscope calibration offset.
47 struct inv_mpu6050_reg_map {
79 * struct inv_mpu6050_chip_config - Cached chip configuration data.
80 * @fsr: Full scale range.
81 * @lpf: Digital low pass filter frequency.
82 * @accl_fs: accel full scale range.
83 * @enable: master enable state.
84 * @accl_fifo_enable: enable accel data output
85 * @gyro_fifo_enable: enable gyro data output
86 * @fifo_rate: FIFO update rate.
88 struct inv_mpu6050_chip_config {
91 unsigned int accl_fs:2;
92 unsigned int enable:1;
93 unsigned int accl_fifo_enable:1;
94 unsigned int gyro_fifo_enable:1;
99 * struct inv_mpu6050_hw - Other important hardware information.
100 * @whoami: Self identification byte from WHO_AM_I register
101 * @name: name of the chip.
102 * @reg: register map of the chip.
103 * @config: configuration of the chip.
105 struct inv_mpu6050_hw {
108 const struct inv_mpu6050_reg_map *reg;
109 const struct inv_mpu6050_chip_config *config;
113 * struct inv_mpu6050_state - Driver state variables.
114 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
115 * @trig: IIO trigger.
116 * @chip_config: Cached attribute information.
117 * @reg: Map of important registers.
118 * @hw: Other hardware-specific information.
119 * @chip_type: chip type.
120 * @time_stamp_lock: spin lock to time stamp.
121 * @plat_data: platform data (deprecated in favor of @orientation).
122 * @orientation: sensor chip orientation relative to main hardware.
123 * @timestamps: kfifo queue to store time stamp.
124 * @map regmap pointer.
125 * @irq interrupt number.
127 struct inv_mpu6050_state {
128 #define TIMESTAMP_FIFO_SIZE 16
129 struct iio_trigger *trig;
130 struct inv_mpu6050_chip_config chip_config;
131 const struct inv_mpu6050_reg_map *reg;
132 const struct inv_mpu6050_hw *hw;
133 enum inv_devices chip_type;
134 spinlock_t time_stamp_lock;
135 struct i2c_mux_core *muxc;
136 struct i2c_client *mux_client;
137 unsigned int powerup_count;
138 struct inv_mpu6050_platform_data plat_data;
139 struct iio_mount_matrix orientation;
140 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
145 /*register and associated bit definition*/
146 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06
147 #define INV_MPU6050_REG_GYRO_OFFSET 0x13
149 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
150 #define INV_MPU6050_REG_CONFIG 0x1A
151 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B
152 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
154 #define INV_MPU6050_REG_FIFO_EN 0x23
155 #define INV_MPU6050_BIT_ACCEL_OUT 0x08
156 #define INV_MPU6050_BITS_GYRO_OUT 0x70
158 #define INV_MPU6050_REG_INT_ENABLE 0x38
159 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01
160 #define INV_MPU6050_BIT_DMP_INT_EN 0x02
162 #define INV_MPU6050_REG_RAW_ACCEL 0x3B
163 #define INV_MPU6050_REG_TEMPERATURE 0x41
164 #define INV_MPU6050_REG_RAW_GYRO 0x43
166 #define INV_MPU6050_REG_USER_CTRL 0x6A
167 #define INV_MPU6050_BIT_FIFO_RST 0x04
168 #define INV_MPU6050_BIT_DMP_RST 0x08
169 #define INV_MPU6050_BIT_I2C_MST_EN 0x20
170 #define INV_MPU6050_BIT_FIFO_EN 0x40
171 #define INV_MPU6050_BIT_DMP_EN 0x80
172 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10
174 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B
175 #define INV_MPU6050_BIT_H_RESET 0x80
176 #define INV_MPU6050_BIT_SLEEP 0x40
177 #define INV_MPU6050_BIT_CLK_MASK 0x7
179 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C
180 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
181 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
183 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72
184 #define INV_MPU6050_REG_FIFO_R_W 0x74
186 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
187 #define INV_MPU6050_FIFO_COUNT_BYTE 2
188 #define INV_MPU6050_FIFO_THRESHOLD 500
190 /* mpu6500 registers */
191 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77
193 /* delay time in milliseconds */
194 #define INV_MPU6050_POWER_UP_TIME 100
195 #define INV_MPU6050_TEMP_UP_TIME 100
196 #define INV_MPU6050_SENSOR_UP_TIME 30
198 /* delay time in microseconds */
199 #define INV_MPU6050_REG_UP_TIME_MIN 5000
200 #define INV_MPU6050_REG_UP_TIME_MAX 10000
202 #define INV_MPU6050_TEMP_OFFSET 12421
203 #define INV_MPU6050_TEMP_SCALE 2941
204 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3
205 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3
206 #define INV_MPU6050_THREE_AXIS 3
207 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
208 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
210 /* 6 + 6 round up and plus 8 */
211 #define INV_MPU6050_OUTPUT_DATA_SIZE 24
213 #define INV_MPU6050_REG_INT_PIN_CFG 0x37
214 #define INV_MPU6050_BIT_BYPASS_EN 0x2
215 #define INV_MPU6050_INT_PIN_CFG 0
217 /* init parameters */
218 #define INV_MPU6050_INIT_FIFO_RATE 50
219 #define INV_MPU6050_TIME_STAMP_TOR 5
220 #define INV_MPU6050_MAX_FIFO_RATE 1000
221 #define INV_MPU6050_MIN_FIFO_RATE 4
222 #define INV_MPU6050_ONE_K_HZ 1000
224 #define INV_MPU6050_REG_WHOAMI 117
226 #define INV_MPU6000_WHOAMI_VALUE 0x68
227 #define INV_MPU6050_WHOAMI_VALUE 0x68
228 #define INV_MPU6500_WHOAMI_VALUE 0x70
229 #define INV_MPU9150_WHOAMI_VALUE 0x68
230 #define INV_MPU9250_WHOAMI_VALUE 0x71
231 #define INV_ICM20608_WHOAMI_VALUE 0xAF
233 /* scan element definition */
234 enum inv_mpu6050_scan {
235 INV_MPU6050_SCAN_ACCL_X,
236 INV_MPU6050_SCAN_ACCL_Y,
237 INV_MPU6050_SCAN_ACCL_Z,
238 INV_MPU6050_SCAN_GYRO_X,
239 INV_MPU6050_SCAN_GYRO_Y,
240 INV_MPU6050_SCAN_GYRO_Z,
241 INV_MPU6050_SCAN_TIMESTAMP,
244 enum inv_mpu6050_filter_e {
245 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
246 INV_MPU6050_FILTER_188HZ,
247 INV_MPU6050_FILTER_98HZ,
248 INV_MPU6050_FILTER_42HZ,
249 INV_MPU6050_FILTER_20HZ,
250 INV_MPU6050_FILTER_10HZ,
251 INV_MPU6050_FILTER_5HZ,
252 INV_MPU6050_FILTER_2100HZ_NOLPF,
256 /* IIO attribute address */
257 enum INV_MPU6050_IIO_ATTR_ADDR {
262 enum inv_mpu6050_accl_fs_e {
263 INV_MPU6050_FS_02G = 0,
270 enum inv_mpu6050_fsr_e {
271 INV_MPU6050_FSR_250DPS = 0,
272 INV_MPU6050_FSR_500DPS,
273 INV_MPU6050_FSR_1000DPS,
274 INV_MPU6050_FSR_2000DPS,
278 enum inv_mpu6050_clock_sel_e {
279 INV_CLK_INTERNAL = 0,
284 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
285 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
286 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
287 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
288 int inv_reset_fifo(struct iio_dev *indio_dev);
289 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
290 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
291 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
292 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
293 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
294 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
295 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
296 int inv_mpu_core_remove(struct device *dev);
297 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
298 extern const struct dev_pm_ops inv_mpu_pmops;