2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: RDMA Controller HW interface (header)
39 #ifndef __BNXT_QPLIB_RCFW_H__
40 #define __BNXT_QPLIB_RCFW_H__
42 #define RCFW_CMDQ_TRIG_VAL 1
43 #define RCFW_COMM_PCI_BAR_REGION 0
44 #define RCFW_COMM_CONS_PCI_BAR_REGION 2
45 #define RCFW_COMM_BASE_OFFSET 0x600
46 #define RCFW_PF_COMM_PROD_OFFSET 0xc
47 #define RCFW_VF_COMM_PROD_OFFSET 0xc
48 #define RCFW_COMM_TRIG_OFFSET 0x100
49 #define RCFW_COMM_SIZE 0x104
51 #define RCFW_DBR_PCI_BAR_REGION 2
53 #define RCFW_CMD_PREP(req, CMD, cmd_flags) \
55 memset(&(req), 0, sizeof((req))); \
56 (req).opcode = CMDQ_BASE_OPCODE_##CMD; \
57 (req).cmd_size = (sizeof((req)) + \
58 BNXT_QPLIB_CMDQE_UNITS - 1) / \
59 BNXT_QPLIB_CMDQE_UNITS; \
60 (req).flags = cpu_to_le16(cmd_flags); \
63 #define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */
66 #define BNXT_QPLIB_CMDQE_MAX_CNT 256
67 #define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe)
68 #define BNXT_QPLIB_CMDQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CMDQE_UNITS)
70 #define MAX_CMDQ_IDX (BNXT_QPLIB_CMDQE_MAX_CNT - 1)
71 #define MAX_CMDQ_IDX_PER_PG (BNXT_QPLIB_CMDQE_CNT_PER_PG - 1)
73 #define RCFW_MAX_OUTSTANDING_CMD BNXT_QPLIB_CMDQE_MAX_CNT
74 #define RCFW_MAX_COOKIE_VALUE 0x7FFF
75 #define RCFW_CMD_IS_BLOCKING 0x8000
77 /* Cmdq contains a fix number of a 16-Byte slots */
78 struct bnxt_qplib_cmdqe {
82 static inline u32 get_cmdq_pg(u32 val)
84 return (val & ~MAX_CMDQ_IDX_PER_PG) / BNXT_QPLIB_CMDQE_CNT_PER_PG;
87 static inline u32 get_cmdq_idx(u32 val)
89 return val & MAX_CMDQ_IDX_PER_PG;
92 /* Crsq buf is 1024-Byte */
93 struct bnxt_qplib_crsbe {
98 #define BNXT_QPLIB_CRSBE_MAX_CNT 4
99 #define BNXT_QPLIB_CRSBE_UNITS sizeof(struct bnxt_qplib_crsbe)
100 #define BNXT_QPLIB_CRSBE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CRSBE_UNITS)
102 #define MAX_CRSB_IDX (BNXT_QPLIB_CRSBE_MAX_CNT - 1)
103 #define MAX_CRSB_IDX_PER_PG (BNXT_QPLIB_CRSBE_CNT_PER_PG - 1)
105 static inline u32 get_crsb_pg(u32 val)
107 return (val & ~MAX_CRSB_IDX_PER_PG) / BNXT_QPLIB_CRSBE_CNT_PER_PG;
110 static inline u32 get_crsb_idx(u32 val)
112 return val & MAX_CRSB_IDX_PER_PG;
115 static inline void bnxt_qplib_crsb_dma_next(dma_addr_t *pg_map_arr,
116 u32 prod, dma_addr_t *dma_addr)
118 *dma_addr = pg_map_arr[(prod) / BNXT_QPLIB_CRSBE_CNT_PER_PG];
119 *dma_addr += ((prod) % BNXT_QPLIB_CRSBE_CNT_PER_PG) *
120 BNXT_QPLIB_CRSBE_UNITS;
124 /* Allocate 1 per QP for async error notification for now */
125 #define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024)
126 #define BNXT_QPLIB_CREQE_UNITS 16 /* 16-Bytes per prod unit */
127 #define BNXT_QPLIB_CREQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
129 #define MAX_CREQ_IDX (BNXT_QPLIB_CREQE_MAX_CNT - 1)
130 #define MAX_CREQ_IDX_PER_PG (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
132 static inline u32 get_creq_pg(u32 val)
134 return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
137 static inline u32 get_creq_idx(u32 val)
139 return val & MAX_CREQ_IDX_PER_PG;
142 #define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
144 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit) \
145 (!!((hdr)->v & CREQ_BASE_V) == \
146 !((raw_cons) & (cp_bit)))
148 #define CREQ_DB_KEY_CP (0x2 << CMPL_DOORBELL_KEY_SFT)
149 #define CREQ_DB_IDX_VALID CMPL_DOORBELL_IDX_VALID
150 #define CREQ_DB_IRQ_DIS CMPL_DOORBELL_MASK
151 #define CREQ_DB_CP_FLAGS_REARM (CREQ_DB_KEY_CP | \
153 #define CREQ_DB_CP_FLAGS (CREQ_DB_KEY_CP | \
154 CREQ_DB_IDX_VALID | \
156 #define CREQ_DB_REARM(db, raw_cons, cp_bit) \
157 writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
158 #define CREQ_DB(db, raw_cons, cp_bit) \
159 writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
162 struct bnxt_qplib_crsqe {
163 struct creq_qp_event qp_event;
167 struct bnxt_qplib_crsq {
168 struct bnxt_qplib_crsqe *crsq;
174 /* RCFW Communication Channels */
175 struct bnxt_qplib_rcfw {
176 struct pci_dev *pdev;
178 struct tasklet_struct worker;
180 unsigned long *cmdq_bitmap;
183 #define FIRMWARE_INITIALIZED_FLAG 1
184 #define FIRMWARE_FIRST_FLAG BIT(31)
185 wait_queue_head_t waitq;
186 int (*aeq_handler)(struct bnxt_qplib_rcfw *,
187 struct creq_func_event *);
190 /* Bar region info */
191 void __iomem *cmdq_bar_reg_iomem;
193 u16 cmdq_bar_reg_prod_off;
194 u16 cmdq_bar_reg_trig_off;
197 void __iomem *creq_bar_reg_iomem;
199 /* Cmd-Resp and Async Event notification queue */
200 struct bnxt_qplib_hwq creq;
201 u64 creq_qp_event_processed;
202 u64 creq_func_event_processed;
204 /* Actual Cmd and Resp Queues */
205 struct bnxt_qplib_hwq cmdq;
206 struct bnxt_qplib_crsq crsq;
207 struct bnxt_qplib_hwq crsb;
210 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
211 int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
212 struct bnxt_qplib_rcfw *rcfw);
213 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
214 int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
215 struct bnxt_qplib_rcfw *rcfw,
217 int cp_bar_reg_off, int virt_fn,
219 (struct bnxt_qplib_rcfw *,
220 struct creq_func_event *));
222 int bnxt_qplib_rcfw_block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie);
223 int bnxt_qplib_rcfw_wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie);
224 void *bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
225 struct cmdq_base *req, void **crsbe,
228 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
229 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
230 struct bnxt_qplib_ctx *ctx, int is_virtfn);
231 #endif /* __BNXT_QPLIB_RCFW_H__ */