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[karo-tx-linux.git] / drivers / infiniband / hw / cxgb4 / cq.c
1 /*
2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include "iw_cxgb4.h"
34
35 static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
36                       struct c4iw_dev_ucontext *uctx)
37 {
38         struct fw_ri_res_wr *res_wr;
39         struct fw_ri_res *res;
40         int wr_len;
41         struct c4iw_wr_wait wr_wait;
42         struct sk_buff *skb;
43         int ret;
44
45         wr_len = sizeof *res_wr + sizeof *res;
46         skb = alloc_skb(wr_len, GFP_KERNEL);
47         if (!skb)
48                 return -ENOMEM;
49         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
50
51         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
52         memset(res_wr, 0, wr_len);
53         res_wr->op_nres = cpu_to_be32(
54                         FW_WR_OP(FW_RI_RES_WR) |
55                         V_FW_RI_RES_WR_NRES(1) |
56                         FW_WR_COMPL(1));
57         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
58         res_wr->cookie = (unsigned long) &wr_wait;
59         res = res_wr->res;
60         res->u.cq.restype = FW_RI_RES_TYPE_CQ;
61         res->u.cq.op = FW_RI_RES_OP_RESET;
62         res->u.cq.iqid = cpu_to_be32(cq->cqid);
63
64         c4iw_init_wr_wait(&wr_wait);
65         ret = c4iw_ofld_send(rdev, skb);
66         if (!ret) {
67                 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
68         }
69
70         kfree(cq->sw_queue);
71         dma_free_coherent(&(rdev->lldi.pdev->dev),
72                           cq->memsize, cq->queue,
73                           dma_unmap_addr(cq, mapping));
74         c4iw_put_cqid(rdev, cq->cqid, uctx);
75         return ret;
76 }
77
78 static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
79                      struct c4iw_dev_ucontext *uctx)
80 {
81         struct fw_ri_res_wr *res_wr;
82         struct fw_ri_res *res;
83         int wr_len;
84         int user = (uctx != &rdev->uctx);
85         struct c4iw_wr_wait wr_wait;
86         int ret;
87         struct sk_buff *skb;
88
89         cq->cqid = c4iw_get_cqid(rdev, uctx);
90         if (!cq->cqid) {
91                 ret = -ENOMEM;
92                 goto err1;
93         }
94
95         if (!user) {
96                 cq->sw_queue = kzalloc(cq->memsize, GFP_KERNEL);
97                 if (!cq->sw_queue) {
98                         ret = -ENOMEM;
99                         goto err2;
100                 }
101         }
102         cq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev, cq->memsize,
103                                        &cq->dma_addr, GFP_KERNEL);
104         if (!cq->queue) {
105                 ret = -ENOMEM;
106                 goto err3;
107         }
108         dma_unmap_addr_set(cq, mapping, cq->dma_addr);
109         memset(cq->queue, 0, cq->memsize);
110
111         /* build fw_ri_res_wr */
112         wr_len = sizeof *res_wr + sizeof *res;
113
114         skb = alloc_skb(wr_len, GFP_KERNEL);
115         if (!skb) {
116                 ret = -ENOMEM;
117                 goto err4;
118         }
119         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
120
121         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
122         memset(res_wr, 0, wr_len);
123         res_wr->op_nres = cpu_to_be32(
124                         FW_WR_OP(FW_RI_RES_WR) |
125                         V_FW_RI_RES_WR_NRES(1) |
126                         FW_WR_COMPL(1));
127         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
128         res_wr->cookie = (unsigned long) &wr_wait;
129         res = res_wr->res;
130         res->u.cq.restype = FW_RI_RES_TYPE_CQ;
131         res->u.cq.op = FW_RI_RES_OP_WRITE;
132         res->u.cq.iqid = cpu_to_be32(cq->cqid);
133         res->u.cq.iqandst_to_iqandstindex = cpu_to_be32(
134                         V_FW_RI_RES_WR_IQANUS(0) |
135                         V_FW_RI_RES_WR_IQANUD(1) |
136                         F_FW_RI_RES_WR_IQANDST |
137                         V_FW_RI_RES_WR_IQANDSTINDEX(*rdev->lldi.rxq_ids));
138         res->u.cq.iqdroprss_to_iqesize = cpu_to_be16(
139                         F_FW_RI_RES_WR_IQDROPRSS |
140                         V_FW_RI_RES_WR_IQPCIECH(2) |
141                         V_FW_RI_RES_WR_IQINTCNTTHRESH(0) |
142                         F_FW_RI_RES_WR_IQO |
143                         V_FW_RI_RES_WR_IQESIZE(1));
144         res->u.cq.iqsize = cpu_to_be16(cq->size);
145         res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr);
146
147         c4iw_init_wr_wait(&wr_wait);
148
149         ret = c4iw_ofld_send(rdev, skb);
150         if (ret)
151                 goto err4;
152         PDBG("%s wait_event wr_wait %p\n", __func__, &wr_wait);
153         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
154         if (ret)
155                 goto err4;
156
157         cq->gen = 1;
158         cq->gts = rdev->lldi.gts_reg;
159         cq->rdev = rdev;
160         if (user) {
161                 cq->ugts = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
162                                         (cq->cqid << rdev->cqshift);
163                 cq->ugts &= PAGE_MASK;
164         }
165         return 0;
166 err4:
167         dma_free_coherent(&rdev->lldi.pdev->dev, cq->memsize, cq->queue,
168                           dma_unmap_addr(cq, mapping));
169 err3:
170         kfree(cq->sw_queue);
171 err2:
172         c4iw_put_cqid(rdev, cq->cqid, uctx);
173 err1:
174         return ret;
175 }
176
177 static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq)
178 {
179         struct t4_cqe cqe;
180
181         PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
182              wq, cq, cq->sw_cidx, cq->sw_pidx);
183         memset(&cqe, 0, sizeof(cqe));
184         cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
185                                  V_CQE_OPCODE(FW_RI_SEND) |
186                                  V_CQE_TYPE(0) |
187                                  V_CQE_SWCQE(1) |
188                                  V_CQE_QPID(wq->sq.qid));
189         cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
190         cq->sw_queue[cq->sw_pidx] = cqe;
191         t4_swcq_produce(cq);
192 }
193
194 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
195 {
196         int flushed = 0;
197         int in_use = wq->rq.in_use - count;
198
199         BUG_ON(in_use < 0);
200         PDBG("%s wq %p cq %p rq.in_use %u skip count %u\n", __func__,
201              wq, cq, wq->rq.in_use, count);
202         while (in_use--) {
203                 insert_recv_cqe(wq, cq);
204                 flushed++;
205         }
206         return flushed;
207 }
208
209 static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
210                           struct t4_swsqe *swcqe)
211 {
212         struct t4_cqe cqe;
213
214         PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
215              wq, cq, cq->sw_cidx, cq->sw_pidx);
216         memset(&cqe, 0, sizeof(cqe));
217         cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
218                                  V_CQE_OPCODE(swcqe->opcode) |
219                                  V_CQE_TYPE(1) |
220                                  V_CQE_SWCQE(1) |
221                                  V_CQE_QPID(wq->sq.qid));
222         CQE_WRID_SQ_IDX(&cqe) = swcqe->idx;
223         cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
224         cq->sw_queue[cq->sw_pidx] = cqe;
225         t4_swcq_produce(cq);
226 }
227
228 static void advance_oldest_read(struct t4_wq *wq);
229
230 int c4iw_flush_sq(struct c4iw_qp *qhp)
231 {
232         int flushed = 0;
233         struct t4_wq *wq = &qhp->wq;
234         struct c4iw_cq *chp = to_c4iw_cq(qhp->ibqp.send_cq);
235         struct t4_cq *cq = &chp->cq;
236         int idx;
237         struct t4_swsqe *swsqe;
238
239         if (wq->sq.flush_cidx == -1)
240                 wq->sq.flush_cidx = wq->sq.cidx;
241         idx = wq->sq.flush_cidx;
242         BUG_ON(idx >= wq->sq.size);
243         while (idx != wq->sq.pidx) {
244                 swsqe = &wq->sq.sw_sq[idx];
245                 BUG_ON(swsqe->flushed);
246                 swsqe->flushed = 1;
247                 insert_sq_cqe(wq, cq, swsqe);
248                 if (wq->sq.oldest_read == swsqe) {
249                         BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
250                         advance_oldest_read(wq);
251                 }
252                 flushed++;
253                 if (++idx == wq->sq.size)
254                         idx = 0;
255         }
256         wq->sq.flush_cidx += flushed;
257         if (wq->sq.flush_cidx >= wq->sq.size)
258                 wq->sq.flush_cidx -= wq->sq.size;
259         return flushed;
260 }
261
262 static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
263 {
264         struct t4_swsqe *swsqe;
265         int cidx;
266
267         if (wq->sq.flush_cidx == -1)
268                 wq->sq.flush_cidx = wq->sq.cidx;
269         cidx = wq->sq.flush_cidx;
270         BUG_ON(cidx > wq->sq.size);
271
272         while (cidx != wq->sq.pidx) {
273                 swsqe = &wq->sq.sw_sq[cidx];
274                 if (!swsqe->signaled) {
275                         if (++cidx == wq->sq.size)
276                                 cidx = 0;
277                 } else if (swsqe->complete) {
278
279                         BUG_ON(swsqe->flushed);
280
281                         /*
282                          * Insert this completed cqe into the swcq.
283                          */
284                         PDBG("%s moving cqe into swcq sq idx %u cq idx %u\n",
285                                         __func__, cidx, cq->sw_pidx);
286                         swsqe->cqe.header |= htonl(V_CQE_SWCQE(1));
287                         cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
288                         t4_swcq_produce(cq);
289                         swsqe->flushed = 1;
290                         if (++cidx == wq->sq.size)
291                                 cidx = 0;
292                         wq->sq.flush_cidx = cidx;
293                 } else
294                         break;
295         }
296 }
297
298 static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe,
299                 struct t4_cqe *read_cqe)
300 {
301         read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx;
302         read_cqe->len = htonl(wq->sq.oldest_read->read_len);
303         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(hw_cqe)) |
304                         V_CQE_SWCQE(SW_CQE(hw_cqe)) |
305                         V_CQE_OPCODE(FW_RI_READ_REQ) |
306                         V_CQE_TYPE(1));
307         read_cqe->bits_type_ts = hw_cqe->bits_type_ts;
308 }
309
310 static void advance_oldest_read(struct t4_wq *wq)
311 {
312
313         u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1;
314
315         if (rptr == wq->sq.size)
316                 rptr = 0;
317         while (rptr != wq->sq.pidx) {
318                 wq->sq.oldest_read = &wq->sq.sw_sq[rptr];
319
320                 if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ)
321                         return;
322                 if (++rptr == wq->sq.size)
323                         rptr = 0;
324         }
325         wq->sq.oldest_read = NULL;
326 }
327
328 /*
329  * Move all CQEs from the HWCQ into the SWCQ.
330  * Deal with out-of-order and/or completions that complete
331  * prior unsignalled WRs.
332  */
333 void c4iw_flush_hw_cq(struct c4iw_cq *chp)
334 {
335         struct t4_cqe *hw_cqe, *swcqe, read_cqe;
336         struct c4iw_qp *qhp;
337         struct t4_swsqe *swsqe;
338         int ret;
339
340         PDBG("%s  cqid 0x%x\n", __func__, chp->cq.cqid);
341         ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
342
343         /*
344          * This logic is similar to poll_cq(), but not quite the same
345          * unfortunately.  Need to move pertinent HW CQEs to the SW CQ but
346          * also do any translation magic that poll_cq() normally does.
347          */
348         while (!ret) {
349                 qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe));
350
351                 /*
352                  * drop CQEs with no associated QP
353                  */
354                 if (qhp == NULL)
355                         goto next_cqe;
356
357                 if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE)
358                         goto next_cqe;
359
360                 if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
361
362                         /* If we have reached here because of async
363                          * event or other error, and have egress error
364                          * then drop
365                          */
366                         if (CQE_TYPE(hw_cqe) == 1)
367                                 goto next_cqe;
368
369                         /* drop peer2peer RTR reads.
370                          */
371                         if (CQE_WRID_STAG(hw_cqe) == 1)
372                                 goto next_cqe;
373
374                         /*
375                          * Eat completions for unsignaled read WRs.
376                          */
377                         if (!qhp->wq.sq.oldest_read->signaled) {
378                                 advance_oldest_read(&qhp->wq);
379                                 goto next_cqe;
380                         }
381
382                         /*
383                          * Don't write to the HWCQ, create a new read req CQE
384                          * in local memory and move it into the swcq.
385                          */
386                         create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe);
387                         hw_cqe = &read_cqe;
388                         advance_oldest_read(&qhp->wq);
389                 }
390
391                 /* if its a SQ completion, then do the magic to move all the
392                  * unsignaled and now in-order completions into the swcq.
393                  */
394                 if (SQ_TYPE(hw_cqe)) {
395                         swsqe = &qhp->wq.sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
396                         swsqe->cqe = *hw_cqe;
397                         swsqe->complete = 1;
398                         flush_completed_wrs(&qhp->wq, &chp->cq);
399                 } else {
400                         swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx];
401                         *swcqe = *hw_cqe;
402                         swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
403                         t4_swcq_produce(&chp->cq);
404                 }
405 next_cqe:
406                 t4_hwcq_consume(&chp->cq);
407                 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
408         }
409 }
410
411 static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
412 {
413         if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
414                 return 0;
415
416         if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe))
417                 return 0;
418
419         if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe))
420                 return 0;
421
422         if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq))
423                 return 0;
424         return 1;
425 }
426
427 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
428 {
429         struct t4_cqe *cqe;
430         u32 ptr;
431
432         *count = 0;
433         PDBG("%s count zero %d\n", __func__, *count);
434         ptr = cq->sw_cidx;
435         while (ptr != cq->sw_pidx) {
436                 cqe = &cq->sw_queue[ptr];
437                 if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) &&
438                     (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq))
439                         (*count)++;
440                 if (++ptr == cq->size)
441                         ptr = 0;
442         }
443         PDBG("%s cq %p count %d\n", __func__, cq, *count);
444 }
445
446 /*
447  * poll_cq
448  *
449  * Caller must:
450  *     check the validity of the first CQE,
451  *     supply the wq assicated with the qpid.
452  *
453  * credit: cq credit to return to sge.
454  * cqe_flushed: 1 iff the CQE is flushed.
455  * cqe: copy of the polled CQE.
456  *
457  * return value:
458  *    0             CQE returned ok.
459  *    -EAGAIN       CQE skipped, try again.
460  *    -EOVERFLOW    CQ overflow detected.
461  */
462 static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
463                    u8 *cqe_flushed, u64 *cookie, u32 *credit)
464 {
465         int ret = 0;
466         struct t4_cqe *hw_cqe, read_cqe;
467
468         *cqe_flushed = 0;
469         *credit = 0;
470         ret = t4_next_cqe(cq, &hw_cqe);
471         if (ret)
472                 return ret;
473
474         PDBG("%s CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x"
475              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
476              __func__, CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
477              CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
478              CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
479              CQE_WRID_LOW(hw_cqe));
480
481         /*
482          * skip cqe's not affiliated with a QP.
483          */
484         if (wq == NULL) {
485                 ret = -EAGAIN;
486                 goto skip_cqe;
487         }
488
489         /*
490         * skip hw cqe's if the wq is flushed.
491         */
492         if (wq->flushed && !SW_CQE(hw_cqe)) {
493                 ret = -EAGAIN;
494                 goto skip_cqe;
495         }
496
497         /*
498          * skip TERMINATE cqes...
499          */
500         if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) {
501                 ret = -EAGAIN;
502                 goto skip_cqe;
503         }
504
505         /*
506          * Gotta tweak READ completions:
507          *      1) the cqe doesn't contain the sq_wptr from the wr.
508          *      2) opcode not reflected from the wr.
509          *      3) read_len not reflected from the wr.
510          *      4) cq_type is RQ_TYPE not SQ_TYPE.
511          */
512         if (RQ_TYPE(hw_cqe) && (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP)) {
513
514                 /* If we have reached here because of async
515                  * event or other error, and have egress error
516                  * then drop
517                  */
518                 if (CQE_TYPE(hw_cqe) == 1) {
519                         if (CQE_STATUS(hw_cqe))
520                                 t4_set_wq_in_error(wq);
521                         ret = -EAGAIN;
522                         goto skip_cqe;
523                 }
524
525                 /* If this is an unsolicited read response, then the read
526                  * was generated by the kernel driver as part of peer-2-peer
527                  * connection setup.  So ignore the completion.
528                  */
529                 if (CQE_WRID_STAG(hw_cqe) == 1) {
530                         if (CQE_STATUS(hw_cqe))
531                                 t4_set_wq_in_error(wq);
532                         ret = -EAGAIN;
533                         goto skip_cqe;
534                 }
535
536                 /*
537                  * Eat completions for unsignaled read WRs.
538                  */
539                 if (!wq->sq.oldest_read->signaled) {
540                         advance_oldest_read(wq);
541                         ret = -EAGAIN;
542                         goto skip_cqe;
543                 }
544
545                 /*
546                  * Don't write to the HWCQ, so create a new read req CQE
547                  * in local memory.
548                  */
549                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
550                 hw_cqe = &read_cqe;
551                 advance_oldest_read(wq);
552         }
553
554         if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) {
555                 *cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH);
556                 t4_set_wq_in_error(wq);
557         }
558
559         /*
560          * RECV completion.
561          */
562         if (RQ_TYPE(hw_cqe)) {
563
564                 /*
565                  * HW only validates 4 bits of MSN.  So we must validate that
566                  * the MSN in the SEND is the next expected MSN.  If its not,
567                  * then we complete this with T4_ERR_MSN and mark the wq in
568                  * error.
569                  */
570
571                 if (t4_rq_empty(wq)) {
572                         t4_set_wq_in_error(wq);
573                         ret = -EAGAIN;
574                         goto skip_cqe;
575                 }
576                 if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) {
577                         t4_set_wq_in_error(wq);
578                         hw_cqe->header |= htonl(V_CQE_STATUS(T4_ERR_MSN));
579                         goto proc_cqe;
580                 }
581                 goto proc_cqe;
582         }
583
584         /*
585          * If we get here its a send completion.
586          *
587          * Handle out of order completion. These get stuffed
588          * in the SW SQ. Then the SW SQ is walked to move any
589          * now in-order completions into the SW CQ.  This handles
590          * 2 cases:
591          *      1) reaping unsignaled WRs when the first subsequent
592          *         signaled WR is completed.
593          *      2) out of order read completions.
594          */
595         if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
596                 struct t4_swsqe *swsqe;
597
598                 PDBG("%s out of order completion going in sw_sq at idx %u\n",
599                      __func__, CQE_WRID_SQ_IDX(hw_cqe));
600                 swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
601                 swsqe->cqe = *hw_cqe;
602                 swsqe->complete = 1;
603                 ret = -EAGAIN;
604                 goto flush_wq;
605         }
606
607 proc_cqe:
608         *cqe = *hw_cqe;
609
610         /*
611          * Reap the associated WR(s) that are freed up with this
612          * completion.
613          */
614         if (SQ_TYPE(hw_cqe)) {
615                 int idx = CQE_WRID_SQ_IDX(hw_cqe);
616                 BUG_ON(idx >= wq->sq.size);
617
618                 /*
619                 * Account for any unsignaled completions completed by
620                 * this signaled completion.  In this case, cidx points
621                 * to the first unsignaled one, and idx points to the
622                 * signaled one.  So adjust in_use based on this delta.
623                 * if this is not completing any unsigned wrs, then the
624                 * delta will be 0. Handle wrapping also!
625                 */
626                 if (idx < wq->sq.cidx)
627                         wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
628                 else
629                         wq->sq.in_use -= idx - wq->sq.cidx;
630                 BUG_ON(wq->sq.in_use <= 0 && wq->sq.in_use >= wq->sq.size);
631
632                 wq->sq.cidx = (uint16_t)idx;
633                 PDBG("%s completing sq idx %u\n", __func__, wq->sq.cidx);
634                 *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
635                 t4_sq_consume(wq);
636         } else {
637                 PDBG("%s completing rq idx %u\n", __func__, wq->rq.cidx);
638                 *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
639                 BUG_ON(t4_rq_empty(wq));
640                 t4_rq_consume(wq);
641                 goto skip_cqe;
642         }
643
644 flush_wq:
645         /*
646          * Flush any completed cqes that are now in-order.
647          */
648         flush_completed_wrs(wq, cq);
649
650 skip_cqe:
651         if (SW_CQE(hw_cqe)) {
652                 PDBG("%s cq %p cqid 0x%x skip sw cqe cidx %u\n",
653                      __func__, cq, cq->cqid, cq->sw_cidx);
654                 t4_swcq_consume(cq);
655         } else {
656                 PDBG("%s cq %p cqid 0x%x skip hw cqe cidx %u\n",
657                      __func__, cq, cq->cqid, cq->cidx);
658                 t4_hwcq_consume(cq);
659         }
660         return ret;
661 }
662
663 /*
664  * Get one cq entry from c4iw and map it to openib.
665  *
666  * Returns:
667  *      0                       cqe returned
668  *      -ENODATA                EMPTY;
669  *      -EAGAIN                 caller must try again
670  *      any other -errno        fatal error
671  */
672 static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
673 {
674         struct c4iw_qp *qhp = NULL;
675         struct t4_cqe uninitialized_var(cqe), *rd_cqe;
676         struct t4_wq *wq;
677         u32 credit = 0;
678         u8 cqe_flushed;
679         u64 cookie = 0;
680         int ret;
681
682         ret = t4_next_cqe(&chp->cq, &rd_cqe);
683
684         if (ret)
685                 return ret;
686
687         qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe));
688         if (!qhp)
689                 wq = NULL;
690         else {
691                 spin_lock(&qhp->lock);
692                 wq = &(qhp->wq);
693         }
694         ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit);
695         if (ret)
696                 goto out;
697
698         wc->wr_id = cookie;
699         wc->qp = &qhp->ibqp;
700         wc->vendor_err = CQE_STATUS(&cqe);
701         wc->wc_flags = 0;
702
703         PDBG("%s qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x "
704              "lo 0x%x cookie 0x%llx\n", __func__, CQE_QPID(&cqe),
705              CQE_TYPE(&cqe), CQE_OPCODE(&cqe), CQE_STATUS(&cqe), CQE_LEN(&cqe),
706              CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe), (unsigned long long)cookie);
707
708         if (CQE_TYPE(&cqe) == 0) {
709                 if (!CQE_STATUS(&cqe))
710                         wc->byte_len = CQE_LEN(&cqe);
711                 else
712                         wc->byte_len = 0;
713                 wc->opcode = IB_WC_RECV;
714                 if (CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_INV ||
715                     CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_SE_INV) {
716                         wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe);
717                         wc->wc_flags |= IB_WC_WITH_INVALIDATE;
718                 }
719         } else {
720                 switch (CQE_OPCODE(&cqe)) {
721                 case FW_RI_RDMA_WRITE:
722                         wc->opcode = IB_WC_RDMA_WRITE;
723                         break;
724                 case FW_RI_READ_REQ:
725                         wc->opcode = IB_WC_RDMA_READ;
726                         wc->byte_len = CQE_LEN(&cqe);
727                         break;
728                 case FW_RI_SEND_WITH_INV:
729                 case FW_RI_SEND_WITH_SE_INV:
730                         wc->opcode = IB_WC_SEND;
731                         wc->wc_flags |= IB_WC_WITH_INVALIDATE;
732                         break;
733                 case FW_RI_SEND:
734                 case FW_RI_SEND_WITH_SE:
735                         wc->opcode = IB_WC_SEND;
736                         break;
737                 case FW_RI_BIND_MW:
738                         wc->opcode = IB_WC_BIND_MW;
739                         break;
740
741                 case FW_RI_LOCAL_INV:
742                         wc->opcode = IB_WC_LOCAL_INV;
743                         break;
744                 case FW_RI_FAST_REGISTER:
745                         wc->opcode = IB_WC_FAST_REG_MR;
746                         break;
747                 default:
748                         printk(KERN_ERR MOD "Unexpected opcode %d "
749                                "in the CQE received for QPID=0x%0x\n",
750                                CQE_OPCODE(&cqe), CQE_QPID(&cqe));
751                         ret = -EINVAL;
752                         goto out;
753                 }
754         }
755
756         if (cqe_flushed)
757                 wc->status = IB_WC_WR_FLUSH_ERR;
758         else {
759
760                 switch (CQE_STATUS(&cqe)) {
761                 case T4_ERR_SUCCESS:
762                         wc->status = IB_WC_SUCCESS;
763                         break;
764                 case T4_ERR_STAG:
765                         wc->status = IB_WC_LOC_ACCESS_ERR;
766                         break;
767                 case T4_ERR_PDID:
768                         wc->status = IB_WC_LOC_PROT_ERR;
769                         break;
770                 case T4_ERR_QPID:
771                 case T4_ERR_ACCESS:
772                         wc->status = IB_WC_LOC_ACCESS_ERR;
773                         break;
774                 case T4_ERR_WRAP:
775                         wc->status = IB_WC_GENERAL_ERR;
776                         break;
777                 case T4_ERR_BOUND:
778                         wc->status = IB_WC_LOC_LEN_ERR;
779                         break;
780                 case T4_ERR_INVALIDATE_SHARED_MR:
781                 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
782                         wc->status = IB_WC_MW_BIND_ERR;
783                         break;
784                 case T4_ERR_CRC:
785                 case T4_ERR_MARKER:
786                 case T4_ERR_PDU_LEN_ERR:
787                 case T4_ERR_OUT_OF_RQE:
788                 case T4_ERR_DDP_VERSION:
789                 case T4_ERR_RDMA_VERSION:
790                 case T4_ERR_DDP_QUEUE_NUM:
791                 case T4_ERR_MSN:
792                 case T4_ERR_TBIT:
793                 case T4_ERR_MO:
794                 case T4_ERR_MSN_RANGE:
795                 case T4_ERR_IRD_OVERFLOW:
796                 case T4_ERR_OPCODE:
797                 case T4_ERR_INTERNAL_ERR:
798                         wc->status = IB_WC_FATAL_ERR;
799                         break;
800                 case T4_ERR_SWFLUSH:
801                         wc->status = IB_WC_WR_FLUSH_ERR;
802                         break;
803                 default:
804                         printk(KERN_ERR MOD
805                                "Unexpected cqe_status 0x%x for QPID=0x%0x\n",
806                                CQE_STATUS(&cqe), CQE_QPID(&cqe));
807                         ret = -EINVAL;
808                 }
809         }
810 out:
811         if (wq)
812                 spin_unlock(&qhp->lock);
813         return ret;
814 }
815
816 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
817 {
818         struct c4iw_cq *chp;
819         unsigned long flags;
820         int npolled;
821         int err = 0;
822
823         chp = to_c4iw_cq(ibcq);
824
825         spin_lock_irqsave(&chp->lock, flags);
826         for (npolled = 0; npolled < num_entries; ++npolled) {
827                 do {
828                         err = c4iw_poll_cq_one(chp, wc + npolled);
829                 } while (err == -EAGAIN);
830                 if (err)
831                         break;
832         }
833         spin_unlock_irqrestore(&chp->lock, flags);
834         return !err || err == -ENODATA ? npolled : err;
835 }
836
837 int c4iw_destroy_cq(struct ib_cq *ib_cq)
838 {
839         struct c4iw_cq *chp;
840         struct c4iw_ucontext *ucontext;
841
842         PDBG("%s ib_cq %p\n", __func__, ib_cq);
843         chp = to_c4iw_cq(ib_cq);
844
845         remove_handle(chp->rhp, &chp->rhp->cqidr, chp->cq.cqid);
846         atomic_dec(&chp->refcnt);
847         wait_event(chp->wait, !atomic_read(&chp->refcnt));
848
849         ucontext = ib_cq->uobject ? to_c4iw_ucontext(ib_cq->uobject->context)
850                                   : NULL;
851         destroy_cq(&chp->rhp->rdev, &chp->cq,
852                    ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx);
853         kfree(chp);
854         return 0;
855 }
856
857 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
858                              int vector, struct ib_ucontext *ib_context,
859                              struct ib_udata *udata)
860 {
861         struct c4iw_dev *rhp;
862         struct c4iw_cq *chp;
863         struct c4iw_create_cq_resp uresp;
864         struct c4iw_ucontext *ucontext = NULL;
865         int ret;
866         size_t memsize, hwentries;
867         struct c4iw_mm_entry *mm, *mm2;
868
869         PDBG("%s ib_dev %p entries %d\n", __func__, ibdev, entries);
870
871         rhp = to_c4iw_dev(ibdev);
872
873         chp = kzalloc(sizeof(*chp), GFP_KERNEL);
874         if (!chp)
875                 return ERR_PTR(-ENOMEM);
876
877         if (ib_context)
878                 ucontext = to_c4iw_ucontext(ib_context);
879
880         /* account for the status page. */
881         entries++;
882
883         /* IQ needs one extra entry to differentiate full vs empty. */
884         entries++;
885
886         /*
887          * entries must be multiple of 16 for HW.
888          */
889         entries = roundup(entries, 16);
890
891         /*
892          * Make actual HW queue 2x to avoid cdix_inc overflows.
893          */
894         hwentries = min(entries * 2, T4_MAX_IQ_SIZE);
895
896         /*
897          * Make HW queue at least 64 entries so GTS updates aren't too
898          * frequent.
899          */
900         if (hwentries < 64)
901                 hwentries = 64;
902
903         memsize = hwentries * sizeof *chp->cq.queue;
904
905         /*
906          * memsize must be a multiple of the page size if its a user cq.
907          */
908         if (ucontext) {
909                 memsize = roundup(memsize, PAGE_SIZE);
910                 hwentries = memsize / sizeof *chp->cq.queue;
911                 while (hwentries > T4_MAX_IQ_SIZE) {
912                         memsize -= PAGE_SIZE;
913                         hwentries = memsize / sizeof *chp->cq.queue;
914                 }
915         }
916         chp->cq.size = hwentries;
917         chp->cq.memsize = memsize;
918
919         ret = create_cq(&rhp->rdev, &chp->cq,
920                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
921         if (ret)
922                 goto err1;
923
924         chp->rhp = rhp;
925         chp->cq.size--;                         /* status page */
926         chp->ibcq.cqe = entries - 2;
927         spin_lock_init(&chp->lock);
928         spin_lock_init(&chp->comp_handler_lock);
929         atomic_set(&chp->refcnt, 1);
930         init_waitqueue_head(&chp->wait);
931         ret = insert_handle(rhp, &rhp->cqidr, chp, chp->cq.cqid);
932         if (ret)
933                 goto err2;
934
935         if (ucontext) {
936                 mm = kmalloc(sizeof *mm, GFP_KERNEL);
937                 if (!mm)
938                         goto err3;
939                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
940                 if (!mm2)
941                         goto err4;
942
943                 memset(&uresp, 0, sizeof(uresp));
944                 uresp.qid_mask = rhp->rdev.cqmask;
945                 uresp.cqid = chp->cq.cqid;
946                 uresp.size = chp->cq.size;
947                 uresp.memsize = chp->cq.memsize;
948                 spin_lock(&ucontext->mmap_lock);
949                 uresp.key = ucontext->key;
950                 ucontext->key += PAGE_SIZE;
951                 uresp.gts_key = ucontext->key;
952                 ucontext->key += PAGE_SIZE;
953                 spin_unlock(&ucontext->mmap_lock);
954                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
955                 if (ret)
956                         goto err5;
957
958                 mm->key = uresp.key;
959                 mm->addr = virt_to_phys(chp->cq.queue);
960                 mm->len = chp->cq.memsize;
961                 insert_mmap(ucontext, mm);
962
963                 mm2->key = uresp.gts_key;
964                 mm2->addr = chp->cq.ugts;
965                 mm2->len = PAGE_SIZE;
966                 insert_mmap(ucontext, mm2);
967         }
968         PDBG("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n",
969              __func__, chp->cq.cqid, chp, chp->cq.size,
970              chp->cq.memsize,
971              (unsigned long long) chp->cq.dma_addr);
972         return &chp->ibcq;
973 err5:
974         kfree(mm2);
975 err4:
976         kfree(mm);
977 err3:
978         remove_handle(rhp, &rhp->cqidr, chp->cq.cqid);
979 err2:
980         destroy_cq(&chp->rhp->rdev, &chp->cq,
981                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
982 err1:
983         kfree(chp);
984         return ERR_PTR(ret);
985 }
986
987 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata)
988 {
989         return -ENOSYS;
990 }
991
992 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
993 {
994         struct c4iw_cq *chp;
995         int ret;
996         unsigned long flag;
997
998         chp = to_c4iw_cq(ibcq);
999         spin_lock_irqsave(&chp->lock, flag);
1000         ret = t4_arm_cq(&chp->cq,
1001                         (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED);
1002         spin_unlock_irqrestore(&chp->lock, flag);
1003         if (ret && !(flags & IB_CQ_REPORT_MISSED_EVENTS))
1004                 ret = 0;
1005         return ret;
1006 }