2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
49 #include <asm/byteorder.h>
51 #include <net/net_namespace.h>
53 #include <rdma/ib_verbs.h>
54 #include <rdma/iw_cm.h>
55 #include <rdma/rdma_netlink.h>
56 #include <rdma/iw_portmap.h>
59 #include "cxgb4_uld.h"
63 #define DRV_NAME "iw_cxgb4"
64 #define MOD DRV_NAME ":"
66 extern int c4iw_debug;
67 #define PDBG(fmt, args...) \
70 printk(MOD fmt, ## args); \
75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
78 static inline void *cplhdr(struct sk_buff *skb)
83 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
84 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
86 struct c4iw_id_table {
88 u32 start; /* logical minimal id */
89 u32 last; /* hint for find */
95 struct c4iw_resource {
96 struct c4iw_id_table tpt_table;
97 struct c4iw_id_table qid_table;
98 struct c4iw_id_table pdid_table;
101 struct c4iw_qid_list {
102 struct list_head entry;
106 struct c4iw_dev_ucontext {
107 struct list_head qpids;
108 struct list_head cqids;
112 enum c4iw_rdev_flags {
113 T4_FATAL_ERROR = (1<<0),
114 T4_STATUS_PAGE_DISABLED = (1<<1),
126 struct c4iw_stat qid;
128 struct c4iw_stat stag;
129 struct c4iw_stat pbl;
130 struct c4iw_stat rqt;
131 struct c4iw_stat ocqp;
135 u64 db_state_transitions;
136 u64 db_fc_interruptions;
138 u64 act_ofld_conn_fails;
139 u64 pas_ofld_conn_fails;
143 struct c4iw_hw_queue {
144 int t4_eq_status_entries;
154 struct wr_log_entry {
155 struct timespec post_host_ts;
156 struct timespec poll_host_ts;
167 struct c4iw_resource resource;
168 unsigned long qpshift;
170 unsigned long cqshift;
172 struct c4iw_dev_ucontext uctx;
173 struct gen_pool *pbl_pool;
174 struct gen_pool *rqt_pool;
175 struct gen_pool *ocqp_pool;
177 struct cxgb4_lld_info lldi;
178 unsigned long bar2_pa;
179 void __iomem *bar2_kva;
180 unsigned long oc_mw_pa;
181 void __iomem *oc_mw_kva;
182 struct c4iw_stats stats;
183 struct c4iw_hw_queue hw_queue;
184 struct t4_dev_status_page *status_page;
186 struct wr_log_entry *wr_log;
190 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
192 return rdev->flags & T4_FATAL_ERROR;
195 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
197 return (int)(rdev->lldi.vr->stag.size >> 5);
200 #define C4IW_WR_TO (60*HZ)
202 struct c4iw_wr_wait {
203 struct completion completion;
207 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
210 init_completion(&wr_waitp->completion);
213 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
216 complete(&wr_waitp->completion);
219 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
220 struct c4iw_wr_wait *wr_waitp,
226 if (c4iw_fatal_error(rdev)) {
227 wr_waitp->ret = -EIO;
231 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
233 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
234 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
235 rdev->flags |= T4_FATAL_ERROR;
236 wr_waitp->ret = -EIO;
240 PDBG("%s: FW reply %d tid %u qpid %u\n",
241 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
242 return wr_waitp->ret;
253 struct ib_device ibdev;
254 struct c4iw_rdev rdev;
255 u32 device_cap_flags;
260 struct mutex db_mutex;
261 struct dentry *debugfs_root;
262 enum db_state db_state;
263 struct idr hwtid_idr;
266 struct list_head db_fc_list;
270 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
272 return container_of(ibdev, struct c4iw_dev, ibdev);
275 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
277 return container_of(rdev, struct c4iw_dev, rdev);
280 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
282 return idr_find(&rhp->cqidr, cqid);
285 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
287 return idr_find(&rhp->qpidr, qpid);
290 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
292 return idr_find(&rhp->mmidr, mmid);
295 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
296 void *handle, u32 id, int lock)
301 idr_preload(GFP_KERNEL);
302 spin_lock_irq(&rhp->lock);
305 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
308 spin_unlock_irq(&rhp->lock);
312 BUG_ON(ret == -ENOSPC);
313 return ret < 0 ? ret : 0;
316 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
317 void *handle, u32 id)
319 return _insert_handle(rhp, idr, handle, id, 1);
322 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
323 void *handle, u32 id)
325 return _insert_handle(rhp, idr, handle, id, 0);
328 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
332 spin_lock_irq(&rhp->lock);
335 spin_unlock_irq(&rhp->lock);
338 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
340 _remove_handle(rhp, idr, id, 1);
343 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
344 struct idr *idr, u32 id)
346 _remove_handle(rhp, idr, id, 0);
349 extern uint c4iw_max_read_depth;
351 static inline int cur_max_read_depth(struct c4iw_dev *dev)
353 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
359 struct c4iw_dev *rhp;
362 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
364 return container_of(ibpd, struct c4iw_pd, ibpd);
367 struct tpt_attributes {
370 enum fw_ri_mem_perms perms;
379 u32 remote_invaliate_disable:1;
381 u32 mw_bind_enable:1;
387 struct ib_umem *umem;
388 struct c4iw_dev *rhp;
390 struct tpt_attributes attr;
393 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
395 return container_of(ibmr, struct c4iw_mr, ibmr);
400 struct c4iw_dev *rhp;
402 struct tpt_attributes attr;
405 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
407 return container_of(ibmw, struct c4iw_mw, ibmw);
410 struct c4iw_fr_page_list {
411 struct ib_fast_reg_page_list ibpl;
412 DEFINE_DMA_UNMAP_ADDR(mapping);
414 struct c4iw_dev *dev;
418 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
419 struct ib_fast_reg_page_list *ibpl)
421 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
426 struct c4iw_dev *rhp;
429 spinlock_t comp_handler_lock;
431 wait_queue_head_t wait;
434 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
436 return container_of(ibcq, struct c4iw_cq, ibcq);
439 struct c4iw_mpa_attributes {
441 u8 recv_marker_enabled;
442 u8 xmit_marker_enabled;
444 u8 enhanced_rdma_conn;
449 struct c4iw_qp_attributes {
455 u32 sq_max_sges_rdma_write;
459 u8 enable_rdma_write;
461 u8 enable_mmid0_fastreg;
466 char terminate_buffer[52];
467 u32 terminate_msg_len;
468 u8 is_terminate_local;
469 struct c4iw_mpa_attributes mpa_attr;
470 struct c4iw_ep *llp_stream_handle;
480 struct list_head db_fc_entry;
481 struct c4iw_dev *rhp;
483 struct c4iw_qp_attributes attr;
488 wait_queue_head_t wait;
489 struct timer_list timer;
493 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
495 return container_of(ibqp, struct c4iw_qp, ibqp);
498 struct c4iw_ucontext {
499 struct ib_ucontext ibucontext;
500 struct c4iw_dev_ucontext uctx;
502 spinlock_t mmap_lock;
503 struct list_head mmaps;
506 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
508 return container_of(c, struct c4iw_ucontext, ibucontext);
511 struct c4iw_mm_entry {
512 struct list_head entry;
518 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
519 u32 key, unsigned len)
521 struct list_head *pos, *nxt;
522 struct c4iw_mm_entry *mm;
524 spin_lock(&ucontext->mmap_lock);
525 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
527 mm = list_entry(pos, struct c4iw_mm_entry, entry);
528 if (mm->key == key && mm->len == len) {
529 list_del_init(&mm->entry);
530 spin_unlock(&ucontext->mmap_lock);
531 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
532 key, (unsigned long long) mm->addr, mm->len);
536 spin_unlock(&ucontext->mmap_lock);
540 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
541 struct c4iw_mm_entry *mm)
543 spin_lock(&ucontext->mmap_lock);
544 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
545 mm->key, (unsigned long long) mm->addr, mm->len);
546 list_add_tail(&mm->entry, &ucontext->mmaps);
547 spin_unlock(&ucontext->mmap_lock);
550 enum c4iw_qp_attr_mask {
551 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
552 C4IW_QP_ATTR_SQ_DB = 1<<1,
553 C4IW_QP_ATTR_RQ_DB = 1<<2,
554 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
555 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
556 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
557 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
558 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
559 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
560 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
561 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
562 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
563 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
564 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
565 C4IW_QP_ATTR_MAX_ORD |
566 C4IW_QP_ATTR_MAX_IRD |
567 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
568 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
569 C4IW_QP_ATTR_MPA_ATTR |
570 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
573 int c4iw_modify_qp(struct c4iw_dev *rhp,
575 enum c4iw_qp_attr_mask mask,
576 struct c4iw_qp_attributes *attrs,
583 C4IW_QP_STATE_TERMINATE,
584 C4IW_QP_STATE_CLOSING,
588 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
593 return C4IW_QP_STATE_IDLE;
595 return C4IW_QP_STATE_RTS;
597 return C4IW_QP_STATE_CLOSING;
599 return C4IW_QP_STATE_TERMINATE;
601 return C4IW_QP_STATE_ERROR;
607 static inline int to_ib_qp_state(int c4iw_qp_state)
609 switch (c4iw_qp_state) {
610 case C4IW_QP_STATE_IDLE:
612 case C4IW_QP_STATE_RTS:
614 case C4IW_QP_STATE_CLOSING:
616 case C4IW_QP_STATE_TERMINATE:
618 case C4IW_QP_STATE_ERROR:
624 static inline u32 c4iw_ib_to_tpt_access(int a)
626 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
627 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
628 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
629 FW_RI_MEM_ACCESS_LOCAL_READ;
632 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
634 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
635 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
638 enum c4iw_mmid_state {
639 C4IW_STAG_STATE_VALID,
640 C4IW_STAG_STATE_INVALID
643 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
645 #define MPA_KEY_REQ "MPA ID Req Frame"
646 #define MPA_KEY_REP "MPA ID Rep Frame"
648 #define MPA_MAX_PRIVATE_DATA 256
649 #define MPA_ENHANCED_RDMA_CONN 0x10
650 #define MPA_REJECT 0x20
652 #define MPA_MARKERS 0x80
653 #define MPA_FLAGS_MASK 0xE0
655 #define MPA_V2_PEER2PEER_MODEL 0x8000
656 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
657 #define MPA_V2_RDMA_WRITE_RTR 0x8000
658 #define MPA_V2_RDMA_READ_RTR 0x4000
659 #define MPA_V2_IRD_ORD_MASK 0x3FFF
661 #define c4iw_put_ep(ep) { \
662 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
663 ep, atomic_read(&((ep)->kref.refcount))); \
664 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
665 kref_put(&((ep)->kref), _c4iw_free_ep); \
668 #define c4iw_get_ep(ep) { \
669 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
670 ep, atomic_read(&((ep)->kref.refcount))); \
671 kref_get(&((ep)->kref)); \
673 void _c4iw_free_ep(struct kref *kref);
679 __be16 private_data_size;
683 struct mpa_v2_conn_params {
688 struct terminate_message {
695 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
697 enum c4iw_layers_types {
701 RDMAP_LOCAL_CATA = 0x00,
702 RDMAP_REMOTE_PROT = 0x01,
703 RDMAP_REMOTE_OP = 0x02,
704 DDP_LOCAL_CATA = 0x00,
705 DDP_TAGGED_ERR = 0x01,
706 DDP_UNTAGGED_ERR = 0x02,
710 enum c4iw_rdma_ecodes {
711 RDMAP_INV_STAG = 0x00,
712 RDMAP_BASE_BOUNDS = 0x01,
713 RDMAP_ACC_VIOL = 0x02,
714 RDMAP_STAG_NOT_ASSOC = 0x03,
715 RDMAP_TO_WRAP = 0x04,
716 RDMAP_INV_VERS = 0x05,
717 RDMAP_INV_OPCODE = 0x06,
718 RDMAP_STREAM_CATA = 0x07,
719 RDMAP_GLOBAL_CATA = 0x08,
720 RDMAP_CANT_INV_STAG = 0x09,
721 RDMAP_UNSPECIFIED = 0xff
724 enum c4iw_ddp_ecodes {
725 DDPT_INV_STAG = 0x00,
726 DDPT_BASE_BOUNDS = 0x01,
727 DDPT_STAG_NOT_ASSOC = 0x02,
729 DDPT_INV_VERS = 0x04,
731 DDPU_INV_MSN_NOBUF = 0x02,
732 DDPU_INV_MSN_RANGE = 0x03,
734 DDPU_MSG_TOOBIG = 0x05,
738 enum c4iw_mpa_ecodes {
740 MPA_MARKER_ERR = 0x03,
741 MPA_LOCAL_CATA = 0x05,
742 MPA_INSUFF_IRD = 0x06,
743 MPA_NOMATCH_RTR = 0x07,
762 PEER_ABORT_IN_PROGRESS = 0,
763 ABORT_REQ_IN_PROGRESS = 1,
764 RELEASE_RESOURCES = 2,
771 enum c4iw_ep_history {
791 CONN_RPL_UPCALL = 19,
792 ACT_RETRY_NOMEM = 20,
796 struct c4iw_ep_common {
797 struct iw_cm_id *cm_id;
799 struct c4iw_dev *dev;
800 enum c4iw_ep_state state;
803 struct sockaddr_storage local_addr;
804 struct sockaddr_storage remote_addr;
805 struct sockaddr_storage mapped_local_addr;
806 struct sockaddr_storage mapped_remote_addr;
807 struct c4iw_wr_wait wr_wait;
809 unsigned long history;
812 struct c4iw_listen_ep {
813 struct c4iw_ep_common com;
818 struct c4iw_ep_stats {
819 unsigned connect_neg_adv;
820 unsigned abort_neg_adv;
824 struct c4iw_ep_common com;
825 struct c4iw_ep *parent_ep;
826 struct timer_list timer;
827 struct list_head entry;
832 struct l2t_entry *l2t;
833 struct dst_entry *dst;
834 struct sk_buff *mpa_skb;
835 struct c4iw_mpa_attributes mpa_attr;
836 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
837 unsigned int mpa_pkt_len;
850 u8 retry_with_mpa_v1;
851 u8 tried_with_mpa_v1;
852 unsigned int retry_count;
855 struct c4iw_ep_stats stats;
858 static inline void print_addr(struct c4iw_ep_common *epc, const char *func,
862 #define SINA(a) (&(((struct sockaddr_in *)(a))->sin_addr.s_addr))
863 #define SINP(a) ntohs(((struct sockaddr_in *)(a))->sin_port)
864 #define SIN6A(a) (&(((struct sockaddr_in6 *)(a))->sin6_addr))
865 #define SIN6P(a) ntohs(((struct sockaddr_in6 *)(a))->sin6_port)
868 switch (epc->local_addr.ss_family) {
870 PDBG("%s %s %pI4:%u/%u <-> %pI4:%u/%u\n",
871 func, msg, SINA(&epc->local_addr),
872 SINP(&epc->local_addr),
873 SINP(&epc->mapped_local_addr),
874 SINA(&epc->remote_addr),
875 SINP(&epc->remote_addr),
876 SINP(&epc->mapped_remote_addr));
879 PDBG("%s %s %pI6:%u/%u <-> %pI6:%u/%u\n",
880 func, msg, SIN6A(&epc->local_addr),
881 SIN6P(&epc->local_addr),
882 SIN6P(&epc->mapped_local_addr),
883 SIN6A(&epc->remote_addr),
884 SIN6P(&epc->remote_addr),
885 SIN6P(&epc->mapped_remote_addr));
897 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
899 return cm_id->provider_data;
902 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
904 return cm_id->provider_data;
907 static inline int compute_wscale(int win)
911 while (wscale < 14 && (65535<<wscale) < win)
916 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
918 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
919 return infop->vr->ocq.size > 0;
925 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
926 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
927 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
928 u32 reserved, u32 flags);
929 void c4iw_id_table_free(struct c4iw_id_table *alloc);
931 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
933 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
934 struct l2t_entry *l2t);
935 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
936 struct c4iw_dev_ucontext *uctx);
937 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
938 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
939 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
940 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
941 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
942 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
943 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
944 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
945 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
946 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
947 void c4iw_destroy_resource(struct c4iw_resource *rscp);
948 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
949 int c4iw_register_device(struct c4iw_dev *dev);
950 void c4iw_unregister_device(struct c4iw_dev *dev);
951 int __init c4iw_cm_init(void);
952 void c4iw_cm_term(void);
953 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
954 struct c4iw_dev_ucontext *uctx);
955 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
956 struct c4iw_dev_ucontext *uctx);
957 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
958 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
959 struct ib_send_wr **bad_wr);
960 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
961 struct ib_recv_wr **bad_wr);
962 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
963 struct ib_mw_bind *mw_bind);
964 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
965 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
966 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
967 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
968 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
969 void c4iw_qp_add_ref(struct ib_qp *qp);
970 void c4iw_qp_rem_ref(struct ib_qp *qp);
971 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
972 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
973 struct ib_device *device,
975 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
976 int c4iw_dealloc_mw(struct ib_mw *mw);
977 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
978 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
979 u64 length, u64 virt, int acc,
980 struct ib_udata *udata);
981 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
982 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
983 struct ib_phys_buf *buffer_list,
987 int c4iw_reregister_phys_mem(struct ib_mr *mr,
990 struct ib_phys_buf *buffer_list,
992 int acc, u64 *iova_start);
993 int c4iw_dereg_mr(struct ib_mr *ib_mr);
994 int c4iw_destroy_cq(struct ib_cq *ib_cq);
995 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
997 struct ib_ucontext *ib_context,
998 struct ib_udata *udata);
999 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
1000 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1001 int c4iw_destroy_qp(struct ib_qp *ib_qp);
1002 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
1003 struct ib_qp_init_attr *attrs,
1004 struct ib_udata *udata);
1005 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1006 int attr_mask, struct ib_udata *udata);
1007 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1008 int attr_mask, struct ib_qp_init_attr *init_attr);
1009 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
1010 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
1011 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1012 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
1013 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1014 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
1015 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1016 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1017 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
1018 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
1019 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
1020 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1021 int c4iw_flush_sq(struct c4iw_qp *qhp);
1022 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1023 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
1024 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1025 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1026 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1027 struct c4iw_dev_ucontext *uctx);
1028 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1029 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1030 struct c4iw_dev_ucontext *uctx);
1031 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1033 extern struct cxgb4_client t4c_client;
1034 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1035 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1036 extern int c4iw_wr_log;
1037 extern int db_fc_threshold;
1038 extern int db_coalescing_threshold;
1039 extern int use_dsgl;