2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
61 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
64 spin_lock_irqsave(&qhp->lock, flag);
65 qhp->attr.state = state;
66 spin_unlock_irqrestore(&qhp->lock, flag);
69 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
71 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
74 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
76 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
77 pci_unmap_addr(sq, mapping));
80 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
83 dealloc_oc_sq(rdev, sq);
85 dealloc_host_sq(rdev, sq);
88 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
90 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
92 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
95 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
96 rdev->lldi.vr->ocq.start;
97 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
98 rdev->lldi.vr->ocq.start);
99 sq->flags |= T4_SQ_ONCHIP;
103 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
105 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
106 &(sq->dma_addr), GFP_KERNEL);
109 sq->phys_addr = virt_to_phys(sq->queue);
110 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
114 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
118 ret = alloc_oc_sq(rdev, sq);
120 ret = alloc_host_sq(rdev, sq);
124 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct c4iw_dev_ucontext *uctx)
128 * uP clears EQ contexts when the connection exits rdma mode,
129 * so no need to post a RESET WR for these EQs.
131 dma_free_coherent(&(rdev->lldi.pdev->dev),
132 wq->rq.memsize, wq->rq.queue,
133 dma_unmap_addr(&wq->rq, mapping));
134 dealloc_sq(rdev, &wq->sq);
135 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
138 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
139 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
143 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 struct t4_cq *rcq, struct t4_cq *scq,
145 struct c4iw_dev_ucontext *uctx)
147 int user = (uctx != &rdev->uctx);
148 struct fw_ri_res_wr *res_wr;
149 struct fw_ri_res *res;
151 struct c4iw_wr_wait wr_wait;
156 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
160 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
167 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
174 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
183 * RQT must be a power of 2.
185 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
186 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
187 if (!wq->rq.rqt_hwaddr) {
192 ret = alloc_sq(rdev, &wq->sq, user);
195 memset(wq->sq.queue, 0, wq->sq.memsize);
196 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
198 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
199 wq->rq.memsize, &(wq->rq.dma_addr),
205 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
206 __func__, wq->sq.queue,
207 (unsigned long long)virt_to_phys(wq->sq.queue),
209 (unsigned long long)virt_to_phys(wq->rq.queue));
210 memset(wq->rq.queue, 0, wq->rq.memsize);
211 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
213 wq->db = rdev->lldi.db_reg;
214 wq->gts = rdev->lldi.gts_reg;
216 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
217 (wq->sq.qid << rdev->qpshift);
218 wq->sq.udb &= PAGE_MASK;
219 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
220 (wq->rq.qid << rdev->qpshift);
221 wq->rq.udb &= PAGE_MASK;
226 /* build fw_ri_res_wr */
227 wr_len = sizeof *res_wr + 2 * sizeof *res;
229 skb = alloc_skb(wr_len, GFP_KERNEL);
234 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
236 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
237 memset(res_wr, 0, wr_len);
238 res_wr->op_nres = cpu_to_be32(
239 FW_WR_OP(FW_RI_RES_WR) |
240 V_FW_RI_RES_WR_NRES(2) |
242 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
243 res_wr->cookie = (unsigned long) &wr_wait;
245 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
246 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
249 * eqsize is the number of 64B entries plus the status page size.
251 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
253 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
254 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
255 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
256 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
257 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
258 V_FW_RI_RES_WR_IQID(scq->cqid));
259 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
260 V_FW_RI_RES_WR_DCAEN(0) |
261 V_FW_RI_RES_WR_DCACPU(0) |
262 V_FW_RI_RES_WR_FBMIN(2) |
263 V_FW_RI_RES_WR_FBMAX(2) |
264 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
265 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
266 V_FW_RI_RES_WR_EQSIZE(eqsize));
267 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
268 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
270 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
271 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
274 * eqsize is the number of 64B entries plus the status page size.
276 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
277 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
278 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
279 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
280 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
281 V_FW_RI_RES_WR_IQID(rcq->cqid));
282 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
283 V_FW_RI_RES_WR_DCAEN(0) |
284 V_FW_RI_RES_WR_DCACPU(0) |
285 V_FW_RI_RES_WR_FBMIN(2) |
286 V_FW_RI_RES_WR_FBMAX(2) |
287 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
288 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
289 V_FW_RI_RES_WR_EQSIZE(eqsize));
290 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
291 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
293 c4iw_init_wr_wait(&wr_wait);
295 ret = c4iw_ofld_send(rdev, skb);
298 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
302 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
303 __func__, wq->sq.qid, wq->rq.qid, wq->db,
304 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
308 dma_free_coherent(&(rdev->lldi.pdev->dev),
309 wq->rq.memsize, wq->rq.queue,
310 dma_unmap_addr(&wq->rq, mapping));
312 dealloc_sq(rdev, &wq->sq);
314 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
320 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
322 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
326 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
327 struct ib_send_wr *wr, int max, u32 *plenp)
334 dstp = (u8 *)immdp->data;
335 for (i = 0; i < wr->num_sge; i++) {
336 if ((plen + wr->sg_list[i].length) > max)
338 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
339 plen += wr->sg_list[i].length;
340 rem = wr->sg_list[i].length;
342 if (dstp == (u8 *)&sq->queue[sq->size])
343 dstp = (u8 *)sq->queue;
344 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
347 len = (u8 *)&sq->queue[sq->size] - dstp;
348 memcpy(dstp, srcp, len);
354 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
356 memset(dstp, 0, len);
357 immdp->op = FW_RI_DATA_IMMD;
360 immdp->immdlen = cpu_to_be32(plen);
365 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
366 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
367 int num_sge, u32 *plenp)
372 __be64 *flitp = (__be64 *)isglp->sge;
374 for (i = 0; i < num_sge; i++) {
375 if ((plen + sg_list[i].length) < plen)
377 plen += sg_list[i].length;
378 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
380 if (++flitp == queue_end)
382 *flitp = cpu_to_be64(sg_list[i].addr);
383 if (++flitp == queue_end)
386 *flitp = (__force __be64)0;
387 isglp->op = FW_RI_DATA_ISGL;
389 isglp->nsge = cpu_to_be16(num_sge);
396 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
397 struct ib_send_wr *wr, u8 *len16)
403 if (wr->num_sge > T4_MAX_SEND_SGE)
405 switch (wr->opcode) {
407 if (wr->send_flags & IB_SEND_SOLICITED)
408 wqe->send.sendop_pkd = cpu_to_be32(
409 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
411 wqe->send.sendop_pkd = cpu_to_be32(
412 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
413 wqe->send.stag_inv = 0;
415 case IB_WR_SEND_WITH_INV:
416 if (wr->send_flags & IB_SEND_SOLICITED)
417 wqe->send.sendop_pkd = cpu_to_be32(
418 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
420 wqe->send.sendop_pkd = cpu_to_be32(
421 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
422 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
431 if (wr->send_flags & IB_SEND_INLINE) {
432 ret = build_immd(sq, wqe->send.u.immd_src, wr,
433 T4_MAX_SEND_INLINE, &plen);
436 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
439 ret = build_isgl((__be64 *)sq->queue,
440 (__be64 *)&sq->queue[sq->size],
441 wqe->send.u.isgl_src,
442 wr->sg_list, wr->num_sge, &plen);
445 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
446 wr->num_sge * sizeof(struct fw_ri_sge);
449 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
450 wqe->send.u.immd_src[0].r1 = 0;
451 wqe->send.u.immd_src[0].r2 = 0;
452 wqe->send.u.immd_src[0].immdlen = 0;
453 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
456 *len16 = DIV_ROUND_UP(size, 16);
457 wqe->send.plen = cpu_to_be32(plen);
461 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
462 struct ib_send_wr *wr, u8 *len16)
468 if (wr->num_sge > T4_MAX_SEND_SGE)
471 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
472 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
474 if (wr->send_flags & IB_SEND_INLINE) {
475 ret = build_immd(sq, wqe->write.u.immd_src, wr,
476 T4_MAX_WRITE_INLINE, &plen);
479 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
482 ret = build_isgl((__be64 *)sq->queue,
483 (__be64 *)&sq->queue[sq->size],
484 wqe->write.u.isgl_src,
485 wr->sg_list, wr->num_sge, &plen);
488 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
489 wr->num_sge * sizeof(struct fw_ri_sge);
492 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
493 wqe->write.u.immd_src[0].r1 = 0;
494 wqe->write.u.immd_src[0].r2 = 0;
495 wqe->write.u.immd_src[0].immdlen = 0;
496 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
499 *len16 = DIV_ROUND_UP(size, 16);
500 wqe->write.plen = cpu_to_be32(plen);
504 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
509 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
510 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
512 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
513 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
514 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
515 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
517 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
519 wqe->read.stag_src = cpu_to_be32(2);
520 wqe->read.to_src_hi = 0;
521 wqe->read.to_src_lo = 0;
522 wqe->read.stag_sink = cpu_to_be32(2);
524 wqe->read.to_sink_hi = 0;
525 wqe->read.to_sink_lo = 0;
529 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
533 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
534 struct ib_recv_wr *wr, u8 *len16)
538 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
539 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
540 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
543 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
544 wr->num_sge * sizeof(struct fw_ri_sge), 16);
548 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
549 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
552 struct fw_ri_immd *imdp;
555 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
558 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
561 wqe->fr.qpbinde_to_dcacpu = 0;
562 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
563 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
564 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
566 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
567 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
568 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
569 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
572 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
573 struct c4iw_fr_page_list *c4pl =
574 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
575 struct fw_ri_dsgl *sglp;
577 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
578 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
580 wr->wr.fast_reg.page_list->page_list[i]);
583 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
584 sglp->op = FW_RI_DATA_DSGL;
586 sglp->nsge = cpu_to_be16(1);
587 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
588 sglp->len0 = cpu_to_be32(pbllen);
590 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
592 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
593 imdp->op = FW_RI_DATA_IMMD;
596 imdp->immdlen = cpu_to_be32(pbllen);
597 p = (__be64 *)(imdp + 1);
599 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
601 (u64)wr->wr.fast_reg.page_list->page_list[i]);
603 if (++p == (__be64 *)&sq->queue[sq->size])
604 p = (__be64 *)sq->queue;
610 if (++p == (__be64 *)&sq->queue[sq->size])
611 p = (__be64 *)sq->queue;
613 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
619 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
622 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
624 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
628 void c4iw_qp_add_ref(struct ib_qp *qp)
630 PDBG("%s ib_qp %p\n", __func__, qp);
631 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
634 void c4iw_qp_rem_ref(struct ib_qp *qp)
636 PDBG("%s ib_qp %p\n", __func__, qp);
637 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
638 wake_up(&(to_c4iw_qp(qp)->wait));
641 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
643 if (list_empty(entry))
644 list_add_tail(entry, head);
647 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
651 spin_lock_irqsave(&qhp->rhp->lock, flags);
652 spin_lock(&qhp->lock);
653 if (qhp->rhp->db_state == NORMAL) {
654 t4_ring_sq_db(&qhp->wq, inc);
656 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
657 qhp->wq.sq.wq_pidx_inc += inc;
659 spin_unlock(&qhp->lock);
660 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
664 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
668 spin_lock_irqsave(&qhp->rhp->lock, flags);
669 spin_lock(&qhp->lock);
670 if (qhp->rhp->db_state == NORMAL) {
671 t4_ring_rq_db(&qhp->wq, inc);
673 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
674 qhp->wq.rq.wq_pidx_inc += inc;
676 spin_unlock(&qhp->lock);
677 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
681 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
682 struct ib_send_wr **bad_wr)
686 enum fw_wr_opcodes fw_opcode = 0;
687 enum fw_ri_wr_flags fw_flags;
691 struct t4_swsqe *swsqe;
695 qhp = to_c4iw_qp(ibqp);
696 spin_lock_irqsave(&qhp->lock, flag);
697 if (t4_wq_in_error(&qhp->wq)) {
698 spin_unlock_irqrestore(&qhp->lock, flag);
701 num_wrs = t4_sq_avail(&qhp->wq);
703 spin_unlock_irqrestore(&qhp->lock, flag);
712 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
713 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
716 if (wr->send_flags & IB_SEND_SOLICITED)
717 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
718 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
719 fw_flags |= FW_RI_COMPLETION_FLAG;
720 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
721 switch (wr->opcode) {
722 case IB_WR_SEND_WITH_INV:
724 if (wr->send_flags & IB_SEND_FENCE)
725 fw_flags |= FW_RI_READ_FENCE_FLAG;
726 fw_opcode = FW_RI_SEND_WR;
727 if (wr->opcode == IB_WR_SEND)
728 swsqe->opcode = FW_RI_SEND;
730 swsqe->opcode = FW_RI_SEND_WITH_INV;
731 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
733 case IB_WR_RDMA_WRITE:
734 fw_opcode = FW_RI_RDMA_WRITE_WR;
735 swsqe->opcode = FW_RI_RDMA_WRITE;
736 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
738 case IB_WR_RDMA_READ:
739 case IB_WR_RDMA_READ_WITH_INV:
740 fw_opcode = FW_RI_RDMA_READ_WR;
741 swsqe->opcode = FW_RI_READ_REQ;
742 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
743 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
746 err = build_rdma_read(wqe, wr, &len16);
749 swsqe->read_len = wr->sg_list[0].length;
750 if (!qhp->wq.sq.oldest_read)
751 qhp->wq.sq.oldest_read = swsqe;
753 case IB_WR_FAST_REG_MR:
754 fw_opcode = FW_RI_FR_NSMR_WR;
755 swsqe->opcode = FW_RI_FAST_REGISTER;
756 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
758 qhp->rhp->rdev.lldi.adapter_type) ?
761 case IB_WR_LOCAL_INV:
762 if (wr->send_flags & IB_SEND_FENCE)
763 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
764 fw_opcode = FW_RI_INV_LSTAG_WR;
765 swsqe->opcode = FW_RI_LOCAL_INV;
766 err = build_inv_stag(wqe, wr, &len16);
769 PDBG("%s post of type=%d TBD!\n", __func__,
777 swsqe->idx = qhp->wq.sq.pidx;
779 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
782 swsqe->wr_id = wr->wr_id;
784 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
786 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
787 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
788 swsqe->opcode, swsqe->read_len);
791 t4_sq_produce(&qhp->wq, len16);
792 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
794 if (!qhp->rhp->rdev.status_page->db_off) {
795 t4_ring_sq_db(&qhp->wq, idx);
796 spin_unlock_irqrestore(&qhp->lock, flag);
798 spin_unlock_irqrestore(&qhp->lock, flag);
799 ring_kernel_sq_db(qhp, idx);
804 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
805 struct ib_recv_wr **bad_wr)
809 union t4_recv_wr *wqe;
815 qhp = to_c4iw_qp(ibqp);
816 spin_lock_irqsave(&qhp->lock, flag);
817 if (t4_wq_in_error(&qhp->wq)) {
818 spin_unlock_irqrestore(&qhp->lock, flag);
821 num_wrs = t4_rq_avail(&qhp->wq);
823 spin_unlock_irqrestore(&qhp->lock, flag);
827 if (wr->num_sge > T4_MAX_RECV_SGE) {
832 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
836 err = build_rdma_recv(qhp, wqe, wr, &len16);
844 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
846 wqe->recv.opcode = FW_RI_RECV_WR;
848 wqe->recv.wrid = qhp->wq.rq.pidx;
852 wqe->recv.len16 = len16;
853 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
854 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
855 t4_rq_produce(&qhp->wq, len16);
856 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
860 if (!qhp->rhp->rdev.status_page->db_off) {
861 t4_ring_rq_db(&qhp->wq, idx);
862 spin_unlock_irqrestore(&qhp->lock, flag);
864 spin_unlock_irqrestore(&qhp->lock, flag);
865 ring_kernel_rq_db(qhp, idx);
870 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
875 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
885 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
890 status = CQE_STATUS(err_cqe);
891 opcode = CQE_OPCODE(err_cqe);
892 rqtype = RQ_TYPE(err_cqe);
893 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
894 (opcode == FW_RI_SEND_WITH_SE_INV);
895 tagged = (opcode == FW_RI_RDMA_WRITE) ||
896 (rqtype && (opcode == FW_RI_READ_RESP));
901 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
902 *ecode = RDMAP_CANT_INV_STAG;
904 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
905 *ecode = RDMAP_INV_STAG;
909 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
910 if ((opcode == FW_RI_SEND_WITH_INV) ||
911 (opcode == FW_RI_SEND_WITH_SE_INV))
912 *ecode = RDMAP_CANT_INV_STAG;
914 *ecode = RDMAP_STAG_NOT_ASSOC;
917 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
918 *ecode = RDMAP_STAG_NOT_ASSOC;
921 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
922 *ecode = RDMAP_ACC_VIOL;
925 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
926 *ecode = RDMAP_TO_WRAP;
930 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
931 *ecode = DDPT_BASE_BOUNDS;
933 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
934 *ecode = RDMAP_BASE_BOUNDS;
937 case T4_ERR_INVALIDATE_SHARED_MR:
938 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
939 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
940 *ecode = RDMAP_CANT_INV_STAG;
943 case T4_ERR_ECC_PSTAG:
944 case T4_ERR_INTERNAL_ERR:
945 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
948 case T4_ERR_OUT_OF_RQE:
949 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
950 *ecode = DDPU_INV_MSN_NOBUF;
952 case T4_ERR_PBL_ADDR_BOUND:
953 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
954 *ecode = DDPT_BASE_BOUNDS;
957 *layer_type = LAYER_MPA|DDP_LLP;
958 *ecode = MPA_CRC_ERR;
961 *layer_type = LAYER_MPA|DDP_LLP;
962 *ecode = MPA_MARKER_ERR;
964 case T4_ERR_PDU_LEN_ERR:
965 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
966 *ecode = DDPU_MSG_TOOBIG;
968 case T4_ERR_DDP_VERSION:
970 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
971 *ecode = DDPT_INV_VERS;
973 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
974 *ecode = DDPU_INV_VERS;
977 case T4_ERR_RDMA_VERSION:
978 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
979 *ecode = RDMAP_INV_VERS;
982 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
983 *ecode = RDMAP_INV_OPCODE;
985 case T4_ERR_DDP_QUEUE_NUM:
986 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
987 *ecode = DDPU_INV_QN;
991 case T4_ERR_MSN_RANGE:
992 case T4_ERR_IRD_OVERFLOW:
993 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
994 *ecode = DDPU_INV_MSN_RANGE;
997 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1001 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1002 *ecode = DDPU_INV_MO;
1005 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1011 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1014 struct fw_ri_wr *wqe;
1015 struct sk_buff *skb;
1016 struct terminate_message *term;
1018 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1021 skb = alloc_skb(sizeof *wqe, gfp);
1024 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1026 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1027 memset(wqe, 0, sizeof *wqe);
1028 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1029 wqe->flowid_len16 = cpu_to_be32(
1030 FW_WR_FLOWID(qhp->ep->hwtid) |
1031 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1033 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1034 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1035 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1036 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1037 term->layer_etype = qhp->attr.layer_etype;
1038 term->ecode = qhp->attr.ecode;
1040 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1041 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1045 * Assumes qhp lock is held.
1047 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1048 struct c4iw_cq *schp)
1054 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1056 /* locking hierarchy: cq lock first, then qp lock. */
1057 spin_lock_irqsave(&rchp->lock, flag);
1058 spin_lock(&qhp->lock);
1060 if (qhp->wq.flushed) {
1061 spin_unlock(&qhp->lock);
1062 spin_unlock_irqrestore(&rchp->lock, flag);
1065 qhp->wq.flushed = 1;
1067 c4iw_flush_hw_cq(rchp);
1068 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1069 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1070 spin_unlock(&qhp->lock);
1071 spin_unlock_irqrestore(&rchp->lock, flag);
1073 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1074 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1075 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1078 /* locking hierarchy: cq lock first, then qp lock. */
1079 spin_lock_irqsave(&schp->lock, flag);
1080 spin_lock(&qhp->lock);
1082 c4iw_flush_hw_cq(schp);
1083 flushed = c4iw_flush_sq(qhp);
1084 spin_unlock(&qhp->lock);
1085 spin_unlock_irqrestore(&schp->lock, flag);
1087 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1088 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
1089 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1093 static void flush_qp(struct c4iw_qp *qhp)
1095 struct c4iw_cq *rchp, *schp;
1098 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1099 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1101 t4_set_wq_in_error(&qhp->wq);
1102 if (qhp->ibqp.uobject) {
1103 t4_set_cq_in_error(&rchp->cq);
1104 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1105 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1106 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1108 t4_set_cq_in_error(&schp->cq);
1109 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1110 (*schp->ibcq.comp_handler)(&schp->ibcq,
1111 schp->ibcq.cq_context);
1112 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1116 __flush_qp(qhp, rchp, schp);
1119 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1122 struct fw_ri_wr *wqe;
1124 struct sk_buff *skb;
1126 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1129 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1132 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1134 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1135 memset(wqe, 0, sizeof *wqe);
1136 wqe->op_compl = cpu_to_be32(
1137 FW_WR_OP(FW_RI_INIT_WR) |
1139 wqe->flowid_len16 = cpu_to_be32(
1140 FW_WR_FLOWID(ep->hwtid) |
1141 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1142 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1144 wqe->u.fini.type = FW_RI_TYPE_FINI;
1145 ret = c4iw_ofld_send(&rhp->rdev, skb);
1149 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1150 qhp->wq.sq.qid, __func__);
1152 PDBG("%s ret %d\n", __func__, ret);
1156 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1158 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1159 memset(&init->u, 0, sizeof init->u);
1161 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1162 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1163 init->u.write.stag_sink = cpu_to_be32(1);
1164 init->u.write.to_sink = cpu_to_be64(1);
1165 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1166 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1167 sizeof(struct fw_ri_immd),
1170 case FW_RI_INIT_P2PTYPE_READ_REQ:
1171 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1172 init->u.read.stag_src = cpu_to_be32(1);
1173 init->u.read.to_src_lo = cpu_to_be32(1);
1174 init->u.read.stag_sink = cpu_to_be32(1);
1175 init->u.read.to_sink_lo = cpu_to_be32(1);
1176 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1181 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1183 struct fw_ri_wr *wqe;
1185 struct sk_buff *skb;
1187 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1190 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1193 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1195 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1196 memset(wqe, 0, sizeof *wqe);
1197 wqe->op_compl = cpu_to_be32(
1198 FW_WR_OP(FW_RI_INIT_WR) |
1200 wqe->flowid_len16 = cpu_to_be32(
1201 FW_WR_FLOWID(qhp->ep->hwtid) |
1202 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1204 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1206 wqe->u.init.type = FW_RI_TYPE_INIT;
1207 wqe->u.init.mpareqbit_p2ptype =
1208 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1209 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1210 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1211 if (qhp->attr.mpa_attr.recv_marker_enabled)
1212 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1213 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1214 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1215 if (qhp->attr.mpa_attr.crc_enabled)
1216 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1218 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1219 FW_RI_QP_RDMA_WRITE_ENABLE |
1220 FW_RI_QP_BIND_ENABLE;
1221 if (!qhp->ibqp.uobject)
1222 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1223 FW_RI_QP_STAG0_ENABLE;
1224 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1225 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1226 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1227 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1228 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1229 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1230 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1231 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1232 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1233 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1234 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1235 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1236 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1237 rhp->rdev.lldi.vr->rq.start);
1238 if (qhp->attr.mpa_attr.initiator)
1239 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1241 ret = c4iw_ofld_send(&rhp->rdev, skb);
1245 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1246 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1248 PDBG("%s ret %d\n", __func__, ret);
1252 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1253 enum c4iw_qp_attr_mask mask,
1254 struct c4iw_qp_attributes *attrs,
1258 struct c4iw_qp_attributes newattr = qhp->attr;
1263 struct c4iw_ep *ep = NULL;
1265 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1266 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1267 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1269 mutex_lock(&qhp->mutex);
1271 /* Process attr changes if in IDLE */
1272 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1273 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1277 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1278 newattr.enable_rdma_read = attrs->enable_rdma_read;
1279 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1280 newattr.enable_rdma_write = attrs->enable_rdma_write;
1281 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1282 newattr.enable_bind = attrs->enable_bind;
1283 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1284 if (attrs->max_ord > c4iw_max_read_depth) {
1288 newattr.max_ord = attrs->max_ord;
1290 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1291 if (attrs->max_ird > c4iw_max_read_depth) {
1295 newattr.max_ird = attrs->max_ird;
1297 qhp->attr = newattr;
1300 if (mask & C4IW_QP_ATTR_SQ_DB) {
1301 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1304 if (mask & C4IW_QP_ATTR_RQ_DB) {
1305 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1309 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1311 if (qhp->attr.state == attrs->next_state)
1314 switch (qhp->attr.state) {
1315 case C4IW_QP_STATE_IDLE:
1316 switch (attrs->next_state) {
1317 case C4IW_QP_STATE_RTS:
1318 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1322 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1326 qhp->attr.mpa_attr = attrs->mpa_attr;
1327 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1328 qhp->ep = qhp->attr.llp_stream_handle;
1329 set_state(qhp, C4IW_QP_STATE_RTS);
1332 * Ref the endpoint here and deref when we
1333 * disassociate the endpoint from the QP. This
1334 * happens in CLOSING->IDLE transition or *->ERROR
1337 c4iw_get_ep(&qhp->ep->com);
1338 ret = rdma_init(rhp, qhp);
1342 case C4IW_QP_STATE_ERROR:
1343 set_state(qhp, C4IW_QP_STATE_ERROR);
1351 case C4IW_QP_STATE_RTS:
1352 switch (attrs->next_state) {
1353 case C4IW_QP_STATE_CLOSING:
1354 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1355 set_state(qhp, C4IW_QP_STATE_CLOSING);
1360 c4iw_get_ep(&qhp->ep->com);
1362 t4_set_wq_in_error(&qhp->wq);
1363 ret = rdma_fini(rhp, qhp, ep);
1367 case C4IW_QP_STATE_TERMINATE:
1368 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1369 qhp->attr.layer_etype = attrs->layer_etype;
1370 qhp->attr.ecode = attrs->ecode;
1371 t4_set_wq_in_error(&qhp->wq);
1377 ret = rdma_fini(rhp, qhp, ep);
1381 c4iw_get_ep(&qhp->ep->com);
1383 case C4IW_QP_STATE_ERROR:
1384 set_state(qhp, C4IW_QP_STATE_ERROR);
1385 t4_set_wq_in_error(&qhp->wq);
1390 c4iw_get_ep(&qhp->ep->com);
1399 case C4IW_QP_STATE_CLOSING:
1404 switch (attrs->next_state) {
1405 case C4IW_QP_STATE_IDLE:
1407 set_state(qhp, C4IW_QP_STATE_IDLE);
1408 qhp->attr.llp_stream_handle = NULL;
1409 c4iw_put_ep(&qhp->ep->com);
1411 wake_up(&qhp->wait);
1413 case C4IW_QP_STATE_ERROR:
1420 case C4IW_QP_STATE_ERROR:
1421 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1425 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1429 set_state(qhp, C4IW_QP_STATE_IDLE);
1431 case C4IW_QP_STATE_TERMINATE:
1439 printk(KERN_ERR "%s in a bad state %d\n",
1440 __func__, qhp->attr.state);
1447 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1450 /* disassociate the LLP connection */
1451 qhp->attr.llp_stream_handle = NULL;
1455 set_state(qhp, C4IW_QP_STATE_ERROR);
1458 wake_up(&qhp->wait);
1462 mutex_unlock(&qhp->mutex);
1465 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1468 * If disconnect is 1, then we need to initiate a disconnect
1469 * on the EP. This can be a normal close (RTS->CLOSING) or
1470 * an abnormal close (RTS/CLOSING->ERROR).
1473 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1475 c4iw_put_ep(&ep->com);
1479 * If free is 1, then we've disassociated the EP from the QP
1480 * and we need to dereference the EP.
1483 c4iw_put_ep(&ep->com);
1484 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1488 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1490 struct c4iw_dev *rhp;
1491 struct c4iw_qp *qhp;
1492 struct c4iw_qp_attributes attrs;
1493 struct c4iw_ucontext *ucontext;
1495 qhp = to_c4iw_qp(ib_qp);
1498 attrs.next_state = C4IW_QP_STATE_ERROR;
1499 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1500 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1502 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1503 wait_event(qhp->wait, !qhp->ep);
1505 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1506 atomic_dec(&qhp->refcnt);
1507 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1509 spin_lock_irq(&rhp->lock);
1510 if (!list_empty(&qhp->db_fc_entry))
1511 list_del_init(&qhp->db_fc_entry);
1512 spin_unlock_irq(&rhp->lock);
1514 ucontext = ib_qp->uobject ?
1515 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1516 destroy_qp(&rhp->rdev, &qhp->wq,
1517 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1519 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1524 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1525 struct ib_udata *udata)
1527 struct c4iw_dev *rhp;
1528 struct c4iw_qp *qhp;
1529 struct c4iw_pd *php;
1530 struct c4iw_cq *schp;
1531 struct c4iw_cq *rchp;
1532 struct c4iw_create_qp_resp uresp;
1533 unsigned int sqsize, rqsize;
1534 struct c4iw_ucontext *ucontext;
1536 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1538 PDBG("%s ib_pd %p\n", __func__, pd);
1540 if (attrs->qp_type != IB_QPT_RC)
1541 return ERR_PTR(-EINVAL);
1543 php = to_c4iw_pd(pd);
1545 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1546 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1548 return ERR_PTR(-EINVAL);
1550 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1551 return ERR_PTR(-EINVAL);
1553 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1554 if (rqsize > T4_MAX_RQ_SIZE)
1555 return ERR_PTR(-E2BIG);
1557 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1558 if (sqsize > T4_MAX_SQ_SIZE)
1559 return ERR_PTR(-E2BIG);
1561 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1563 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1565 return ERR_PTR(-ENOMEM);
1566 qhp->wq.sq.size = sqsize;
1567 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1568 qhp->wq.sq.flush_cidx = -1;
1569 qhp->wq.rq.size = rqsize;
1570 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1573 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1574 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1577 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1578 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1580 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1581 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1585 attrs->cap.max_recv_wr = rqsize - 1;
1586 attrs->cap.max_send_wr = sqsize - 1;
1587 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1590 qhp->attr.pd = php->pdid;
1591 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1592 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1593 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1594 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1595 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1596 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1597 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1598 qhp->attr.state = C4IW_QP_STATE_IDLE;
1599 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1600 qhp->attr.enable_rdma_read = 1;
1601 qhp->attr.enable_rdma_write = 1;
1602 qhp->attr.enable_bind = 1;
1603 qhp->attr.max_ord = 1;
1604 qhp->attr.max_ird = 1;
1605 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1606 spin_lock_init(&qhp->lock);
1607 mutex_init(&qhp->mutex);
1608 init_waitqueue_head(&qhp->wait);
1609 atomic_set(&qhp->refcnt, 1);
1611 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1616 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1621 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1626 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1631 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1636 if (t4_sq_onchip(&qhp->wq.sq)) {
1637 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1642 uresp.flags = C4IW_QPF_ONCHIP;
1645 uresp.qid_mask = rhp->rdev.qpmask;
1646 uresp.sqid = qhp->wq.sq.qid;
1647 uresp.sq_size = qhp->wq.sq.size;
1648 uresp.sq_memsize = qhp->wq.sq.memsize;
1649 uresp.rqid = qhp->wq.rq.qid;
1650 uresp.rq_size = qhp->wq.rq.size;
1651 uresp.rq_memsize = qhp->wq.rq.memsize;
1652 spin_lock(&ucontext->mmap_lock);
1654 uresp.ma_sync_key = ucontext->key;
1655 ucontext->key += PAGE_SIZE;
1657 uresp.ma_sync_key = 0;
1659 uresp.sq_key = ucontext->key;
1660 ucontext->key += PAGE_SIZE;
1661 uresp.rq_key = ucontext->key;
1662 ucontext->key += PAGE_SIZE;
1663 uresp.sq_db_gts_key = ucontext->key;
1664 ucontext->key += PAGE_SIZE;
1665 uresp.rq_db_gts_key = ucontext->key;
1666 ucontext->key += PAGE_SIZE;
1667 spin_unlock(&ucontext->mmap_lock);
1668 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1671 mm1->key = uresp.sq_key;
1672 mm1->addr = qhp->wq.sq.phys_addr;
1673 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1674 insert_mmap(ucontext, mm1);
1675 mm2->key = uresp.rq_key;
1676 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1677 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1678 insert_mmap(ucontext, mm2);
1679 mm3->key = uresp.sq_db_gts_key;
1680 mm3->addr = qhp->wq.sq.udb;
1681 mm3->len = PAGE_SIZE;
1682 insert_mmap(ucontext, mm3);
1683 mm4->key = uresp.rq_db_gts_key;
1684 mm4->addr = qhp->wq.rq.udb;
1685 mm4->len = PAGE_SIZE;
1686 insert_mmap(ucontext, mm4);
1688 mm5->key = uresp.ma_sync_key;
1689 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1690 + A_PCIE_MA_SYNC) & PAGE_MASK;
1691 mm5->len = PAGE_SIZE;
1692 insert_mmap(ucontext, mm5);
1695 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1696 init_timer(&(qhp->timer));
1697 INIT_LIST_HEAD(&qhp->db_fc_entry);
1698 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1699 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1713 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1715 destroy_qp(&rhp->rdev, &qhp->wq,
1716 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1719 return ERR_PTR(ret);
1722 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1723 int attr_mask, struct ib_udata *udata)
1725 struct c4iw_dev *rhp;
1726 struct c4iw_qp *qhp;
1727 enum c4iw_qp_attr_mask mask = 0;
1728 struct c4iw_qp_attributes attrs;
1730 PDBG("%s ib_qp %p\n", __func__, ibqp);
1732 /* iwarp does not support the RTR state */
1733 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1734 attr_mask &= ~IB_QP_STATE;
1736 /* Make sure we still have something left to do */
1740 memset(&attrs, 0, sizeof attrs);
1741 qhp = to_c4iw_qp(ibqp);
1744 attrs.next_state = c4iw_convert_state(attr->qp_state);
1745 attrs.enable_rdma_read = (attr->qp_access_flags &
1746 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1747 attrs.enable_rdma_write = (attr->qp_access_flags &
1748 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1749 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1752 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1753 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1754 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1755 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1756 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1759 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1760 * ringing the queue db when we're in DB_FULL mode.
1762 attrs.sq_db_inc = attr->sq_psn;
1763 attrs.rq_db_inc = attr->rq_psn;
1764 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1765 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1767 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1770 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1772 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1773 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1776 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1777 int attr_mask, struct ib_qp_init_attr *init_attr)
1779 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1781 memset(attr, 0, sizeof *attr);
1782 memset(init_attr, 0, sizeof *init_attr);
1783 attr->qp_state = to_ib_qp_state(qhp->attr.state);