2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include "t4fw_ri_api.h"
39 #define T4_QID_BASE 1024
40 #define T4_MAX_QIDS 256
41 #define T4_MAX_NUM_QP (1<<16)
42 #define T4_MAX_NUM_CQ (1<<15)
43 #define T4_MAX_NUM_PD (1<<15)
44 #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
45 #define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
46 #define T4_MAX_IQ_SIZE (65520 - 1)
47 #define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
48 #define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
49 #define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
50 #define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
51 #define T4_MAX_NUM_STAG (1<<15)
52 #define T4_MAX_MR_SIZE (~0ULL - 1)
53 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
54 #define T4_STAG_UNSET 0xffffffff
56 #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
58 struct t4_status_page {
59 __be32 rsvd1; /* flit 0 - hw owns */
64 u8 qp_err; /* flit 1 - sw owns */
70 #define T4_SQ_NUM_SLOTS 4
71 #define T4_SQ_NUM_BYTES (T4_EQ_SIZE * T4_SQ_NUM_SLOTS)
72 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
73 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
74 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
75 sizeof(struct fw_ri_immd)))
76 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
77 sizeof(struct fw_ri_rdma_write_wr) - \
78 sizeof(struct fw_ri_immd)))
79 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
80 sizeof(struct fw_ri_rdma_write_wr) - \
81 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
82 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
83 sizeof(struct fw_ri_immd)))
84 #define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
86 #define T4_RQ_NUM_SLOTS 2
87 #define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
88 #define T4_MAX_RECV_SGE 4
91 struct fw_ri_res_wr res;
93 struct fw_ri_rdma_write_wr write;
94 struct fw_ri_send_wr send;
95 struct fw_ri_rdma_read_wr read;
96 struct fw_ri_bind_mw_wr bind;
97 struct fw_ri_fr_nsmr_wr fr;
98 struct fw_ri_inv_lstag_wr inv;
99 struct t4_status_page status;
100 __be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
104 struct fw_ri_recv_wr recv;
105 struct t4_status_page status;
106 __be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
109 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
110 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
114 wqe->send.opcode = (u8)opcode;
115 wqe->send.flags = flags;
116 wqe->send.wrid = wrid;
120 wqe->send.len16 = len16;
122 slots_used = DIV_ROUND_UP(len16*16, T4_EQ_SIZE);
123 while (slots_used < T4_SQ_NUM_SLOTS) {
124 wqe->flits[slots_used * T4_EQ_SIZE / sizeof(__be64)] = 0;
129 /* CQE/AE status codes */
130 #define T4_ERR_SUCCESS 0x0
131 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
132 /* STAG is offlimt, being 0, */
133 /* or STAG_key mismatch */
134 #define T4_ERR_PDID 0x2 /* PDID mismatch */
135 #define T4_ERR_QPID 0x3 /* QPID mismatch */
136 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
137 #define T4_ERR_WRAP 0x5 /* Wrap error */
138 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
139 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
140 /* shared memory region */
141 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
142 /* shared memory region */
143 #define T4_ERR_ECC 0x9 /* ECC error detected */
144 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
145 /* reading PSTAG for a MW */
147 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
149 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
150 #define T4_ERR_CRC 0x10 /* CRC error */
151 #define T4_ERR_MARKER 0x11 /* Marker error */
152 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
153 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
154 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
155 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
156 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
157 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
158 #define T4_ERR_MSN 0x18 /* MSN error */
159 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
160 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
162 #define T4_ERR_MSN_GAP 0x1B
163 #define T4_ERR_MSN_RANGE 0x1C
164 #define T4_ERR_IRD_OVERFLOW 0x1D
165 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
167 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
194 /* macros for flit 0 of the cqe */
196 #define S_CQE_QPID 12
197 #define M_CQE_QPID 0xFFFFF
198 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
199 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
201 #define S_CQE_SWCQE 11
202 #define M_CQE_SWCQE 0x1
203 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
204 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
206 #define S_CQE_STATUS 5
207 #define M_CQE_STATUS 0x1F
208 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
209 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
212 #define M_CQE_TYPE 0x1
213 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
214 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
216 #define S_CQE_OPCODE 0
217 #define M_CQE_OPCODE 0xF
218 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
219 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
221 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
222 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
223 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
224 #define SQ_TYPE(x) (CQE_TYPE((x)))
225 #define RQ_TYPE(x) (!CQE_TYPE((x)))
226 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
227 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
229 #define CQE_SEND_OPCODE(x)( \
230 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
231 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
232 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
233 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
235 #define CQE_LEN(x) (be32_to_cpu((x)->len))
237 /* used for RQ completion processing */
238 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
239 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
241 /* used for SQ completion processing */
242 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
244 /* generic accessor macros */
245 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
246 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
248 /* macros for flit 3 of the cqe */
249 #define S_CQE_GENBIT 63
250 #define M_CQE_GENBIT 0x1
251 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
252 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
254 #define S_CQE_OVFBIT 62
255 #define M_CQE_OVFBIT 0x1
256 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
258 #define S_CQE_IQTYPE 60
259 #define M_CQE_IQTYPE 0x3
260 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
262 #define M_CQE_TS 0x0fffffffffffffffULL
263 #define G_CQE_TS(x) ((x) & M_CQE_TS)
265 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
266 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
267 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
282 DECLARE_PCI_UNMAP_ADDR(mapping);
283 struct t4_swsqe *sw_sq;
284 struct t4_swsqe *oldest_read;
299 union t4_recv_wr *queue;
301 DECLARE_PCI_UNMAP_ADDR(mapping);
302 struct t4_swrqe *sw_rq;
320 struct c4iw_rdev *rdev;
323 static inline int t4_rqes_posted(struct t4_wq *wq)
325 return wq->rq.in_use;
328 static inline int t4_rq_empty(struct t4_wq *wq)
330 return wq->rq.in_use == 0;
333 static inline int t4_rq_full(struct t4_wq *wq)
335 return wq->rq.in_use == (wq->rq.size - 1);
338 static inline u32 t4_rq_avail(struct t4_wq *wq)
340 return wq->rq.size - 1 - wq->rq.in_use;
343 static inline void t4_rq_produce(struct t4_wq *wq)
346 if (++wq->rq.pidx == wq->rq.size)
350 static inline void t4_rq_consume(struct t4_wq *wq)
354 if (++wq->rq.cidx == wq->rq.size)
358 static inline int t4_sq_empty(struct t4_wq *wq)
360 return wq->sq.in_use == 0;
363 static inline int t4_sq_full(struct t4_wq *wq)
365 return wq->sq.in_use == (wq->sq.size - 1);
368 static inline u32 t4_sq_avail(struct t4_wq *wq)
370 return wq->sq.size - 1 - wq->sq.in_use;
373 static inline void t4_sq_produce(struct t4_wq *wq)
376 if (++wq->sq.pidx == wq->sq.size)
380 static inline void t4_sq_consume(struct t4_wq *wq)
383 if (++wq->sq.cidx == wq->sq.size)
387 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
389 inc *= T4_SQ_NUM_SLOTS;
391 writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
394 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
396 inc *= T4_RQ_NUM_SLOTS;
398 writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
401 static inline int t4_wq_in_error(struct t4_wq *wq)
403 return wq->sq.queue[wq->sq.size].status.qp_err;
406 static inline void t4_set_wq_in_error(struct t4_wq *wq)
408 wq->sq.queue[wq->sq.size].status.qp_err = 1;
409 wq->rq.queue[wq->rq.size].status.qp_err = 1;
412 static inline void t4_disable_wq_db(struct t4_wq *wq)
414 wq->sq.queue[wq->sq.size].status.db_off = 1;
415 wq->rq.queue[wq->rq.size].status.db_off = 1;
418 static inline void t4_enable_wq_db(struct t4_wq *wq)
420 wq->sq.queue[wq->sq.size].status.db_off = 0;
421 wq->rq.queue[wq->rq.size].status.db_off = 0;
424 static inline int t4_wq_db_enabled(struct t4_wq *wq)
426 return !wq->sq.queue[wq->sq.size].status.db_off;
430 struct t4_cqe *queue;
432 DECLARE_PCI_UNMAP_ADDR(mapping);
433 struct t4_cqe *sw_queue;
435 struct c4iw_rdev *rdev;
440 u16 size; /* including status page */
450 static inline int t4_arm_cq(struct t4_cq *cq, int se)
454 while (cq->cidx_inc > CIDXINC_MASK) {
455 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
456 INGRESSQID(cq->cqid);
457 writel(val, cq->gts);
458 cq->cidx_inc -= CIDXINC_MASK;
460 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
461 INGRESSQID(cq->cqid);
462 writel(val, cq->gts);
467 static inline void t4_swcq_produce(struct t4_cq *cq)
470 if (++cq->sw_pidx == cq->size)
474 static inline void t4_swcq_consume(struct t4_cq *cq)
477 if (++cq->sw_cidx == cq->size)
481 static inline void t4_hwcq_consume(struct t4_cq *cq)
483 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
484 if (++cq->cidx_inc == cq->size)
486 if (++cq->cidx == cq->size) {
492 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
494 return (CQE_GENBIT(cqe) == cq->gen);
497 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
503 prev_cidx = cq->size - 1;
505 prev_cidx = cq->cidx - 1;
507 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
510 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
511 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
512 *cqe = &cq->queue[cq->cidx];
519 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
522 return &cq->sw_queue[cq->sw_cidx];
526 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
532 else if (cq->sw_in_use)
533 *cqe = &cq->sw_queue[cq->sw_cidx];
535 ret = t4_next_hw_cqe(cq, cqe);
539 static inline int t4_cq_in_error(struct t4_cq *cq)
541 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
544 static inline void t4_set_cq_in_error(struct t4_cq *cq)
546 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;