2 * Copyright(c) 2015, 2016 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/firmware.h>
49 #include <linux/mutex.h>
50 #include <linux/module.h>
51 #include <linux/delay.h>
52 #include <linux/crc32.h>
58 * Make it easy to toggle firmware file name and if it gets loaded by
59 * editing the following. This may be something we do while in development
60 * but not necessarily something a user would ever need to use.
62 #define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin"
63 #define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw"
64 #define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw"
65 #define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw"
66 #define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw"
67 #define DEFAULT_PLATFORM_CONFIG_NAME "hfi1_platform.dat"
68 #define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw"
69 #define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw"
70 #define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw"
71 #define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw"
73 static uint fw_8051_load = 1;
74 static uint fw_fabric_serdes_load = 1;
75 static uint fw_pcie_serdes_load = 1;
76 static uint fw_sbus_load = 1;
79 * Access required in platform.c
80 * Maintains state of whether the platform config was fetched via the
83 uint platform_config_load;
85 /* Firmware file names get set in hfi1_firmware_init() based on the above */
86 static char *fw_8051_name;
87 static char *fw_fabric_serdes_name;
88 static char *fw_sbus_name;
89 static char *fw_pcie_serdes_name;
90 static char *platform_config_name;
92 #define SBUS_MAX_POLL_COUNT 100
93 #define SBUS_COUNTER(reg, name) \
94 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \
95 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK)
98 * Firmware security header.
106 u32 date; /* BCD yyyymmdd */
107 u32 size; /* in DWORDs */
108 u32 key_size; /* in DWORDs */
109 u32 modulus_size; /* in DWORDs */
110 u32 exponent_size; /* in DWORDs */
114 /* expected field values */
115 #define CSS_MODULE_TYPE 0x00000006
116 #define CSS_HEADER_LEN 0x000000a1
117 #define CSS_HEADER_VERSION 0x00010000
118 #define CSS_MODULE_VENDOR 0x00008086
122 #define EXPONENT_SIZE 4
124 /* the file itself */
125 struct firmware_file {
126 struct css_header css_header;
127 u8 modulus[KEY_SIZE];
128 u8 exponent[EXPONENT_SIZE];
129 u8 signature[KEY_SIZE];
133 struct augmented_firmware_file {
134 struct css_header css_header;
135 u8 modulus[KEY_SIZE];
136 u8 exponent[EXPONENT_SIZE];
137 u8 signature[KEY_SIZE];
143 /* augmented file size difference */
144 #define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \
145 sizeof(struct firmware_file))
147 struct firmware_details {
148 /* Linux core piece */
149 const struct firmware *fw;
151 struct css_header *css_header;
152 u8 *firmware_ptr; /* pointer to binary data */
153 u32 firmware_len; /* length in bytes */
154 u8 *modulus; /* pointer to the modulus */
155 u8 *exponent; /* pointer to the exponent */
156 u8 *signature; /* pointer to the signature */
157 u8 *r2; /* pointer to r2 */
158 u8 *mu; /* pointer to mu */
159 struct augmented_firmware_file dummy_header;
163 * The mutex protects fw_state, fw_err, and all of the firmware_details
166 static DEFINE_MUTEX(fw_mutex);
174 static enum fw_state fw_state = FW_EMPTY;
176 static struct firmware_details fw_8051;
177 static struct firmware_details fw_fabric;
178 static struct firmware_details fw_pcie;
179 static struct firmware_details fw_sbus;
180 static const struct firmware *platform_config;
182 /* flags for turn_off_spicos() */
183 #define SPICO_SBUS 0x1
184 #define SPICO_FABRIC 0x2
185 #define ENABLE_SPICO_SMASK 0x1
187 /* security block commands */
188 #define RSA_CMD_INIT 0x1
189 #define RSA_CMD_START 0x2
191 /* security block status */
192 #define RSA_STATUS_IDLE 0x0
193 #define RSA_STATUS_ACTIVE 0x1
194 #define RSA_STATUS_DONE 0x2
195 #define RSA_STATUS_FAILED 0x3
197 /* RSA engine timeout, in ms */
198 #define RSA_ENGINE_TIMEOUT 100 /* ms */
200 /* hardware mutex timeout, in ms */
201 #define HM_TIMEOUT 10 /* ms */
203 /* 8051 memory access timeout, in us */
204 #define DC8051_ACCESS_TIMEOUT 100 /* us */
206 /* the number of fabric SerDes on the SBus */
207 #define NUM_FABRIC_SERDES 4
209 /* ASIC_STS_SBUS_RESULT.RESULT_CODE value */
210 #define SBUS_READ_COMPLETE 0x4
212 /* SBus fabric SerDes addresses, one set per HFI */
213 static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = {
214 { 0x01, 0x02, 0x03, 0x04 },
215 { 0x28, 0x29, 0x2a, 0x2b }
218 /* SBus PCIe SerDes addresses, one set per HFI */
219 static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = {
220 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16,
221 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 },
222 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
223 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d }
226 /* SBus PCIe PCS addresses, one set per HFI */
227 const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = {
228 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17,
229 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 },
230 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
231 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e }
234 /* SBus fabric SerDes broadcast addresses, one per HFI */
235 static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 };
236 static const u8 all_fabric_serdes_broadcast = 0xe1;
238 /* SBus PCIe SerDes broadcast addresses, one per HFI */
239 const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 };
240 static const u8 all_pcie_serdes_broadcast = 0xe0;
242 static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
248 QSFP_ATTEN_TABLE_MAX,
249 VARIABLE_SETTINGS_TABLE_MAX
253 static void dispose_one_firmware(struct firmware_details *fdet);
254 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
255 struct firmware_details *fdet);
256 static void dump_fw_version(struct hfi1_devdata *dd);
259 * Read a single 64-bit value from 8051 data memory.
262 * o caller to have already set up data read, no auto increment
263 * o caller to turn off read enable when finished
265 * The address argument is a byte offset. Bits 0:2 in the address are
266 * ignored - i.e. the hardware will always do aligned 8-byte reads as if
267 * the lower bits are zero.
269 * Return 0 on success, -ENXIO on a read error (timeout).
271 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result)
276 /* step 1: set the address, clear enable */
277 reg = (addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
278 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT;
279 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
281 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
282 reg | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK);
284 /* wait until ACCESS_COMPLETED is set */
286 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
287 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
290 if (count > DC8051_ACCESS_TIMEOUT) {
291 dd_dev_err(dd, "timeout reading 8051 data\n");
297 /* gather the data */
298 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA);
304 * Read 8051 data starting at addr, for len bytes. Will read in 8-byte chunks.
305 * Return 0 on success, -errno on error.
307 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result)
313 spin_lock_irqsave(&dd->dc8051_memlock, flags);
315 /* data read set-up, no auto-increment */
316 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
318 for (done = 0; done < len; addr += 8, done += 8, result++) {
319 ret = __read_8051_data(dd, addr, result);
324 /* turn off read enable */
325 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
327 spin_unlock_irqrestore(&dd->dc8051_memlock, flags);
333 * Write data or code to the 8051 code or data RAM.
335 static int write_8051(struct hfi1_devdata *dd, int code, u32 start,
336 const u8 *data, u32 len)
342 /* check alignment */
343 aligned = ((unsigned long)data & 0x7) == 0;
346 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull)
347 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK;
348 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
350 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
351 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
352 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK;
353 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
356 for (offset = 0; offset < len; offset += 8) {
357 int bytes = len - offset;
361 memcpy(®, &data[offset], bytes);
362 } else if (aligned) {
363 reg = *(u64 *)&data[offset];
365 memcpy(®, &data[offset], 8);
367 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
369 /* wait until ACCESS_COMPLETED is set */
371 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
372 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
375 if (count > DC8051_ACCESS_TIMEOUT) {
376 dd_dev_err(dd, "timeout writing 8051 data\n");
383 /* turn off write access, auto increment (also sets to data access) */
384 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
385 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
390 /* return 0 if values match, non-zero and complain otherwise */
391 static int invalid_header(struct hfi1_devdata *dd, const char *what,
392 u32 actual, u32 expected)
394 if (actual == expected)
398 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
399 what, expected, actual);
404 * Verify that the static fields in the CSS header match.
406 static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css)
408 /* verify CSS header fields (most sizes are in DW, so add /4) */
409 if (invalid_header(dd, "module_type", css->module_type,
411 invalid_header(dd, "header_len", css->header_len,
412 (sizeof(struct firmware_file) / 4)) ||
413 invalid_header(dd, "header_version", css->header_version,
414 CSS_HEADER_VERSION) ||
415 invalid_header(dd, "module_vendor", css->module_vendor,
416 CSS_MODULE_VENDOR) ||
417 invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) ||
418 invalid_header(dd, "modulus_size", css->modulus_size,
420 invalid_header(dd, "exponent_size", css->exponent_size,
421 EXPONENT_SIZE / 4)) {
428 * Make sure there are at least some bytes after the prefix.
430 static int payload_check(struct hfi1_devdata *dd, const char *name,
431 long file_size, long prefix_size)
433 /* make sure we have some payload */
434 if (prefix_size >= file_size) {
436 "firmware \"%s\", size %ld, must be larger than %ld bytes\n",
437 name, file_size, prefix_size);
445 * Request the firmware from the system. Extract the pieces and fill in
446 * fdet. If successful, the caller will need to call dispose_one_firmware().
447 * Returns 0 on success, -ERRNO on error.
449 static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
450 struct firmware_details *fdet)
452 struct css_header *css;
455 memset(fdet, 0, sizeof(*fdet));
457 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev);
459 dd_dev_warn(dd, "cannot find firmware \"%s\", err %d\n",
464 /* verify the firmware */
465 if (fdet->fw->size < sizeof(struct css_header)) {
466 dd_dev_err(dd, "firmware \"%s\" is too small\n", name);
470 css = (struct css_header *)fdet->fw->data;
472 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name);
473 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size);
474 hfi1_cdbg(FIRMWARE, "CSS structure:");
475 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type);
476 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)",
477 css->header_len, 4 * css->header_len);
478 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version);
479 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id);
480 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor);
481 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date);
482 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)",
483 css->size, 4 * css->size);
484 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)",
485 css->key_size, 4 * css->key_size);
486 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)",
487 css->modulus_size, 4 * css->modulus_size);
488 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)",
489 css->exponent_size, 4 * css->exponent_size);
490 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes",
491 fdet->fw->size - sizeof(struct firmware_file));
494 * If the file does not have a valid CSS header, fail.
495 * Otherwise, check the CSS size field for an expected size.
496 * The augmented file has r2 and mu inserted after the header
497 * was generated, so there will be a known difference between
498 * the CSS header size and the actual file size. Use this
499 * difference to identify an augmented file.
501 * Note: css->size is in DWORDs, multiply by 4 to get bytes.
503 ret = verify_css_header(dd, css);
505 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name);
506 } else if ((css->size * 4) == fdet->fw->size) {
507 /* non-augmented firmware file */
508 struct firmware_file *ff = (struct firmware_file *)
511 /* make sure there are bytes in the payload */
512 ret = payload_check(dd, name, fdet->fw->size,
513 sizeof(struct firmware_file));
515 fdet->css_header = css;
516 fdet->modulus = ff->modulus;
517 fdet->exponent = ff->exponent;
518 fdet->signature = ff->signature;
519 fdet->r2 = fdet->dummy_header.r2; /* use dummy space */
520 fdet->mu = fdet->dummy_header.mu; /* use dummy space */
521 fdet->firmware_ptr = ff->firmware;
522 fdet->firmware_len = fdet->fw->size -
523 sizeof(struct firmware_file);
525 * Header does not include r2 and mu - generate here.
528 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n");
531 } else if ((css->size * 4) + AUGMENT_SIZE == fdet->fw->size) {
532 /* augmented firmware file */
533 struct augmented_firmware_file *aff =
534 (struct augmented_firmware_file *)fdet->fw->data;
536 /* make sure there are bytes in the payload */
537 ret = payload_check(dd, name, fdet->fw->size,
538 sizeof(struct augmented_firmware_file));
540 fdet->css_header = css;
541 fdet->modulus = aff->modulus;
542 fdet->exponent = aff->exponent;
543 fdet->signature = aff->signature;
546 fdet->firmware_ptr = aff->firmware;
547 fdet->firmware_len = fdet->fw->size -
548 sizeof(struct augmented_firmware_file);
551 /* css->size check failed */
553 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
555 (fdet->fw->size - AUGMENT_SIZE) / 4,
562 /* if returning an error, clean up after ourselves */
564 dispose_one_firmware(fdet);
568 static void dispose_one_firmware(struct firmware_details *fdet)
570 release_firmware(fdet->fw);
571 /* erase all previous information */
572 memset(fdet, 0, sizeof(*fdet));
576 * Obtain the 4 firmwares from the OS. All must be obtained at once or not
577 * at all. If called with the firmware state in FW_TRY, use alternate names.
578 * On exit, this routine will have set the firmware state to one of FW_TRY,
579 * FW_FINAL, or FW_ERR.
581 * Must be holding fw_mutex.
583 static void __obtain_firmware(struct hfi1_devdata *dd)
587 if (fw_state == FW_FINAL) /* nothing more to obtain */
589 if (fw_state == FW_ERR) /* already in error */
592 /* fw_state is FW_EMPTY or FW_TRY */
594 if (fw_state == FW_TRY) {
596 * We tried the original and it failed. Move to the
599 dd_dev_warn(dd, "using alternate firmware names\n");
601 * Let others run. Some systems, when missing firmware, does
602 * something that holds for 30 seconds. If we do that twice
603 * in a row it triggers task blocked warning.
607 dispose_one_firmware(&fw_8051);
608 if (fw_fabric_serdes_load)
609 dispose_one_firmware(&fw_fabric);
611 dispose_one_firmware(&fw_sbus);
612 if (fw_pcie_serdes_load)
613 dispose_one_firmware(&fw_pcie);
614 fw_8051_name = ALT_FW_8051_NAME_ASIC;
615 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME;
616 fw_sbus_name = ALT_FW_SBUS_NAME;
617 fw_pcie_serdes_name = ALT_FW_PCIE_NAME;
621 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus);
626 if (fw_pcie_serdes_load) {
627 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie);
632 if (fw_fabric_serdes_load) {
633 err = obtain_one_firmware(dd, fw_fabric_serdes_name,
640 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051);
647 /* oops, had problems obtaining a firmware */
648 if (fw_state == FW_EMPTY && dd->icode == ICODE_RTL_SILICON) {
649 /* retry with alternate (RTL only) */
653 dd_dev_err(dd, "unable to obtain working firmware\n");
658 if (fw_state == FW_EMPTY &&
659 dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
660 fw_state = FW_TRY; /* may retry later */
662 fw_state = FW_FINAL; /* cannot try again */
667 * Called by all HFIs when loading their firmware - i.e. device probe time.
668 * The first one will do the actual firmware load. Use a mutex to resolve
669 * any possible race condition.
671 * The call to this routine cannot be moved to driver load because the kernel
672 * call request_firmware() requires a device which is only available after
673 * the first device probe.
675 static int obtain_firmware(struct hfi1_devdata *dd)
677 unsigned long timeout;
680 mutex_lock(&fw_mutex);
682 /* 40s delay due to long delay on missing firmware on some systems */
683 timeout = jiffies + msecs_to_jiffies(40000);
684 while (fw_state == FW_TRY) {
686 * Another device is trying the firmware. Wait until it
687 * decides what works (or not).
689 if (time_after(jiffies, timeout)) {
690 /* waited too long */
691 dd_dev_err(dd, "Timeout waiting for firmware try");
696 mutex_unlock(&fw_mutex);
697 msleep(20); /* arbitrary delay */
698 mutex_lock(&fw_mutex);
700 /* not in FW_TRY state */
702 if (fw_state == FW_FINAL) {
703 if (platform_config) {
704 dd->platform_config.data = platform_config->data;
705 dd->platform_config.size = platform_config->size;
707 goto done; /* already acquired */
708 } else if (fw_state == FW_ERR) {
709 goto done; /* already tried and failed */
711 /* fw_state is FW_EMPTY */
713 /* set fw_state to FW_TRY, FW_FINAL, or FW_ERR, and fw_err */
714 __obtain_firmware(dd);
716 if (platform_config_load) {
717 platform_config = NULL;
718 err = request_firmware(&platform_config, platform_config_name,
721 platform_config = NULL;
723 "%s: No default platform config file found\n",
727 dd->platform_config.data = platform_config->data;
728 dd->platform_config.size = platform_config->size;
732 mutex_unlock(&fw_mutex);
738 * Called when the driver unloads. The timing is asymmetric with its
739 * counterpart, obtain_firmware(). If called at device remove time,
740 * then it is conceivable that another device could probe while the
741 * firmware is being disposed. The mutexes can be moved to do that
742 * safely, but then the firmware would be requested from the OS multiple
745 * No mutex is needed as the driver is unloading and there cannot be any
748 void dispose_firmware(void)
750 dispose_one_firmware(&fw_8051);
751 dispose_one_firmware(&fw_fabric);
752 dispose_one_firmware(&fw_pcie);
753 dispose_one_firmware(&fw_sbus);
755 release_firmware(platform_config);
756 platform_config = NULL;
758 /* retain the error state, otherwise revert to empty */
759 if (fw_state != FW_ERR)
764 * Called with the result of a firmware download.
766 * Return 1 to retry loading the firmware, 0 to stop.
768 static int retry_firmware(struct hfi1_devdata *dd, int load_result)
772 mutex_lock(&fw_mutex);
774 if (load_result == 0) {
776 * The load succeeded, so expect all others to do the same.
777 * Do not retry again.
779 if (fw_state == FW_TRY)
781 retry = 0; /* do NOT retry */
782 } else if (fw_state == FW_TRY) {
783 /* load failed, obtain alternate firmware */
784 __obtain_firmware(dd);
785 retry = (fw_state == FW_FINAL);
787 /* else in FW_FINAL or FW_ERR, no retry in either case */
791 mutex_unlock(&fw_mutex);
796 * Write a block of data to a given array CSR. All calls will be in
797 * multiples of 8 bytes.
799 static void write_rsa_data(struct hfi1_devdata *dd, int what,
800 const u8 *data, int nbytes)
802 int qw_size = nbytes / 8;
805 if (((unsigned long)data & 0x7) == 0) {
807 u64 *ptr = (u64 *)data;
809 for (i = 0; i < qw_size; i++, ptr++)
810 write_csr(dd, what + (8 * i), *ptr);
813 for (i = 0; i < qw_size; i++, data += 8) {
816 memcpy(&value, data, 8);
817 write_csr(dd, what + (8 * i), value);
823 * Write a block of data to a given CSR as a stream of writes. All calls will
824 * be in multiples of 8 bytes.
826 static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what,
827 const u8 *data, int nbytes)
829 u64 *ptr = (u64 *)data;
830 int qw_size = nbytes / 8;
832 for (; qw_size > 0; qw_size--, ptr++)
833 write_csr(dd, what, *ptr);
837 * Download the signature and start the RSA mechanism. Wait for
838 * RSA_ENGINE_TIMEOUT before giving up.
840 static int run_rsa(struct hfi1_devdata *dd, const char *who,
843 unsigned long timeout;
848 /* write the signature */
849 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE);
852 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
855 * Make sure the engine is idle and insert a delay between the two
856 * writes to MISC_CFG_RSA_CMD.
858 status = (read_csr(dd, MISC_CFG_FW_CTRL)
859 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
860 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
861 if (status != RSA_STATUS_IDLE) {
862 dd_dev_err(dd, "%s security engine not idle - giving up\n",
868 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
871 * Look for the result.
873 * The RSA engine is hooked up to two MISC errors. The driver
874 * masks these errors as they do not respond to the standard
875 * error "clear down" mechanism. Look for these errors here and
876 * clear them when possible. This routine will exit with the
877 * errors of the current run still set.
879 * MISC_FW_AUTH_FAILED_ERR
880 * Firmware authorization failed. This can be cleared by
881 * re-initializing the RSA engine, then clearing the status bit.
882 * Do not re-init the RSA angine immediately after a successful
883 * run - this will reset the current authorization.
885 * MISC_KEY_MISMATCH_ERR
886 * Key does not match. The only way to clear this is to load
887 * a matching key then clear the status bit. If this error
888 * is raised, it will persist outside of this routine until a
889 * matching key is loaded.
891 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies;
893 status = (read_csr(dd, MISC_CFG_FW_CTRL)
894 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
895 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
897 if (status == RSA_STATUS_IDLE) {
898 /* should not happen */
899 dd_dev_err(dd, "%s firmware security bad idle state\n",
903 } else if (status == RSA_STATUS_DONE) {
904 /* finished successfully */
906 } else if (status == RSA_STATUS_FAILED) {
907 /* finished unsuccessfully */
911 /* else still active */
913 if (time_after(jiffies, timeout)) {
915 * Timed out while active. We can't reset the engine
916 * if it is stuck active, but run through the
917 * error code to see what error bits are set.
919 dd_dev_err(dd, "%s firmware security time out\n", who);
928 * Arrive here on success or failure. Clear all RSA engine
929 * errors. All current errors will stick - the RSA logic is keeping
930 * error high. All previous errors will clear - the RSA logic
931 * is not keeping the error high.
933 write_csr(dd, MISC_ERR_CLEAR,
934 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK |
935 MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
937 * All that is left are the current errors. Print warnings on
938 * authorization failure details, if any. Firmware authorization
939 * can be retried, so these are only warnings.
941 reg = read_csr(dd, MISC_ERR_STATUS);
943 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK)
944 dd_dev_warn(dd, "%s firmware authorization failed\n",
946 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK)
947 dd_dev_warn(dd, "%s firmware key mismatch\n", who);
953 static void load_security_variables(struct hfi1_devdata *dd,
954 struct firmware_details *fdet)
956 /* Security variables a. Write the modulus */
957 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE);
958 /* Security variables b. Write the r2 */
959 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE);
960 /* Security variables c. Write the mu */
961 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE);
962 /* Security variables d. Write the header */
963 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD,
964 (u8 *)fdet->css_header,
965 sizeof(struct css_header));
968 /* return the 8051 firmware state */
969 static inline u32 get_firmware_state(struct hfi1_devdata *dd)
971 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
973 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT)
974 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK;
978 * Wait until the firmware is up and ready to take host requests.
979 * Return 0 on success, -ETIMEDOUT on timeout.
981 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout)
983 unsigned long timeout;
985 /* in the simulator, the fake 8051 is always ready */
986 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
989 timeout = msecs_to_jiffies(mstimeout) + jiffies;
991 if (get_firmware_state(dd) == 0xa0) /* ready */
993 if (time_after(jiffies, timeout)) /* timed out */
995 usleep_range(1950, 2050); /* sleep 2ms-ish */
1000 * Load the 8051 firmware.
1002 static int load_8051_firmware(struct hfi1_devdata *dd,
1003 struct firmware_details *fdet)
1011 * Load DC 8051 firmware
1014 * DC reset step 1: Reset DC8051
1016 reg = DC_DC8051_CFG_RST_M8051W_SMASK
1017 | DC_DC8051_CFG_RST_CRAM_SMASK
1018 | DC_DC8051_CFG_RST_DRAM_SMASK
1019 | DC_DC8051_CFG_RST_IRAM_SMASK
1020 | DC_DC8051_CFG_RST_SFR_SMASK;
1021 write_csr(dd, DC_DC8051_CFG_RST, reg);
1024 * DC reset step 2 (optional): Load 8051 data memory with link
1029 * DC reset step 3: Load DC8051 firmware
1031 /* release all but the core reset */
1032 reg = DC_DC8051_CFG_RST_M8051W_SMASK;
1033 write_csr(dd, DC_DC8051_CFG_RST, reg);
1035 /* Firmware load step 1 */
1036 load_security_variables(dd, fdet);
1039 * Firmware load step 2. Clear MISC_CFG_FW_CTRL.FW_8051_LOADED
1041 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1043 /* Firmware load steps 3-5 */
1044 ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr,
1045 fdet->firmware_len);
1050 * DC reset step 4. Host starts the DC8051 firmware
1053 * Firmware load step 6. Set MISC_CFG_FW_CTRL.FW_8051_LOADED
1055 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
1057 /* Firmware load steps 7-10 */
1058 ret = run_rsa(dd, "8051", fdet->signature);
1062 /* clear all reset bits, releasing the 8051 */
1063 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
1066 * DC reset step 5. Wait for firmware to be ready to accept host
1069 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
1070 if (ret) { /* timed out */
1071 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n",
1072 get_firmware_state(dd));
1076 read_misc_status(dd, &ver_a, &ver_b);
1077 dd_dev_info(dd, "8051 firmware version %d.%d\n",
1078 (int)ver_b, (int)ver_a);
1079 dd->dc8051_ver = dc8051_ver(ver_b, ver_a);
1085 * Write the SBus request register
1087 * No need for masking - the arguments are sized exactly.
1089 void sbus_request(struct hfi1_devdata *dd,
1090 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1092 write_csr(dd, ASIC_CFG_SBUS_REQUEST,
1093 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) |
1094 ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) |
1095 ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) |
1096 ((u64)receiver_addr <<
1097 ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
1101 * Read a value from the SBus.
1103 * Requires the caller to be in fast mode
1105 static u32 sbus_read(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr,
1112 u32 result_code = 0;
1114 sbus_request(dd, receiver_addr, data_addr, READ_SBUS_RECEIVER, data_in);
1116 for (retries = 0; retries < 100; retries++) {
1117 usleep_range(1000, 1200); /* arbitrary */
1118 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1119 result_code = (reg >> ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT)
1120 & ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK;
1121 if (result_code != SBUS_READ_COMPLETE)
1125 result = (reg >> ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT)
1126 & ASIC_STS_SBUS_RESULT_DATA_OUT_MASK;
1131 dd_dev_err(dd, "%s: read failed, result code 0x%x\n", __func__,
1139 * Turn off the SBus and fabric serdes spicos.
1141 * + Must be called with Sbus fast mode turned on.
1142 * + Must be called after fabric serdes broadcast is set up.
1143 * + Must be called before the 8051 is loaded - assumes 8051 is not loaded
1144 * when using MISC_CFG_FW_CTRL.
1146 static void turn_off_spicos(struct hfi1_devdata *dd, int flags)
1148 /* only needed on A0 */
1152 dd_dev_info(dd, "Turning off spicos:%s%s\n",
1153 flags & SPICO_SBUS ? " SBus" : "",
1154 flags & SPICO_FABRIC ? " fabric" : "");
1156 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
1157 /* disable SBus spico */
1158 if (flags & SPICO_SBUS)
1159 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
1160 WRITE_SBUS_RECEIVER, 0x00000040);
1162 /* disable the fabric serdes spicos */
1163 if (flags & SPICO_FABRIC)
1164 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id],
1165 0x07, WRITE_SBUS_RECEIVER, 0x00000000);
1166 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1170 * Reset all of the fabric serdes for this HFI in preparation to take the
1173 * To do a reset, we need to write to to the serdes registers. Unfortunately,
1174 * the fabric serdes download to the other HFI on the ASIC will have turned
1175 * off the firmware validation on this HFI. This means we can't write to the
1176 * registers to reset the serdes. Work around this by performing a complete
1177 * re-download and validation of the fabric serdes firmware. This, as a
1178 * by-product, will reset the serdes. NOTE: the re-download requires that
1179 * the 8051 be in the Offline state. I.e. not actively trying to use the
1180 * serdes. This routine is called at the point where the link is Offline and
1181 * is getting ready to go to Polling.
1183 void fabric_serdes_reset(struct hfi1_devdata *dd)
1187 if (!fw_fabric_serdes_load)
1190 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1193 "Cannot acquire SBus resource to reset fabric SerDes - perhaps you should reboot\n");
1196 set_sbus_fast_mode(dd);
1199 /* A0 serdes do not work with a re-download */
1200 u8 ra = fabric_serdes_broadcast[dd->hfi1_id];
1202 /* place SerDes in reset and disable SPICO */
1203 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1204 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1206 /* remove SerDes reset */
1207 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1208 /* turn SPICO enable on */
1209 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1211 turn_off_spicos(dd, SPICO_FABRIC);
1213 * No need for firmware retry - what to download has already
1215 * No need to pay attention to the load return - the only
1216 * failure is a validation failure, which has already been
1217 * checked by the initial download.
1219 (void)load_fabric_serdes_firmware(dd, &fw_fabric);
1222 clear_sbus_fast_mode(dd);
1223 release_chip_resource(dd, CR_SBUS);
1226 /* Access to the SBus in this routine should probably be serialized */
1227 int sbus_request_slow(struct hfi1_devdata *dd,
1228 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1232 /* make sure fast mode is clear */
1233 clear_sbus_fast_mode(dd);
1235 sbus_request(dd, receiver_addr, data_addr, command, data_in);
1236 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1237 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK);
1238 /* Wait for both DONE and RCV_DATA_VALID to go high */
1239 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1240 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1241 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) {
1242 if (count++ >= SBUS_MAX_POLL_COUNT) {
1243 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1245 * If the loop has timed out, we are OK if DONE bit
1246 * is set and RCV_DATA_VALID and EXECUTE counters
1247 * are the same. If not, we cannot proceed.
1249 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1250 (SBUS_COUNTER(counts, RCV_DATA_VALID) ==
1251 SBUS_COUNTER(counts, EXECUTE)))
1256 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1259 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1260 /* Wait for DONE to clear after EXECUTE is cleared */
1261 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1262 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) {
1263 if (count++ >= SBUS_MAX_POLL_COUNT)
1266 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1271 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
1272 struct firmware_details *fdet)
1275 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; /* receiver addr */
1277 dd_dev_info(dd, "Downloading fabric firmware\n");
1279 /* step 1: load security variables */
1280 load_security_variables(dd, fdet);
1281 /* step 2: place SerDes in reset and disable SPICO */
1282 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1283 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1285 /* step 3: remove SerDes reset */
1286 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1287 /* step 4: assert IMEM override */
1288 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000);
1289 /* step 5: download SerDes machine code */
1290 for (i = 0; i < fdet->firmware_len; i += 4) {
1291 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER,
1292 *(u32 *)&fdet->firmware_ptr[i]);
1294 /* step 6: IMEM override off */
1295 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000);
1296 /* step 7: turn ECC on */
1297 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000);
1299 /* steps 8-11: run the RSA engine */
1300 err = run_rsa(dd, "fabric serdes", fdet->signature);
1304 /* step 12: turn SPICO enable on */
1305 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1306 /* step 13: enable core hardware interrupts */
1307 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000);
1312 static int load_sbus_firmware(struct hfi1_devdata *dd,
1313 struct firmware_details *fdet)
1316 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1318 dd_dev_info(dd, "Downloading SBus firmware\n");
1320 /* step 1: load security variables */
1321 load_security_variables(dd, fdet);
1322 /* step 2: place SPICO into reset and enable off */
1323 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0);
1324 /* step 3: remove reset, enable off, IMEM_CNTRL_EN on */
1325 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240);
1326 /* step 4: set starting IMEM address for burst download */
1327 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000);
1328 /* step 5: download the SBus Master machine code */
1329 for (i = 0; i < fdet->firmware_len; i += 4) {
1330 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER,
1331 *(u32 *)&fdet->firmware_ptr[i]);
1333 /* step 6: set IMEM_CNTL_EN off */
1334 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040);
1335 /* step 7: turn ECC on */
1336 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000);
1338 /* steps 8-11: run the RSA engine */
1339 err = run_rsa(dd, "SBus", fdet->signature);
1343 /* step 12: set SPICO_ENABLE on */
1344 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1349 static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
1350 struct firmware_details *fdet)
1353 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1355 dd_dev_info(dd, "Downloading PCIe firmware\n");
1357 /* step 1: load security variables */
1358 load_security_variables(dd, fdet);
1359 /* step 2: assert single step (halts the SBus Master spico) */
1360 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001);
1361 /* step 3: enable XDMEM access */
1362 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40);
1363 /* step 4: load firmware into SBus Master XDMEM */
1365 * NOTE: the dmem address, write_en, and wdata are all pre-packed,
1366 * we only need to pick up the bytes and write them
1368 for (i = 0; i < fdet->firmware_len; i += 4) {
1369 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
1370 *(u32 *)&fdet->firmware_ptr[i]);
1372 /* step 5: disable XDMEM access */
1373 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1374 /* step 6: allow SBus Spico to run */
1375 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000);
1378 * steps 7-11: run RSA, if it succeeds, firmware is available to
1381 return run_rsa(dd, "PCIe serdes", fdet->signature);
1385 * Set the given broadcast values on the given list of devices.
1387 static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2,
1388 const u8 *addrs, int count)
1390 while (--count >= 0) {
1392 * Set BROADCAST_GROUP_1 and BROADCAST_GROUP_2, leave
1393 * defaults for everything else. Do not read-modify-write,
1394 * per instruction from the manufacturer.
1398 * ----- ---------------------------------
1399 * 0 IGNORE_BROADCAST (default 0)
1400 * 11:4 BROADCAST_GROUP_1 (default 0xff)
1401 * 23:16 BROADCAST_GROUP_2 (default 0xff)
1403 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER,
1404 (u32)bg1 << 4 | (u32)bg2 << 16);
1408 int acquire_hw_mutex(struct hfi1_devdata *dd)
1410 unsigned long timeout;
1412 u8 mask = 1 << dd->hfi1_id;
1416 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies;
1418 write_csr(dd, ASIC_CFG_MUTEX, mask);
1419 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1421 return 0; /* success */
1422 if (time_after(jiffies, timeout))
1423 break; /* timed out */
1429 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
1430 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
1433 /* break mutex and retry */
1434 write_csr(dd, ASIC_CFG_MUTEX, 0);
1442 void release_hw_mutex(struct hfi1_devdata *dd)
1444 write_csr(dd, ASIC_CFG_MUTEX, 0);
1447 /* return the given resource bit(s) as a mask for the given HFI */
1448 static inline u64 resource_mask(u32 hfi1_id, u32 resource)
1450 return ((u64)resource) << (hfi1_id ? CR_DYN_SHIFT : 0);
1453 static void fail_mutex_acquire_message(struct hfi1_devdata *dd,
1457 "%s: hardware mutex stuck - suggest rebooting the machine\n",
1462 * Acquire access to a chip resource.
1464 * Return 0 on success, -EBUSY if resource busy, -EIO if mutex acquire failed.
1466 static int __acquire_chip_resource(struct hfi1_devdata *dd, u32 resource)
1468 u64 scratch0, all_bits, my_bit;
1471 if (resource & CR_DYN_MASK) {
1472 /* a dynamic resource is in use if either HFI has set the bit */
1473 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0 &&
1474 (resource & (CR_I2C1 | CR_I2C2))) {
1475 /* discrete devices must serialize across both chains */
1476 all_bits = resource_mask(0, CR_I2C1 | CR_I2C2) |
1477 resource_mask(1, CR_I2C1 | CR_I2C2);
1479 all_bits = resource_mask(0, resource) |
1480 resource_mask(1, resource);
1482 my_bit = resource_mask(dd->hfi1_id, resource);
1484 /* non-dynamic resources are not split between HFIs */
1485 all_bits = resource;
1489 /* lock against other callers within the driver wanting a resource */
1490 mutex_lock(&dd->asic_data->asic_resource_mutex);
1492 ret = acquire_hw_mutex(dd);
1494 fail_mutex_acquire_message(dd, __func__);
1499 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1500 if (scratch0 & all_bits) {
1503 write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit);
1504 /* force write to be visible to other HFI on another OS */
1505 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1508 release_hw_mutex(dd);
1511 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1516 * Acquire access to a chip resource, wait up to mswait milliseconds for
1517 * the resource to become available.
1519 * Return 0 on success, -EBUSY if busy (even after wait), -EIO if mutex
1522 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait)
1524 unsigned long timeout;
1527 timeout = jiffies + msecs_to_jiffies(mswait);
1529 ret = __acquire_chip_resource(dd, resource);
1532 /* resource is busy, check our timeout */
1533 if (time_after_eq(jiffies, timeout))
1535 usleep_range(80, 120); /* arbitrary delay */
1540 * Release access to a chip resource
1542 void release_chip_resource(struct hfi1_devdata *dd, u32 resource)
1546 /* only dynamic resources should ever be cleared */
1547 if (!(resource & CR_DYN_MASK)) {
1548 dd_dev_err(dd, "%s: invalid resource 0x%x\n", __func__,
1552 bit = resource_mask(dd->hfi1_id, resource);
1554 /* lock against other callers within the driver wanting a resource */
1555 mutex_lock(&dd->asic_data->asic_resource_mutex);
1557 if (acquire_hw_mutex(dd)) {
1558 fail_mutex_acquire_message(dd, __func__);
1562 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1563 if ((scratch0 & bit) != 0) {
1565 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1566 /* force write to be visible to other HFI on another OS */
1567 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1569 dd_dev_warn(dd, "%s: id %d, resource 0x%x: bit not set\n",
1570 __func__, dd->hfi1_id, resource);
1573 release_hw_mutex(dd);
1576 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1580 * Return true if resource is set, false otherwise. Print a warning
1581 * if not set and a function is supplied.
1583 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
1588 if (resource & CR_DYN_MASK)
1589 bit = resource_mask(dd->hfi1_id, resource);
1593 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1594 if ((scratch0 & bit) == 0) {
1597 "%s: id %d, resource 0x%x, not acquired!\n",
1598 func, dd->hfi1_id, resource);
1604 static void clear_chip_resources(struct hfi1_devdata *dd, const char *func)
1608 /* lock against other callers within the driver wanting a resource */
1609 mutex_lock(&dd->asic_data->asic_resource_mutex);
1611 if (acquire_hw_mutex(dd)) {
1612 fail_mutex_acquire_message(dd, func);
1616 /* clear all dynamic access bits for this HFI */
1617 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1618 scratch0 &= ~resource_mask(dd->hfi1_id, CR_DYN_MASK);
1619 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1620 /* force write to be visible to other HFI on another OS */
1621 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1623 release_hw_mutex(dd);
1626 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1629 void init_chip_resources(struct hfi1_devdata *dd)
1631 /* clear any holds left by us */
1632 clear_chip_resources(dd, __func__);
1635 void finish_chip_resources(struct hfi1_devdata *dd)
1637 /* clear any holds left by us */
1638 clear_chip_resources(dd, __func__);
1641 void set_sbus_fast_mode(struct hfi1_devdata *dd)
1643 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1644 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
1647 void clear_sbus_fast_mode(struct hfi1_devdata *dd)
1651 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1652 while (SBUS_COUNTER(reg, EXECUTE) !=
1653 SBUS_COUNTER(reg, RCV_DATA_VALID)) {
1654 if (count++ >= SBUS_MAX_POLL_COUNT)
1657 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1659 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1662 int load_firmware(struct hfi1_devdata *dd)
1666 if (fw_fabric_serdes_load) {
1667 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1671 set_sbus_fast_mode(dd);
1673 set_serdes_broadcast(dd, all_fabric_serdes_broadcast,
1674 fabric_serdes_broadcast[dd->hfi1_id],
1675 fabric_serdes_addrs[dd->hfi1_id],
1677 turn_off_spicos(dd, SPICO_FABRIC);
1679 ret = load_fabric_serdes_firmware(dd, &fw_fabric);
1680 } while (retry_firmware(dd, ret));
1682 clear_sbus_fast_mode(dd);
1683 release_chip_resource(dd, CR_SBUS);
1690 ret = load_8051_firmware(dd, &fw_8051);
1691 } while (retry_firmware(dd, ret));
1696 dump_fw_version(dd);
1700 int hfi1_firmware_init(struct hfi1_devdata *dd)
1702 /* only RTL can use these */
1703 if (dd->icode != ICODE_RTL_SILICON) {
1704 fw_fabric_serdes_load = 0;
1705 fw_pcie_serdes_load = 0;
1709 /* no 8051 or QSFP on simulator */
1710 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
1712 platform_config_load = 0;
1715 if (!fw_8051_name) {
1716 if (dd->icode == ICODE_RTL_SILICON)
1717 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC;
1719 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA;
1721 if (!fw_fabric_serdes_name)
1722 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME;
1724 fw_sbus_name = DEFAULT_FW_SBUS_NAME;
1725 if (!fw_pcie_serdes_name)
1726 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME;
1727 if (!platform_config_name)
1728 platform_config_name = DEFAULT_PLATFORM_CONFIG_NAME;
1730 return obtain_firmware(dd);
1734 * This function is a helper function for parse_platform_config(...) and
1735 * does not check for validity of the platform configuration cache
1736 * (because we know it is invalid as we are building up the cache).
1737 * As such, this should not be called from anywhere other than
1738 * parse_platform_config
1740 static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table)
1742 u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask;
1743 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1749 *(pcfgcache->config_tables[PLATFORM_CONFIG_SYSTEM_TABLE].table_metadata
1750 + SYSTEM_TABLE_META_VERSION);
1752 mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
1753 ver_start = meta_ver_meta & mask;
1755 meta_ver_meta >>= METADATA_TABLE_FIELD_LEN_SHIFT;
1757 mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
1758 ver_len = meta_ver_meta & mask;
1761 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1);
1765 dd, "%s:Please update platform config\n", __func__);
1771 int parse_platform_config(struct hfi1_devdata *dd)
1773 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1775 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0, file_length = 0;
1776 u32 record_idx = 0, table_type = 0, table_length_dwords = 0;
1777 int ret = -EINVAL; /* assume failure */
1780 * For integrated devices that did not fall back to the default file,
1781 * the SI tuning information for active channels is acquired from the
1782 * scratch register bitmap, thus there is no platform config to parse.
1783 * Skip parsing in these situations.
1785 if (is_integrated(dd) && !platform_config_load)
1788 if (!dd->platform_config.data) {
1789 dd_dev_err(dd, "%s: Missing config file\n", __func__);
1792 ptr = (u32 *)dd->platform_config.data;
1796 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) {
1797 dd_dev_err(dd, "%s: Bad config file\n", __func__);
1801 /* Field is file size in DWORDs */
1802 file_length = (*ptr) * 4;
1805 if (file_length > dd->platform_config.size) {
1806 dd_dev_info(dd, "%s:File claims to be larger than read size\n",
1809 } else if (file_length < dd->platform_config.size) {
1811 "%s:File claims to be smaller than read size, continuing\n",
1814 /* exactly equal, perfection */
1817 * In both cases where we proceed, using the self-reported file length
1818 * is the safer option
1820 while (ptr < (u32 *)(dd->platform_config.data + file_length)) {
1822 header2 = *(ptr + 1);
1823 if (header1 != ~header2) {
1824 dd_dev_err(dd, "%s: Failed validation at offset %ld\n",
1825 __func__, (ptr - (u32 *)
1826 dd->platform_config.data));
1831 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1);
1833 table_length_dwords = (*ptr >>
1834 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) &
1835 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1);
1837 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) &
1838 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1);
1840 /* Done with this set of headers */
1845 switch (table_type) {
1846 case PLATFORM_CONFIG_SYSTEM_TABLE:
1847 pcfgcache->config_tables[table_type].num_table =
1849 ret = check_meta_version(dd, ptr);
1853 case PLATFORM_CONFIG_PORT_TABLE:
1854 pcfgcache->config_tables[table_type].num_table =
1857 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1859 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1861 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1863 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1864 pcfgcache->config_tables[table_type].num_table =
1865 table_length_dwords;
1869 "%s: Unknown data table %d, offset %ld\n",
1870 __func__, table_type,
1872 dd->platform_config.data));
1873 goto bail; /* We don't trust this file now */
1875 pcfgcache->config_tables[table_type].table = ptr;
1877 /* metadata table */
1878 switch (table_type) {
1879 case PLATFORM_CONFIG_SYSTEM_TABLE:
1881 case PLATFORM_CONFIG_PORT_TABLE:
1883 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1885 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1887 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1889 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1893 "%s: Unknown meta table %d, offset %ld\n",
1894 __func__, table_type,
1896 (u32 *)dd->platform_config.data));
1897 goto bail; /* We don't trust this file now */
1899 pcfgcache->config_tables[table_type].table_metadata =
1903 /* Calculate and check table crc */
1904 crc = crc32_le(~(u32)0, (unsigned char const *)ptr,
1905 (table_length_dwords * 4));
1908 /* Jump the table */
1909 ptr += table_length_dwords;
1911 dd_dev_err(dd, "%s: Failed CRC check at offset %ld\n",
1913 (u32 *)dd->platform_config.data));
1916 /* Jump the CRC DWORD */
1920 pcfgcache->cache_valid = 1;
1923 memset(pcfgcache, 0, sizeof(struct platform_config_cache));
1927 static void get_integrated_platform_config_field(
1928 struct hfi1_devdata *dd,
1929 enum platform_config_table_type_encoding table_type,
1930 int field_index, u32 *data)
1932 struct hfi1_pportdata *ppd = dd->pport;
1933 u8 *cache = ppd->qsfp_info.cache;
1936 switch (table_type) {
1937 case PLATFORM_CONFIG_SYSTEM_TABLE:
1938 if (field_index == SYSTEM_TABLE_QSFP_POWER_CLASS_MAX)
1939 *data = ppd->max_power_class;
1940 else if (field_index == SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G)
1941 *data = ppd->default_atten;
1943 case PLATFORM_CONFIG_PORT_TABLE:
1944 if (field_index == PORT_TABLE_PORT_TYPE)
1945 *data = ppd->port_type;
1946 else if (field_index == PORT_TABLE_LOCAL_ATTEN_25G)
1947 *data = ppd->local_atten;
1948 else if (field_index == PORT_TABLE_REMOTE_ATTEN_25G)
1949 *data = ppd->remote_atten;
1951 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1952 if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR_APPLY)
1953 *data = (ppd->rx_preset & QSFP_RX_CDR_APPLY_SMASK) >>
1954 QSFP_RX_CDR_APPLY_SHIFT;
1955 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP_APPLY)
1956 *data = (ppd->rx_preset & QSFP_RX_EMP_APPLY_SMASK) >>
1957 QSFP_RX_EMP_APPLY_SHIFT;
1958 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP_APPLY)
1959 *data = (ppd->rx_preset & QSFP_RX_AMP_APPLY_SMASK) >>
1960 QSFP_RX_AMP_APPLY_SHIFT;
1961 else if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR)
1962 *data = (ppd->rx_preset & QSFP_RX_CDR_SMASK) >>
1964 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP)
1965 *data = (ppd->rx_preset & QSFP_RX_EMP_SMASK) >>
1967 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP)
1968 *data = (ppd->rx_preset & QSFP_RX_AMP_SMASK) >>
1971 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1972 if (cache[QSFP_EQ_INFO_OFFS] & 0x4)
1973 tx_preset = ppd->tx_preset_eq;
1975 tx_preset = ppd->tx_preset_noeq;
1976 if (field_index == TX_PRESET_TABLE_PRECUR)
1977 *data = (tx_preset & TX_PRECUR_SMASK) >>
1979 else if (field_index == TX_PRESET_TABLE_ATTN)
1980 *data = (tx_preset & TX_ATTN_SMASK) >>
1982 else if (field_index == TX_PRESET_TABLE_POSTCUR)
1983 *data = (tx_preset & TX_POSTCUR_SMASK) >>
1985 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR_APPLY)
1986 *data = (tx_preset & QSFP_TX_CDR_APPLY_SMASK) >>
1987 QSFP_TX_CDR_APPLY_SHIFT;
1988 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ_APPLY)
1989 *data = (tx_preset & QSFP_TX_EQ_APPLY_SMASK) >>
1990 QSFP_TX_EQ_APPLY_SHIFT;
1991 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR)
1992 *data = (tx_preset & QSFP_TX_CDR_SMASK) >>
1994 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ)
1995 *data = (tx_preset & QSFP_TX_EQ_SMASK) >>
1998 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1999 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
2005 static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
2006 int field, u32 *field_len_bits,
2007 u32 *field_start_bits)
2009 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
2010 u32 *src_ptr = NULL;
2012 if (!pcfgcache->cache_valid)
2016 case PLATFORM_CONFIG_SYSTEM_TABLE:
2018 case PLATFORM_CONFIG_PORT_TABLE:
2020 case PLATFORM_CONFIG_RX_PRESET_TABLE:
2022 case PLATFORM_CONFIG_TX_PRESET_TABLE:
2024 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
2026 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
2027 if (field && field < platform_config_table_limits[table])
2029 pcfgcache->config_tables[table].table_metadata + field;
2032 dd_dev_info(dd, "%s: Unknown table\n", __func__);
2039 if (field_start_bits)
2040 *field_start_bits = *src_ptr &
2041 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
2044 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT)
2045 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
2050 /* This is the central interface to getting data out of the platform config
2051 * file. It depends on parse_platform_config() having populated the
2052 * platform_config_cache in hfi1_devdata, and checks the cache_valid member to
2053 * validate the sanity of the cache.
2055 * The non-obvious parameters:
2056 * @table_index: Acts as a look up key into which instance of the tables the
2057 * relevant field is fetched from.
2059 * This applies to the data tables that have multiple instances. The port table
2060 * is an exception to this rule as each HFI only has one port and thus the
2061 * relevant table can be distinguished by hfi_id.
2063 * @data: pointer to memory that will be populated with the field requested.
2064 * @len: length of memory pointed by @data in bytes.
2066 int get_platform_config_field(struct hfi1_devdata *dd,
2067 enum platform_config_table_type_encoding
2068 table_type, int table_index, int field_index,
2071 int ret = 0, wlen = 0, seek = 0;
2072 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL;
2073 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
2076 memset(data, 0, len);
2080 if (is_integrated(dd) && !platform_config_load) {
2082 * Use saved configuration from ppd for integrated platforms
2084 get_integrated_platform_config_field(dd, table_type,
2089 ret = get_platform_fw_field_metadata(dd, table_type, field_index,
2095 /* Convert length to bits */
2098 /* Our metadata function checked cache_valid and field_index for us */
2099 switch (table_type) {
2100 case PLATFORM_CONFIG_SYSTEM_TABLE:
2101 src_ptr = pcfgcache->config_tables[table_type].table;
2103 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) {
2104 if (len < field_len_bits)
2107 seek = field_start_bits / 8;
2108 wlen = field_len_bits / 8;
2110 src_ptr = (u32 *)((u8 *)src_ptr + seek);
2113 * We expect the field to be byte aligned and whole byte
2114 * lengths if we are here
2116 memcpy(data, src_ptr, wlen);
2120 case PLATFORM_CONFIG_PORT_TABLE:
2121 /* Port table is 4 DWORDS */
2122 src_ptr = dd->hfi1_id ?
2123 pcfgcache->config_tables[table_type].table + 4 :
2124 pcfgcache->config_tables[table_type].table;
2126 case PLATFORM_CONFIG_RX_PRESET_TABLE:
2128 case PLATFORM_CONFIG_TX_PRESET_TABLE:
2130 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
2132 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
2133 src_ptr = pcfgcache->config_tables[table_type].table;
2136 pcfgcache->config_tables[table_type].num_table)
2137 src_ptr += table_index;
2142 dd_dev_info(dd, "%s: Unknown table\n", __func__);
2146 if (!src_ptr || len < field_len_bits)
2149 src_ptr += (field_start_bits / 32);
2150 *data = (*src_ptr >> (field_start_bits % 32)) &
2151 ((1 << field_len_bits) - 1);
2157 * Download the firmware needed for the Gen3 PCIe SerDes. An update
2158 * to the SBus firmware is needed before updating the PCIe firmware.
2160 * Note: caller must be holding the SBus resource.
2162 int load_pcie_firmware(struct hfi1_devdata *dd)
2166 /* both firmware loads below use the SBus */
2167 set_sbus_fast_mode(dd);
2170 turn_off_spicos(dd, SPICO_SBUS);
2172 ret = load_sbus_firmware(dd, &fw_sbus);
2173 } while (retry_firmware(dd, ret));
2178 if (fw_pcie_serdes_load) {
2179 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n");
2180 set_serdes_broadcast(dd, all_pcie_serdes_broadcast,
2181 pcie_serdes_broadcast[dd->hfi1_id],
2182 pcie_serdes_addrs[dd->hfi1_id],
2185 ret = load_pcie_serdes_firmware(dd, &fw_pcie);
2186 } while (retry_firmware(dd, ret));
2192 clear_sbus_fast_mode(dd);
2198 * Read the GUID from the hardware, store it in dd.
2200 void read_guid(struct hfi1_devdata *dd)
2202 /* Take the DC out of reset to get a valid GUID value */
2203 write_csr(dd, CCE_DC_CTRL, 0);
2204 (void)read_csr(dd, CCE_DC_CTRL);
2206 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
2207 dd_dev_info(dd, "GUID %llx",
2208 (unsigned long long)dd->base_guid);
2211 /* read and display firmware version info */
2212 static void dump_fw_version(struct hfi1_devdata *dd)
2214 u32 pcie_vers[NUM_PCIE_SERDES];
2215 u32 fabric_vers[NUM_FABRIC_SERDES];
2222 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
2224 dd_dev_err(dd, "Unable to acquire SBus to read firmware versions\n");
2229 set_sbus_fast_mode(dd);
2231 /* read version for SBus Master */
2232 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x02, WRITE_SBUS_RECEIVER, 0);
2233 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x07, WRITE_SBUS_RECEIVER, 0x1);
2234 /* wait for interrupt to be processed */
2235 usleep_range(10000, 11000);
2236 sbus_vers = sbus_read(dd, SBUS_MASTER_BROADCAST, 0x08, 0x1);
2237 dd_dev_info(dd, "SBus Master firmware version 0x%08x\n", sbus_vers);
2239 /* read version for PCIe SerDes */
2242 for (i = 0; i < NUM_PCIE_SERDES; i++) {
2243 rcv_addr = pcie_serdes_addrs[dd->hfi1_id][i];
2244 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0);
2245 /* wait for interrupt to be processed */
2246 usleep_range(10000, 11000);
2247 pcie_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0);
2248 if (i > 0 && pcie_vers[0] != pcie_vers[i])
2253 dd_dev_info(dd, "PCIe SerDes firmware version 0x%x\n",
2256 dd_dev_warn(dd, "PCIe SerDes do not have the same firmware version\n");
2257 for (i = 0; i < NUM_PCIE_SERDES; i++) {
2259 "PCIe SerDes lane %d firmware version 0x%x\n",
2264 /* read version for fabric SerDes */
2267 for (i = 0; i < NUM_FABRIC_SERDES; i++) {
2268 rcv_addr = fabric_serdes_addrs[dd->hfi1_id][i];
2269 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0);
2270 /* wait for interrupt to be processed */
2271 usleep_range(10000, 11000);
2272 fabric_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0);
2273 if (i > 0 && fabric_vers[0] != fabric_vers[i])
2278 dd_dev_info(dd, "Fabric SerDes firmware version 0x%x\n",
2281 dd_dev_warn(dd, "Fabric SerDes do not have the same firmware version\n");
2282 for (i = 0; i < NUM_FABRIC_SERDES; i++) {
2284 "Fabric SerDes lane %d firmware version 0x%x\n",
2289 clear_sbus_fast_mode(dd);
2290 release_chip_resource(dd, CR_SBUS);