4 * Copyright(c) 2015-2017 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
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23 * modification, are permitted provided that the following conditions
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50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/idr.h>
60 #include <linux/completion.h>
61 #include <linux/kref.h>
62 #include <linux/sched.h>
63 #include <linux/cdev.h>
64 #include <linux/delay.h>
65 #include <linux/kthread.h>
66 #include <linux/i2c.h>
67 #include <linux/i2c-algo-bit.h>
68 #include <rdma/ib_hdrs.h>
69 #include <linux/rhashtable.h>
70 #include <linux/netdevice.h>
71 #include <rdma/rdma_vt.h>
73 #include "chip_registers.h"
83 /* bumped 1 from s/w major version of TrueScale */
84 #define HFI1_CHIP_VERS_MAJ 3U
86 /* don't care about this except printing */
87 #define HFI1_CHIP_VERS_MIN 0U
89 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
90 #define HFI1_OUI 0x001175
91 #define HFI1_OUI_LSB 40
93 #define DROP_PACKET_OFF 0
94 #define DROP_PACKET_ON 1
96 extern unsigned long hfi1_cap_mask;
97 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
98 #define HFI1_CAP_UGET_MASK(mask, cap) \
99 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
100 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
101 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
102 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
103 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
104 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
106 /* Offline Disabled Reason is 4-bits */
107 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
110 * Control context is always 0 and handles the error packets.
111 * It also handles the VL15 and multicast packets.
113 #define HFI1_CTRL_CTXT 0
116 * Driver context will store software counters for each of the events
117 * associated with these status registers
119 #define NUM_CCE_ERR_STATUS_COUNTERS 41
120 #define NUM_RCV_ERR_STATUS_COUNTERS 64
121 #define NUM_MISC_ERR_STATUS_COUNTERS 13
122 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
123 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
124 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
125 #define NUM_SEND_ERR_STATUS_COUNTERS 3
126 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
127 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
130 * per driver stats, either not device nor port-specific, or
131 * summed over all of the devices and ports.
132 * They are described by name via ipathfs filesystem, so layout
133 * and number of elements can change without breaking compatibility.
134 * If members are added or deleted hfi1_statnames[] in debugfs.c must
137 struct hfi1_ib_stats {
138 __u64 sps_ints; /* number of interrupts handled */
139 __u64 sps_errints; /* number of error interrupts */
140 __u64 sps_txerrs; /* tx-related packet errors */
141 __u64 sps_rcverrs; /* non-crc rcv packet errors */
142 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
143 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
144 __u64 sps_ctxts; /* number of contexts currently open */
145 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
150 extern struct hfi1_ib_stats hfi1_stats;
151 extern const struct pci_error_handlers hfi1_pci_err_handler;
154 * First-cut criterion for "device is active" is
155 * two thousand dwords combined Tx, Rx traffic per
156 * 5-second interval. SMA packets are 64 dwords,
157 * and occur "a few per second", presumably each way.
159 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
162 * Below contains all data related to a single context (formerly called port).
165 #ifdef CONFIG_DEBUG_FS
166 struct hfi1_opcode_stats_perctx;
169 struct ctxt_eager_bufs {
170 ssize_t size; /* total size of eager buffers */
171 u32 count; /* size of buffers array */
172 u32 numbufs; /* number of buffers allocated */
173 u32 alloced; /* number of rcvarray entries used */
174 u32 rcvtid_size; /* size of each eager rcv tid */
175 u32 threshold; /* head update threshold */
176 struct eager_buffer {
188 struct list_head list;
192 struct hfi1_ctxtdata {
193 /* shadow the ctxt's RcvCtrl register */
195 /* rcvhdrq base, needs mmap before useful */
197 /* kernel virtual address where hdrqtail is updated */
198 volatile __le64 *rcvhdrtail_kvaddr;
200 * Shared page for kernel to signal user processes that send buffers
201 * need disarming. The process should call HFI1_CMD_DISARM_BUFS
202 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
204 unsigned long *user_event_mask;
205 /* when waiting for rcv or pioavail */
206 wait_queue_head_t wait;
207 /* rcvhdrq size (for freeing) */
209 /* number of rcvhdrq entries */
211 /* size of each of the rcvhdrq entries */
213 /* mmap of hdrq, must fit in 44 bits */
214 dma_addr_t rcvhdrq_dma;
215 dma_addr_t rcvhdrqtailaddr_dma;
216 struct ctxt_eager_bufs egrbufs;
217 /* this receive context's assigned PIO ACK send context */
218 struct send_context *sc;
220 /* dynamic receive available interrupt timeout */
221 u32 rcvavail_timeout;
223 * number of opens (including slave sub-contexts) on this instance
224 * (ignoring forks, dup, etc. for now)
227 /* Device context index */
230 * non-zero if ctxt can be shared, and defines the maximum number of
231 * sub-contexts for this device context.
234 /* non-zero if ctxt is being shared. */
239 /* number of RcvArray groups for this context. */
240 u32 rcv_array_groups;
241 /* index of first eager TID entry. */
243 /* number of expected TID entries */
245 /* index of first expected TID entry. */
248 struct exp_tid_set tid_group_list;
249 struct exp_tid_set tid_used_list;
250 struct exp_tid_set tid_full_list;
252 /* lock protecting all Expected TID data */
253 struct mutex exp_lock;
254 /* number of pio bufs for this ctxt (all procs, if shared) */
256 /* first pio buffer for this ctxt */
258 /* chip offset of PIO buffers for this ctxt */
260 /* per-context configuration flags */
262 /* per-context event flags for fileops/intr communication */
263 unsigned long event_flags;
264 /* WAIT_RCV that timed out, no interrupt */
266 /* WAIT_PIO that timed out, no interrupt */
268 /* WAIT_RCV already happened, no wait */
270 /* WAIT_PIO already happened, no wait */
272 /* total number of polled urgent packets */
274 /* saved total number of polled urgent packets for poll edge trigger */
276 /* same size as task_struct .comm[], command that opened context */
277 char comm[TASK_COMM_LEN];
278 /* so file ops can get at unit */
279 struct hfi1_devdata *dd;
280 /* so functions that need physical port can get it easily */
281 struct hfi1_pportdata *ppd;
282 /* associated msix interrupt */
284 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
285 void *subctxt_uregbase;
286 /* An array of pages for the eager receive buffers * N */
287 void *subctxt_rcvegrbuf;
288 /* An array of pages for the eager header queue entries * N */
289 void *subctxt_rcvhdr_base;
290 /* Bitmask of in use context(s) */
291 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
292 /* The version of the library which opened this ctxt */
294 /* Type of packets or conditions we want to poll for */
296 /* receive packet sequence counter */
299 /* ctxt rcvhdrq head offset */
302 /* QPs waiting for context processing */
303 struct list_head qp_wait_list;
304 /* interrupt handling */
305 u64 imask; /* clear interrupt mask */
306 int ireg; /* clear interrupt register */
307 unsigned numa_id; /* numa node of this context */
308 /* verbs stats per CTX */
309 struct hfi1_opcode_stats_perctx *opstats;
311 * This is the kernel thread that will keep making
312 * progress on the user sdma requests behind the scenes.
313 * There is one per context (shared contexts use the master's).
315 struct task_struct *progress;
316 struct list_head sdma_queues;
317 /* protect sdma queues */
318 spinlock_t sdma_qlock;
320 /* Is ASPM interrupt supported for this context */
321 bool aspm_intr_supported;
322 /* ASPM state (enabled/disabled) for this context */
324 /* Timer for re-enabling ASPM if interrupt activity quietens down */
325 struct timer_list aspm_timer;
326 /* Lock to serialize between intr, timer intr and user threads */
327 spinlock_t aspm_lock;
328 /* Is ASPM processing enabled for this context (in intr context) */
329 bool aspm_intr_enable;
330 /* Last interrupt timestamp */
331 ktime_t aspm_ts_last_intr;
332 /* Last timestamp at which we scheduled a timer for this context */
333 ktime_t aspm_ts_timer_sched;
336 * The interrupt handler for a particular receive context can vary
337 * throughout it's lifetime. This is not a lock protected data member so
338 * it must be updated atomically and the prev and new value must always
339 * be valid. Worst case is we process an extra interrupt and up to 64
340 * packets with the wrong interrupt handler.
342 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
344 /* Indicates that this is vnic context */
347 /* vnic queue index this context is mapped to */
352 * Represents a single packet at a high level. Put commonly computed things in
353 * here so we do not have to keep doing them over and over. The rule of thumb is
354 * if something is used one time to derive some value, store that something in
355 * here. If it is used multiple times, then store the result of that derivation
361 struct hfi1_ctxtdata *rcd;
364 struct ib_other_headers *ohdr;
378 struct rvt_sge_state;
381 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
382 * Mostly for MADs that set or query link parameters, also ipath
385 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
386 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
387 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
388 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
389 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
390 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
391 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
392 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
393 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
394 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
395 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
396 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
397 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
398 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
399 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
400 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
401 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
402 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
403 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
404 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
405 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
408 * HFI or Host Link States
410 * These describe the states the driver thinks the logical and physical
411 * states are in. Used as an argument to set_link_state(). Implemented
412 * as bits for easy multi-state checking. The actual state can only be
415 #define __HLS_UP_INIT_BP 0
416 #define __HLS_UP_ARMED_BP 1
417 #define __HLS_UP_ACTIVE_BP 2
418 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
419 #define __HLS_DN_POLL_BP 4
420 #define __HLS_DN_DISABLE_BP 5
421 #define __HLS_DN_OFFLINE_BP 6
422 #define __HLS_VERIFY_CAP_BP 7
423 #define __HLS_GOING_UP_BP 8
424 #define __HLS_GOING_OFFLINE_BP 9
425 #define __HLS_LINK_COOLDOWN_BP 10
427 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
428 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
429 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
430 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
431 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
432 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
433 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
434 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
435 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
436 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
437 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
439 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
440 #define HLS_DOWN ~(HLS_UP)
442 /* use this MTU size if none other is given */
443 #define HFI1_DEFAULT_ACTIVE_MTU 10240
444 /* use this MTU size as the default maximum */
445 #define HFI1_DEFAULT_MAX_MTU 10240
446 /* default partition key */
447 #define DEFAULT_PKEY 0xffff
450 * Possible fabric manager config parameters for fm_{get,set}_table()
452 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
453 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
454 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
455 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
456 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
457 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
460 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
461 * these are bits so they can be combined, e.g.
462 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
464 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
465 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
466 #define HFI1_RCVCTRL_CTXT_ENB 0x04
467 #define HFI1_RCVCTRL_CTXT_DIS 0x08
468 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
469 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
470 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
471 #define HFI1_RCVCTRL_PKEY_DIS 0x80
472 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
473 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
474 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
475 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
476 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
477 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
478 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
479 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
481 /* partition enforcement flags */
482 #define HFI1_PART_ENFORCE_IN 0x1
483 #define HFI1_PART_ENFORCE_OUT 0x2
485 /* how often we check for synthetic counter wrap around */
486 #define SYNTH_CNT_TIME 3
489 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
490 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
491 #define CNTR_DISABLED 0x2 /* Disable this counter */
492 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
493 #define CNTR_VL 0x8 /* Per VL counter */
494 #define CNTR_SDMA 0x10
495 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
496 #define CNTR_MODE_W 0x0
497 #define CNTR_MODE_R 0x1
499 /* VLs Supported/Operational */
500 #define HFI1_MIN_VLS_SUPPORTED 1
501 #define HFI1_MAX_VLS_SUPPORTED 8
503 #define HFI1_GUIDS_PER_PORT 5
504 #define HFI1_PORT_GUID_INDEX 0
506 static inline void incr_cntr64(u64 *cntr)
508 if (*cntr < (u64)-1LL)
512 static inline void incr_cntr32(u32 *cntr)
514 if (*cntr < (u32)-1LL)
518 #define MAX_NAME_SIZE 64
519 struct hfi1_msix_entry {
521 struct msix_entry msix;
523 char name[MAX_NAME_SIZE];
525 struct irq_affinity_notify notify;
528 /* per-SL CCA information */
530 struct hrtimer hrtimer;
531 struct hfi1_pportdata *ppd; /* read-only */
532 int sl; /* read-only */
533 u16 ccti; /* read/write - current value of CCTI */
536 struct link_down_reason {
538 * SMA-facing value. Should be set from .latest when
539 * HLS_UP_* -> HLS_DN_* transition actually occurs.
551 struct vl_arb_cache {
552 /* protect vl arb cache */
554 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
558 * The structure below encapsulates data relevant to a physical IB Port.
559 * Current chips support only one such port, but the separation
560 * clarifies things a bit. Note that to conform to IB conventions,
561 * port-numbers are one-based. The first or only port is port1.
563 struct hfi1_pportdata {
564 struct hfi1_ibport ibport_data;
566 struct hfi1_devdata *dd;
567 struct kobject pport_cc_kobj;
568 struct kobject sc2vl_kobj;
569 struct kobject sl2sc_kobj;
570 struct kobject vl2mtu_kobj;
573 struct qsfp_data qsfp_info;
574 /* Values for SI tuning of SerDes */
584 /* GUIDs for this interface, in host order, guids[0] is a port guid */
585 u64 guids[HFI1_GUIDS_PER_PORT];
587 /* GUID for peer interface, in host order */
590 /* up or down physical link state */
594 * this address is mapped read-only into user processes so they can
595 * get status cheaply, whenever they want. One qword of status per port
599 /* SendDMA related entries */
601 struct workqueue_struct *hfi1_wq;
603 /* move out of interrupt context */
604 struct work_struct link_vc_work;
605 struct work_struct link_up_work;
606 struct work_struct link_down_work;
607 struct work_struct sma_message_work;
608 struct work_struct freeze_work;
609 struct work_struct link_downgrade_work;
610 struct work_struct link_bounce_work;
611 struct delayed_work start_link_work;
612 /* host link state variables */
613 struct mutex hls_lock;
616 u32 lstate; /* logical link state */
618 /* these are the "32 bit" regs */
620 u32 ibmtu; /* The MTU programmed for this unit */
622 * Current max size IB packet (in bytes) including IB headers, that
623 * we can send. Changes when ibmtu changes.
626 u32 current_egress_rate; /* units [10^6 bits/sec] */
627 /* LID programmed for this instance */
629 /* list of pkeys programmed; 0 if not set */
630 u16 pkeys[MAX_PKEY_VALUES];
631 u16 link_width_supported;
632 u16 link_width_downgrade_supported;
633 u16 link_speed_supported;
634 u16 link_width_enabled;
635 u16 link_width_downgrade_enabled;
636 u16 link_speed_enabled;
637 u16 link_width_active;
638 u16 link_width_downgrade_tx_active;
639 u16 link_width_downgrade_rx_active;
640 u16 link_speed_active;
643 u8 actual_vls_operational;
644 /* LID mask control */
646 /* Rx Polarity inversion (compensate for ~tx on partner) */
649 u8 hw_pidx; /* physical port index */
650 u8 port; /* IB port number and index into dd->pports - 1 */
651 /* type of neighbor node */
654 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
655 u8 neighbor_port_number;
656 u8 is_sm_config_started;
657 u8 offline_disabled_reason;
658 u8 is_active_optimize_enabled;
659 u8 driver_link_ready; /* driver ready for active link */
660 u8 link_enabled; /* link enabled? */
662 u8 local_tx_rate; /* rate given to 8051 firmware */
663 u8 last_pstate; /* info only */
666 /* placeholders for IB MAD packet settings */
667 u8 overrun_threshold;
668 u8 phy_error_threshold;
670 /* Used to override LED behavior for things like maintenance beaconing*/
672 * Alternates per phase of blink
673 * [0] holds LED off duration, [1] holds LED on duration
675 unsigned long led_override_vals[2];
676 u8 led_override_phase; /* LSB picks from vals[] */
677 atomic_t led_override_timer_active;
678 /* Used to flash LEDs in override mode */
679 struct timer_list led_override_timer;
685 * cca_timer_lock protects access to the per-SL cca_timer
686 * structures (specifically the ccti member).
688 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
689 struct cca_timer cca_timer[OPA_MAX_SLS];
691 /* List of congestion control table entries */
692 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
694 /* congestion entries, each entry corresponding to a SL */
695 struct opa_congestion_setting_entry_shadow
696 congestion_entries[OPA_MAX_SLS];
699 * cc_state_lock protects (write) access to the per-port
702 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
704 struct cc_state __rcu *cc_state;
706 /* Total number of congestion control table entries */
709 /* Bit map identifying service level */
710 u32 cc_sl_control_map;
712 /* CA's max number of 64 entry units in the congestion control table */
713 u8 cc_max_table_entries;
716 * begin congestion log related entries
717 * cc_log_lock protects all congestion log related data
719 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
720 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
721 u16 threshold_event_counter;
722 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
723 int cc_log_idx; /* index for logging events */
724 int cc_mad_idx; /* index for reporting events */
725 /* end congestion log related entries */
727 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
729 /* port relative counter buffer */
731 /* port relative synthetic counter buffer */
733 /* port_xmit_discards are synthesized from different egress errors */
734 u64 port_xmit_discards;
735 u64 port_xmit_discards_vl[C_VL_COUNT];
736 u64 port_xmit_constraint_errors;
737 u64 port_rcv_constraint_errors;
738 /* count of 'link_err' interrupts from DC */
740 /* number of times link retrained successfully */
742 /* number of times a link unknown frame was reported */
743 u64 unknown_frame_count;
744 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
745 u16 port_ltp_crc_mode;
746 /* port_crc_mode_enabled is the crc we support */
747 u8 port_crc_mode_enabled;
748 /* mgmt_allowed is also returned in 'portinfo' MADs */
750 u8 part_enforce; /* partition enforcement flags */
751 struct link_down_reason local_link_down_reason;
752 struct link_down_reason neigh_link_down_reason;
753 /* Value to be sent to link peer on LinkDown .*/
754 u8 remote_link_down_reason;
755 /* Error events that will cause a port bounce. */
756 u32 port_error_action;
757 struct work_struct linkstate_active_work;
758 /* Does this port need to prescan for FECNs */
762 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
764 typedef void (*opcode_handler)(struct hfi1_packet *packet);
766 /* return values for the RHF receive functions */
767 #define RHF_RCV_CONTINUE 0 /* keep going */
768 #define RHF_RCV_DONE 1 /* stop, this packet processed */
769 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
771 struct rcv_array_data {
779 struct send_context *sc;
782 /* 16 to directly index */
783 #define PER_VL_SEND_CONTEXTS 16
785 struct err_info_rcvport {
791 struct err_info_constraint {
798 unsigned int curr; /* current temperature */
799 unsigned int lo_lim; /* low temperature limit */
800 unsigned int hi_lim; /* high temperature limit */
801 unsigned int crit_lim; /* critical temperature limit */
802 u8 triggers; /* temperature triggers */
805 struct hfi1_i2c_bus {
806 struct hfi1_devdata *controlling_dd; /* current controlling device */
807 struct i2c_adapter adapter; /* bus details */
808 struct i2c_algo_bit_data algo; /* bus algorithm details */
809 int num; /* bus number, 0 or 1 */
812 /* common data between shared ASIC HFIs */
813 struct hfi1_asic_data {
814 struct hfi1_devdata *dds[2]; /* back pointers */
815 struct mutex asic_resource_mutex;
816 struct hfi1_i2c_bus *i2c_bus0;
817 struct hfi1_i2c_bus *i2c_bus1;
820 /* sizes for both the QP and RSM map tables */
821 #define NUM_MAP_ENTRIES 256
822 #define NUM_MAP_REGS 32
825 * Number of VNIC contexts used. Ensure it is less than or equal to
826 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
828 #define HFI1_NUM_VNIC_CTXT 8
830 /* Number of VNIC RSM entries */
831 #define NUM_VNIC_MAP_ENTRIES 8
833 /* Virtual NIC information */
834 struct hfi1_vnic_data {
835 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
836 struct kmem_cache *txreq_cache;
844 struct hfi1_vnic_vport_info;
846 /* device data struct now contains only "general per-device" info.
847 * fields related to a physical IB port are in a hfi1_pportdata struct.
852 #define BOARD_VERS_MAX 96 /* how long the version string can be */
853 #define SERIAL_MAX 16 /* length of the serial number */
855 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
856 struct hfi1_devdata {
857 struct hfi1_ibdev verbs_dev; /* must be first */
858 struct list_head list;
859 /* pointers to related structs for this device */
860 /* pci access data structure */
861 struct pci_dev *pcidev;
862 struct cdev user_cdev;
863 struct cdev diag_cdev;
865 struct device *user_device;
866 struct device *diag_device;
867 struct device *ui_device;
869 /* mem-mapped pointer to base of chip regs */
870 u8 __iomem *kregbase;
871 /* end of mem-mapped chip space excluding sendbuf and user regs */
873 /* physical address of chip for io_remap, etc. */
874 resource_size_t physaddr;
875 /* Per VL data. Enough for all VLs but not all elements are set/used. */
876 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
877 /* send context data */
878 struct send_context_info *send_contexts;
879 /* map hardware send contexts to software index */
881 /* spinlock for allocating and releasing send context resources */
883 /* lock for pio_map */
884 spinlock_t pio_map_lock;
885 /* Send Context initialization lock. */
886 spinlock_t sc_init_lock;
887 /* lock for sdma_map */
888 spinlock_t sde_map_lock;
889 /* array of kernel send contexts */
890 struct send_context **kernel_send_context;
891 /* array of vl maps */
892 struct pio_vl_map __rcu *pio_map;
893 /* default flags to last descriptor */
896 /* fields common to all SDMA engines */
898 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
899 dma_addr_t sdma_heads_phys;
900 void *sdma_pad_dma; /* DMA'ed by chip */
901 dma_addr_t sdma_pad_phys;
902 /* for deallocation */
903 size_t sdma_heads_size;
904 /* number from the chip */
905 u32 chip_sdma_engines;
908 /* array of engines sized by num_sdma */
909 struct sdma_engine *per_sdma;
910 /* array of vl maps */
911 struct sdma_vl_map __rcu *sdma_map;
912 /* SPC freeze waitqueue and variable */
913 wait_queue_head_t sdma_unfreeze_wq;
914 atomic_t sdma_unfreeze_count;
916 u32 lcb_access_count; /* count of LCB users */
918 /* common data between shared ASIC HFIs in this OS */
919 struct hfi1_asic_data *asic_data;
921 /* mem-mapped pointer to base of PIO buffers */
922 void __iomem *piobase;
924 * write-combining mem-mapped pointer to base of RcvArray
927 void __iomem *rcvarray_wc;
929 * credit return base - a per-NUMA range of DMA address that
930 * the chip will use to update the per-context free counter
932 struct credit_return_base *cr_base;
934 /* send context numbers and sizes for each type */
935 struct sc_config_sizes sc_sizes[SC_MAX];
937 char *boardname; /* human readable board info */
944 u64 __percpu *send_schedule;
945 /* number of receive contexts in use by the driver */
946 u32 num_rcv_contexts;
947 /* number of pio send contexts in use by the driver */
948 u32 num_send_contexts;
950 * number of ctxts available for PSM open
953 /* total number of available user/PSM contexts */
954 u32 num_user_contexts;
955 /* base receive interrupt timeout, in CSR units */
956 u32 rcv_intr_timeout_csr;
958 u32 freezelen; /* max length of freezemsg */
959 u64 __iomem *egrtidbase;
960 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
961 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
962 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
963 spinlock_t uctxt_lock; /* rcd and user context changes */
964 struct mutex dc8051_lock; /* exclusive access to 8051 */
965 struct workqueue_struct *update_cntr_wq;
966 struct work_struct update_cntr_work;
967 /* exclusive access to 8051 memory */
968 spinlock_t dc8051_memlock;
969 int dc8051_timed_out; /* remember if the 8051 timed out */
971 * A page that will hold event notification bitmaps for all
972 * contexts. This page will be mapped into all processes.
974 unsigned long *events;
976 * per unit status, see also portdata statusp
977 * mapped read-only into user processes so they can get unit and
978 * IB link status cheaply
980 struct hfi1_status *status;
982 /* revision register shadow */
984 /* Base GUID for device (network order) */
987 /* these are the "32 bit" regs */
989 /* value we put in kr_rcvhdrsize */
991 /* number of receive contexts the chip supports */
992 u32 chip_rcv_contexts;
993 /* number of receive array entries */
994 u32 chip_rcv_array_count;
995 /* number of PIO send contexts the chip supports */
996 u32 chip_send_contexts;
997 /* number of bytes in the PIO memory buffer */
998 u32 chip_pio_mem_size;
999 /* number of bytes in the SDMA memory buffer */
1000 u32 chip_sdma_mem_size;
1002 /* size of each rcvegrbuffer */
1005 u16 rcvegrbufsize_shift;
1006 /* both sides of the PCIe link are gen3 capable */
1007 u8 link_gen3_capable;
1008 /* default link down value (poll/sleep) */
1010 /* localbus width (1, 2,4,8,16,32) from config space */
1012 /* localbus speed in MHz */
1014 int unit; /* unit # of this chip */
1015 int node; /* home node of this chip */
1017 /* save these PCI fields to restore after a reset */
1030 * ASCII serial number, from flash, large enough for original
1031 * all digit strings, and longer serial number format
1033 u8 serial[SERIAL_MAX];
1034 /* human readable board version */
1035 u8 boardversion[BOARD_VERS_MAX];
1036 u8 lbus_info[32]; /* human readable localbus info */
1037 /* chip major rev, from CceRevision */
1039 /* chip minor rev, from CceRevision */
1043 /* implementation code */
1045 /* vAU of this device */
1047 /* vCU of this device */
1049 /* link credits of this device */
1051 /* initial vl15 credits to use */
1054 /* Misc small ints */
1058 u16 irev; /* implementation revision */
1059 u32 dc8051_ver; /* 8051 firmware version */
1061 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1062 struct platform_config platform_config;
1063 struct platform_config_cache pcfg_cache;
1065 struct diag_client *diag_client;
1067 /* MSI-X information */
1068 struct hfi1_msix_entry *msix_entries;
1069 u32 num_msix_entries;
1070 u32 first_dyn_msix_idx;
1072 /* INTx information */
1073 u32 requested_intx_irq; /* did we request one? */
1074 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1076 /* general interrupt: mask of handled interrupts */
1077 u64 gi_mask[CCE_NUM_INT_CSRS];
1079 struct rcv_array_data rcv_entries;
1081 /* cycle length of PS* counters in HW (in picoseconds) */
1082 u16 psxmitwait_check_rate;
1085 * 64 bit synthetic counters
1087 struct timer_list synth_stats_timer;
1093 size_t cntrnameslen;
1099 * remembered values for synthetic counters
1108 char *portcntrnames;
1109 size_t portcntrnameslen;
1111 struct err_info_rcvport err_info_rcvport;
1112 struct err_info_constraint err_info_rcv_constraint;
1113 struct err_info_constraint err_info_xmit_constraint;
1115 atomic_t drop_packet;
1117 u8 err_info_uncorrectable;
1118 u8 err_info_fmconfig;
1121 * Software counters for the status bits defined by the
1122 * associated error status registers
1124 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1125 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1126 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1127 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1128 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1129 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1130 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1132 /* Software counter that spans all contexts */
1133 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1134 /* Software counter that spans all DMA engines */
1135 u64 sw_send_dma_eng_err_status_cnt[
1136 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1137 /* Software counter that aggregates all cce_err_status errors */
1138 u64 sw_cce_err_status_aggregate;
1139 /* Software counter that aggregates all bypass packet rcv errors */
1140 u64 sw_rcv_bypass_packet_errors;
1141 /* receive interrupt function */
1142 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1144 /* Save the enabled LCB error bits */
1148 * Capability to have different send engines simply by changing a
1151 send_routine process_pio_send ____cacheline_aligned_in_smp;
1152 send_routine process_dma_send;
1153 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1154 u64 pbc, const void *from, size_t count);
1155 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1156 struct hfi1_vnic_vport_info *vinfo,
1157 struct sk_buff *skb, u64 pbc, u8 plen);
1158 /* hfi1_pportdata, points to array of (physical) port-specific
1159 * data structs, indexed by pidx (0..n-1)
1161 struct hfi1_pportdata *pport;
1162 /* receive context data */
1163 struct hfi1_ctxtdata **rcd;
1164 u64 __percpu *int_counter;
1165 /* device (not port) flags, basically device capabilities */
1167 /* Number of physical ports available */
1169 /* Lowest context number which can be used by user processes or VNIC */
1170 u8 first_dyn_alloc_ctxt;
1171 /* adding a new field here would make it part of this cacheline */
1173 /* seqlock for sc2vl */
1174 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1176 /* receive interrupt functions */
1177 rhf_rcv_function_ptr *rhf_rcv_function_map;
1178 u64 __percpu *rcv_limit;
1179 u16 rhf_offset; /* offset of RHF within receive header entry */
1180 /* adding a new field here would make it part of this cacheline */
1182 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1188 /* Timer and counter used to detect RcvBufOvflCnt changes */
1189 struct timer_list rcverr_timer;
1191 wait_queue_head_t event_queue;
1193 /* receive context tail dummy address */
1194 __le64 *rcvhdrtail_dummy_kvaddr;
1195 dma_addr_t rcvhdrtail_dummy_dma;
1198 /* Serialize ASPM enable/disable between multiple verbs contexts */
1199 spinlock_t aspm_lock;
1200 /* Number of verbs contexts which have disabled ASPM */
1201 atomic_t aspm_disabled_cnt;
1202 /* Keeps track of user space clients */
1203 atomic_t user_refcount;
1204 /* Used to wait for outstanding user space clients before dev removal */
1205 struct completion user_comp;
1207 bool eprom_available; /* true if EPROM is available for this device */
1208 bool aspm_supported; /* Does HW support ASPM */
1209 bool aspm_enabled; /* ASPM state: enabled/disabled */
1210 struct rhashtable *sdma_rht;
1212 struct kobject kobj;
1215 struct hfi1_vnic_data vnic;
1218 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1220 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1223 /* 8051 firmware version helper */
1224 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1225 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1226 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1227 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1229 /* f_put_tid types */
1230 #define PT_EXPECTED 0
1232 #define PT_INVALID 2
1236 struct mmu_rb_handler;
1238 /* Private data for file operations */
1239 struct hfi1_filedata {
1240 struct hfi1_devdata *dd;
1241 struct hfi1_ctxtdata *uctxt;
1242 struct hfi1_user_sdma_comp_q *cq;
1243 struct hfi1_user_sdma_pkt_q *pq;
1245 /* for cpu affinity; -1 if none */
1248 struct mmu_rb_handler *handler;
1249 struct tid_rb_node **entry_to_rb;
1250 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1254 u32 invalid_tid_idx;
1255 /* protect invalid_tids array and invalid_tid_idx */
1256 spinlock_t invalid_lock;
1257 struct mm_struct *mm;
1260 extern struct list_head hfi1_dev_list;
1261 extern spinlock_t hfi1_devs_lock;
1262 struct hfi1_devdata *hfi1_lookup(int unit);
1263 extern u32 hfi1_cpulist_count;
1264 extern unsigned long *hfi1_cpulist;
1266 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1267 int hfi1_count_active_units(void);
1269 int hfi1_diag_add(struct hfi1_devdata *dd);
1270 void hfi1_diag_remove(struct hfi1_devdata *dd);
1271 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1273 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1275 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1276 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1277 int hfi1_create_ctxts(struct hfi1_devdata *dd);
1278 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt,
1280 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1281 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1282 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1284 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1285 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1286 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1287 void set_all_slowpath(struct hfi1_devdata *dd);
1288 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd);
1289 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1290 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1292 extern const struct pci_device_id hfi1_pci_tbl[];
1294 /* receive packet handler dispositions */
1295 #define RCV_PKT_OK 0x0 /* keep going */
1296 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1297 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1299 /* calculate the current RHF address */
1300 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1302 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1305 int hfi1_reset_device(int);
1307 /* return the driver's idea of the logical OPA port state */
1308 static inline u32 driver_lstate(struct hfi1_pportdata *ppd)
1311 * The driver does some processing from the time the logical
1312 * link state is at INIT to the time the SM can be notified
1313 * as such. Return IB_PORT_DOWN until the software state
1316 if (ppd->lstate == IB_PORT_INIT && !(ppd->host_link_state & HLS_UP))
1317 return IB_PORT_DOWN;
1322 void receive_interrupt_work(struct work_struct *work);
1324 /* extract service channel from header and rhf */
1325 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1327 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1330 #define HFI1_JKEY_WIDTH 16
1331 #define HFI1_JKEY_MASK (BIT(16) - 1)
1332 #define HFI1_ADMIN_JKEY_RANGE 32
1335 * J_KEYs are split and allocated in the following groups:
1336 * 0 - 31 - users with administrator privileges
1337 * 32 - 63 - kernel protocols using KDETH packets
1338 * 64 - 65535 - all other users using KDETH packets
1340 static inline u16 generate_jkey(kuid_t uid)
1342 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1344 if (capable(CAP_SYS_ADMIN))
1345 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1347 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1353 * active_egress_rate
1355 * returns the active egress rate in units of [10^6 bits/sec]
1357 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1359 u16 link_speed = ppd->link_speed_active;
1360 u16 link_width = ppd->link_width_active;
1363 if (link_speed == OPA_LINK_SPEED_25G)
1364 egress_rate = 25000;
1365 else /* assume OPA_LINK_SPEED_12_5G */
1366 egress_rate = 12500;
1368 switch (link_width) {
1369 case OPA_LINK_WIDTH_4X:
1372 case OPA_LINK_WIDTH_3X:
1375 case OPA_LINK_WIDTH_2X:
1379 /* assume IB_WIDTH_1X */
1389 * Returns the number of 'fabric clock cycles' to egress a packet
1390 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1391 * rate is (approximately) 805 MHz, the units of the returned value
1394 static inline u32 egress_cycles(u32 len, u32 rate)
1401 * (length) [bits] / (rate) [bits/sec]
1402 * ---------------------------------------------------
1403 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1406 cycles = len * 8; /* bits */
1413 void set_link_ipg(struct hfi1_pportdata *ppd);
1414 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn,
1415 u32 rqpn, u8 svc_type);
1416 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1417 u32 pkey, u32 slid, u32 dlid, u8 sc5,
1418 const struct ib_grh *old_grh);
1419 #define PKEY_CHECK_INVALID -1
1420 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1421 u8 sc5, int8_t s_pkey_index);
1423 #define PACKET_EGRESS_TIMEOUT 350
1424 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1426 /* Pause at least 1us, to ensure chip returns all credits */
1427 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1429 udelay(usec ? usec : 1);
1433 * sc_to_vlt() reverse lookup sc to vl
1437 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1442 if (sc5 >= OPA_MAX_SCS)
1446 seq = read_seqbegin(&dd->sc2vl_lock);
1447 rval = *(((u8 *)dd->sc2vl) + sc5);
1448 } while (read_seqretry(&dd->sc2vl_lock, seq));
1453 #define PKEY_MEMBER_MASK 0x8000
1454 #define PKEY_LOW_15_MASK 0x7fff
1457 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1458 * being an entry from the ingress partition key table), return 0
1459 * otherwise. Use the matching criteria for ingress partition keys
1460 * specified in the OPAv1 spec., section 9.10.14.
1462 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1464 u16 mkey = pkey & PKEY_LOW_15_MASK;
1465 u16 ment = ent & PKEY_LOW_15_MASK;
1469 * If pkey[15] is clear (limited partition member),
1470 * is bit 15 in the corresponding table element
1471 * clear (limited member)?
1473 if (!(pkey & PKEY_MEMBER_MASK))
1474 return !!(ent & PKEY_MEMBER_MASK);
1481 * ingress_pkey_table_search - search the entire pkey table for
1482 * an entry which matches 'pkey'. return 0 if a match is found,
1485 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1489 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1490 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1497 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1498 * i.e., increment port_rcv_constraint_errors for the port, and record
1499 * the 'error info' for this failure.
1501 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1504 struct hfi1_devdata *dd = ppd->dd;
1506 incr_cntr64(&ppd->port_rcv_constraint_errors);
1507 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1508 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1509 dd->err_info_rcv_constraint.slid = slid;
1510 dd->err_info_rcv_constraint.pkey = pkey;
1515 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1516 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1517 * is a hint as to the best place in the partition key table to begin
1518 * searching. This function should not be called on the data path because
1519 * of performance reasons. On datapath pkey check is expected to be done
1520 * by HW and rcv_pkey_check function should be called instead.
1522 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1523 u8 sc5, u8 idx, u16 slid)
1525 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1528 /* If SC15, pkey[0:14] must be 0x7fff */
1529 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1532 /* Is the pkey = 0x0, or 0x8000? */
1533 if ((pkey & PKEY_LOW_15_MASK) == 0)
1536 /* The most likely matching pkey has index 'idx' */
1537 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1540 /* no match - try the whole table */
1541 if (!ingress_pkey_table_search(ppd, pkey))
1545 ingress_pkey_table_fail(ppd, pkey, slid);
1550 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1551 * otherwise. It only ensures pkey is vlid for QP0. This function
1552 * should be called on the data path instead of ingress_pkey_check
1553 * as on data path, pkey check is done by HW (except for QP0).
1555 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1558 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1561 /* If SC15, pkey[0:14] must be 0x7fff */
1562 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1567 ingress_pkey_table_fail(ppd, pkey, slid);
1573 /* MTU enumeration, 256-4k match IB */
1575 #define OPA_MTU_256 1
1576 #define OPA_MTU_512 2
1577 #define OPA_MTU_1024 3
1578 #define OPA_MTU_2048 4
1579 #define OPA_MTU_4096 5
1581 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1582 int mtu_to_enum(u32 mtu, int default_if_bad);
1583 u16 enum_to_mtu(int mtu);
1584 static inline int valid_ib_mtu(unsigned int mtu)
1586 return mtu == 256 || mtu == 512 ||
1587 mtu == 1024 || mtu == 2048 ||
1591 static inline int valid_opa_max_mtu(unsigned int mtu)
1593 return mtu >= 2048 &&
1594 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1597 int set_mtu(struct hfi1_pportdata *ppd);
1599 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1600 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1601 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1602 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1604 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1605 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1607 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf);
1608 void reset_link_credits(struct hfi1_devdata *dd);
1609 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1611 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1613 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1618 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1620 return container_of(dev, struct hfi1_devdata, verbs_dev);
1623 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1625 return dd_from_dev(to_idev(ibdev));
1628 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1630 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1633 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1635 return container_of(rdi, struct hfi1_ibdev, rdi);
1638 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1640 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1641 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1643 WARN_ON(pidx >= dd->num_pports);
1644 return &dd->pport[pidx].ibport_data;
1647 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1649 return &rcd->ppd->ibport_data;
1652 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1654 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1657 struct ib_other_headers *ohdr = pkt->ohdr;
1660 bth1 = be32_to_cpu(ohdr->bth[1]);
1661 if (unlikely(bth1 & (IB_BECN_SMASK | IB_FECN_SMASK))) {
1662 hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1663 return !!(bth1 & IB_FECN_SMASK);
1669 * Return the indexed PKEY from the port PKEY table.
1671 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1673 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1676 if (index >= ARRAY_SIZE(ppd->pkeys))
1679 ret = ppd->pkeys[index];
1685 * Return the indexed GUID from the port GUIDs table.
1687 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1689 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1691 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1692 return cpu_to_be64(ppd->guids[index]);
1696 * Called by readers of cc_state only, must call under rcu_read_lock().
1698 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1700 return rcu_dereference(ppd->cc_state);
1704 * Called by writers of cc_state only, must call under cc_state_lock.
1707 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1709 return rcu_dereference_protected(ppd->cc_state,
1710 lockdep_is_held(&ppd->cc_state_lock));
1714 * values for dd->flags (_device_ related flags)
1716 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1717 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1718 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1719 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1720 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1721 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1723 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1724 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1726 /* ctxt_flag bit offsets */
1727 /* waiting for a packet to arrive */
1728 #define HFI1_CTXT_WAITING_RCV 2
1729 /* master has not finished initializing */
1730 #define HFI1_CTXT_BASE_UNINIT 4
1731 /* waiting for an urgent packet to arrive */
1732 #define HFI1_CTXT_WAITING_URG 5
1734 /* free up any allocated data at closes */
1735 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
1736 const struct pci_device_id *ent);
1737 void hfi1_free_devdata(struct hfi1_devdata *dd);
1738 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1740 /* LED beaconing functions */
1741 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1742 unsigned int timeoff);
1743 void shutdown_led_override(struct hfi1_pportdata *ppd);
1745 #define HFI1_CREDIT_RETURN_RATE (100)
1748 * The number of words for the KDETH protocol field. If this is
1749 * larger then the actual field used, then part of the payload
1750 * will be in the header.
1752 * Optimally, we want this sized so that a typical case will
1753 * use full cache lines. The typical local KDETH header would
1764 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1766 #define DEFAULT_RCVHDRSIZE 9
1769 * Maximal header byte count:
1780 * We also want to maintain a cache line alignment to assist DMA'ing
1781 * of the header bytes. Round up to a good size.
1783 #define DEFAULT_RCVHDR_ENTSIZE 32
1785 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1786 u32 nlocked, u32 npages);
1787 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1788 size_t npages, bool writable, struct page **pages);
1789 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1790 size_t npages, bool dirty);
1792 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1794 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1797 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1800 * volatile because it's a DMA target from the chip, routine is
1801 * inlined, and don't want register caching or reordering.
1803 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1810 extern const char ib_hfi1_version[];
1812 int hfi1_device_create(struct hfi1_devdata *dd);
1813 void hfi1_device_remove(struct hfi1_devdata *dd);
1815 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1816 struct kobject *kobj);
1817 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1818 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1819 /* Hook for sysfs read of QSFP */
1820 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1822 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent);
1823 void hfi1_pcie_cleanup(struct pci_dev *pdev);
1824 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
1825 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1826 void hfi1_pcie_flr(struct hfi1_devdata *dd);
1827 int pcie_speeds(struct hfi1_devdata *dd);
1828 void request_msix(struct hfi1_devdata *dd, u32 *nent,
1829 struct hfi1_msix_entry *entry);
1830 void hfi1_enable_intx(struct pci_dev *pdev);
1831 void restore_pci_variables(struct hfi1_devdata *dd);
1832 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1833 int parse_platform_config(struct hfi1_devdata *dd);
1834 int get_platform_config_field(struct hfi1_devdata *dd,
1835 enum platform_config_table_type_encoding
1836 table_type, int table_index, int field_index,
1837 u32 *data, u32 len);
1839 const char *get_unit_name(int unit);
1840 const char *get_card_name(struct rvt_dev_info *rdi);
1841 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
1844 * Flush write combining store buffers (if present) and perform a write
1847 static inline void flush_wc(void)
1849 asm volatile("sfence" : : : "memory");
1852 void handle_eflags(struct hfi1_packet *packet);
1853 int process_receive_ib(struct hfi1_packet *packet);
1854 int process_receive_bypass(struct hfi1_packet *packet);
1855 int process_receive_error(struct hfi1_packet *packet);
1856 int kdeth_process_expected(struct hfi1_packet *packet);
1857 int kdeth_process_eager(struct hfi1_packet *packet);
1858 int process_receive_invalid(struct hfi1_packet *packet);
1860 /* global module parameter variables */
1861 extern unsigned int hfi1_max_mtu;
1862 extern unsigned int hfi1_cu;
1863 extern unsigned int user_credit_return_threshold;
1864 extern int num_user_contexts;
1865 extern unsigned long n_krcvqs;
1866 extern uint krcvqs[];
1867 extern int krcvqsset;
1868 extern uint kdeth_qp;
1869 extern uint loopback;
1870 extern uint quick_linkup;
1871 extern uint rcv_intr_timeout;
1872 extern uint rcv_intr_count;
1873 extern uint rcv_intr_dynamic;
1874 extern ushort link_crc_mask;
1876 extern struct mutex hfi1_mutex;
1878 /* Number of seconds before our card status check... */
1879 #define STATUS_TIMEOUT 60
1881 #define DRIVER_NAME "hfi1"
1882 #define HFI1_USER_MINOR_BASE 0
1883 #define HFI1_TRACE_MINOR 127
1884 #define HFI1_NMINORS 255
1886 #define PCI_VENDOR_ID_INTEL 0x8086
1887 #define PCI_DEVICE_ID_INTEL0 0x24f0
1888 #define PCI_DEVICE_ID_INTEL1 0x24f1
1890 #define HFI1_PKT_USER_SC_INTEGRITY \
1891 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
1892 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
1893 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
1894 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
1896 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
1897 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
1899 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
1902 u64 base_sc_integrity;
1904 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
1905 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
1909 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1910 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1911 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1912 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1913 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1914 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
1915 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1916 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1917 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1918 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
1919 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1920 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1921 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1922 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1923 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1924 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1926 if (ctxt_type == SC_USER)
1927 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
1929 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
1931 /* turn on send-side job key checks if !A0 */
1933 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1935 return base_sc_integrity;
1938 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
1940 u64 base_sdma_integrity;
1942 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
1943 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
1946 base_sdma_integrity =
1947 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1948 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1949 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1950 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1951 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1952 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1953 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1954 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
1955 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1956 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1957 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1958 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1959 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1960 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1962 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
1963 base_sdma_integrity |=
1964 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
1966 /* turn on send-side job key checks if !A0 */
1968 base_sdma_integrity |=
1969 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1971 return base_sdma_integrity;
1975 * hfi1_early_err is used (only!) to print early errors before devdata is
1976 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1977 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
1978 * the same as dd_dev_err, but is used when the message really needs
1979 * the IB port# to be definitive as to what's happening..
1981 #define hfi1_early_err(dev, fmt, ...) \
1982 dev_err(dev, fmt, ##__VA_ARGS__)
1984 #define hfi1_early_info(dev, fmt, ...) \
1985 dev_info(dev, fmt, ##__VA_ARGS__)
1987 #define dd_dev_emerg(dd, fmt, ...) \
1988 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
1989 get_unit_name((dd)->unit), ##__VA_ARGS__)
1990 #define dd_dev_err(dd, fmt, ...) \
1991 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1992 get_unit_name((dd)->unit), ##__VA_ARGS__)
1993 #define dd_dev_warn(dd, fmt, ...) \
1994 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1995 get_unit_name((dd)->unit), ##__VA_ARGS__)
1997 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
1998 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
1999 get_unit_name((dd)->unit), ##__VA_ARGS__)
2001 #define dd_dev_info(dd, fmt, ...) \
2002 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2003 get_unit_name((dd)->unit), ##__VA_ARGS__)
2005 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2006 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2007 get_unit_name((dd)->unit), ##__VA_ARGS__)
2009 #define dd_dev_dbg(dd, fmt, ...) \
2010 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2011 get_unit_name((dd)->unit), ##__VA_ARGS__)
2013 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2014 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2015 get_unit_name((dd)->unit), (port), ##__VA_ARGS__)
2018 * this is used for formatting hw error messages...
2020 struct hfi1_hwerror_msgs {
2027 void hfi1_format_hwerrors(u64 hwerrs,
2028 const struct hfi1_hwerror_msgs *hwerrmsgs,
2029 size_t nhwerrmsgs, char *msg, size_t lmsg);
2031 #define USER_OPCODE_CHECK_VAL 0xC0
2032 #define USER_OPCODE_CHECK_MASK 0xC0
2033 #define OPCODE_CHECK_VAL_DISABLED 0x0
2034 #define OPCODE_CHECK_MASK_DISABLED 0x0
2036 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2038 struct hfi1_pportdata *ppd;
2041 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2042 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2043 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2045 ppd = (struct hfi1_pportdata *)(dd + 1);
2046 for (i = 0; i < dd->num_pports; i++, ppd++) {
2047 ppd->ibport_data.rvp.z_rc_acks =
2048 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2049 ppd->ibport_data.rvp.z_rc_qacks =
2050 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2054 /* Control LED state */
2055 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2058 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2060 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2063 /* return the i2c resource given the target */
2064 static inline u32 i2c_target(u32 target)
2066 return target ? CR_I2C2 : CR_I2C1;
2069 /* return the i2c chain chip resource that this HFI uses for QSFP */
2070 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2072 return i2c_target(dd->hfi1_id);
2075 /* Is this device integrated or discrete? */
2076 static inline bool is_integrated(struct hfi1_devdata *dd)
2078 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2081 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2083 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2084 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2086 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
2087 #define show_packettype(etype) \
2088 __print_symbolic(etype, \
2089 packettype_name(EXPECTED), \
2090 packettype_name(EAGER), \
2091 packettype_name(IB), \
2092 packettype_name(ERROR), \
2093 packettype_name(BYPASS))
2095 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode }
2096 #define show_ib_opcode(opcode) \
2097 __print_symbolic(opcode, \
2098 ib_opcode_name(RC_SEND_FIRST), \
2099 ib_opcode_name(RC_SEND_MIDDLE), \
2100 ib_opcode_name(RC_SEND_LAST), \
2101 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \
2102 ib_opcode_name(RC_SEND_ONLY), \
2103 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \
2104 ib_opcode_name(RC_RDMA_WRITE_FIRST), \
2105 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \
2106 ib_opcode_name(RC_RDMA_WRITE_LAST), \
2107 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2108 ib_opcode_name(RC_RDMA_WRITE_ONLY), \
2109 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2110 ib_opcode_name(RC_RDMA_READ_REQUEST), \
2111 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \
2112 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \
2113 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \
2114 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \
2115 ib_opcode_name(RC_ACKNOWLEDGE), \
2116 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \
2117 ib_opcode_name(RC_COMPARE_SWAP), \
2118 ib_opcode_name(RC_FETCH_ADD), \
2119 ib_opcode_name(UC_SEND_FIRST), \
2120 ib_opcode_name(UC_SEND_MIDDLE), \
2121 ib_opcode_name(UC_SEND_LAST), \
2122 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \
2123 ib_opcode_name(UC_SEND_ONLY), \
2124 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \
2125 ib_opcode_name(UC_RDMA_WRITE_FIRST), \
2126 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \
2127 ib_opcode_name(UC_RDMA_WRITE_LAST), \
2128 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2129 ib_opcode_name(UC_RDMA_WRITE_ONLY), \
2130 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2131 ib_opcode_name(UD_SEND_ONLY), \
2132 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \
2133 ib_opcode_name(CNP))
2134 #endif /* _HFI1_KERNEL_H */