2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include "ipath_kernel.h"
42 #include "ipath_verbs.h"
43 #include "ipath_common.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
47 const char *ipath_get_unit_name(int unit)
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
67 wait_queue_head_t ipath_state_wait;
69 unsigned ipath_debug = __IPATH_INFO;
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
75 MODULE_LICENSE("GPL");
76 MODULE_AUTHOR("QLogic <support@pathscale.com>");
77 MODULE_DESCRIPTION("QLogic InfiniPath driver");
79 const char *ipath_ibcstatus_str[] = {
86 "LState6", /* unused */
87 "LState7", /* unused */
93 "LState0xD", /* unused */
98 static void __devexit ipath_remove_one(struct pci_dev *);
99 static int __devinit ipath_init_one(struct pci_dev *,
100 const struct pci_device_id *);
102 /* Only needed for registration, nothing else needs this info */
103 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
104 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
105 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
107 /* Number of seconds before our card status check... */
108 #define STATUS_TIMEOUT 60
110 static const struct pci_device_id ipath_pci_tbl[] = {
111 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
112 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
116 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
118 static struct pci_driver ipath_driver = {
119 .name = IPATH_DRV_NAME,
120 .probe = ipath_init_one,
121 .remove = __devexit_p(ipath_remove_one),
122 .id_table = ipath_pci_tbl,
125 static void ipath_check_status(struct work_struct *work)
127 struct ipath_devdata *dd = container_of(work, struct ipath_devdata,
131 * If we don't have any interrupts, let the user know and
132 * don't bother checking again.
134 if (dd->ipath_int_counter == 0)
135 dev_err(&dd->pcidev->dev, "No interrupts detected.\n");
138 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
139 u32 *bar0, u32 *bar1)
143 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
145 ipath_dev_err(dd, "failed to read bar0 before enable: "
148 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
150 ipath_dev_err(dd, "failed to read bar1 before enable: "
153 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
156 static void ipath_free_devdata(struct pci_dev *pdev,
157 struct ipath_devdata *dd)
161 pci_set_drvdata(pdev, NULL);
163 if (dd->ipath_unit != -1) {
164 spin_lock_irqsave(&ipath_devs_lock, flags);
165 idr_remove(&unit_table, dd->ipath_unit);
166 list_del(&dd->ipath_list);
167 spin_unlock_irqrestore(&ipath_devs_lock, flags);
172 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
175 struct ipath_devdata *dd;
178 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
179 dd = ERR_PTR(-ENOMEM);
183 dd = vmalloc(sizeof(*dd));
185 dd = ERR_PTR(-ENOMEM);
188 memset(dd, 0, sizeof(*dd));
191 spin_lock_irqsave(&ipath_devs_lock, flags);
193 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
195 printk(KERN_ERR IPATH_DRV_NAME
196 ": Could not allocate unit ID: error %d\n", -ret);
197 ipath_free_devdata(pdev, dd);
203 pci_set_drvdata(pdev, dd);
205 INIT_DELAYED_WORK(&dd->status_work, ipath_check_status);
207 list_add(&dd->ipath_list, &ipath_dev_list);
210 spin_unlock_irqrestore(&ipath_devs_lock, flags);
216 static inline struct ipath_devdata *__ipath_lookup(int unit)
218 return idr_find(&unit_table, unit);
221 struct ipath_devdata *ipath_lookup(int unit)
223 struct ipath_devdata *dd;
226 spin_lock_irqsave(&ipath_devs_lock, flags);
227 dd = __ipath_lookup(unit);
228 spin_unlock_irqrestore(&ipath_devs_lock, flags);
233 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp)
235 int nunits, npresent, nup;
236 struct ipath_devdata *dd;
240 nunits = npresent = nup = maxports = 0;
242 spin_lock_irqsave(&ipath_devs_lock, flags);
244 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
246 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
249 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
252 if (dd->ipath_cfgports > maxports)
253 maxports = dd->ipath_cfgports;
256 spin_unlock_irqrestore(&ipath_devs_lock, flags);
259 *npresentp = npresent;
263 *maxportsp = maxports;
269 * These next two routines are placeholders in case we don't have per-arch
270 * code for controlling write combining. If explicit control of write
271 * combining is not available, performance will probably be awful.
274 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
279 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
283 static int __devinit ipath_init_one(struct pci_dev *pdev,
284 const struct pci_device_id *ent)
287 struct ipath_devdata *dd;
288 unsigned long long addr;
289 u32 bar0 = 0, bar1 = 0;
292 dd = ipath_alloc_devdata(pdev);
295 printk(KERN_ERR IPATH_DRV_NAME
296 ": Could not allocate devdata: error %d\n", -ret);
300 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
302 read_bars(dd, pdev, &bar0, &bar1);
304 ret = pci_enable_device(pdev);
306 /* This can happen iff:
308 * We did a chip reset, and then failed to reprogram the
309 * BAR, or the chip reset due to an internal error. We then
310 * unloaded the driver and reloaded it.
312 * Both reset cases set the BAR back to initial state. For
313 * the latter case, the AER sticky error bit at offset 0x718
314 * should be set, but the Linux kernel doesn't yet know
315 * about that, it appears. If the original BAR was retained
316 * in the kernel data structures, this may be OK.
318 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
319 dd->ipath_unit, -ret);
322 addr = pci_resource_start(pdev, 0);
323 len = pci_resource_len(pdev, 0);
324 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x "
325 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
326 ent->device, ent->driver_data);
328 read_bars(dd, pdev, &bar0, &bar1);
330 if (!bar1 && !(bar0 & ~0xf)) {
332 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
333 "rewriting as %llx\n", addr);
334 ret = pci_write_config_dword(
335 pdev, PCI_BASE_ADDRESS_0, addr);
337 ipath_dev_err(dd, "rewrite of BAR0 "
338 "failed: err %d\n", -ret);
341 ret = pci_write_config_dword(
342 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
344 ipath_dev_err(dd, "rewrite of BAR1 "
345 "failed: err %d\n", -ret);
349 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
350 "not usable until reboot\n");
356 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
358 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
359 "err %d\n", dd->ipath_unit, -ret);
363 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
366 * if the 64 bit setup fails, try 32 bit. Some systems
367 * do not setup 64 bit maps on systems with 2GB or less
370 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
373 "Unable to set DMA mask for unit %u: %d\n",
374 dd->ipath_unit, ret);
378 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
379 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
382 "Unable to set DMA consistent mask "
384 dd->ipath_unit, ret);
389 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
392 "Unable to set DMA consistent mask "
394 dd->ipath_unit, ret);
397 pci_set_master(pdev);
400 * Save BARs to rewrite after device reset. Save all 64 bits of
403 dd->ipath_pcibar0 = addr;
404 dd->ipath_pcibar1 = addr >> 32;
405 dd->ipath_deviceid = ent->device; /* save for later use */
406 dd->ipath_vendorid = ent->vendor;
408 /* setup the chip-specific functions, as early as possible. */
409 switch (ent->device) {
410 case PCI_DEVICE_ID_INFINIPATH_HT:
412 ipath_init_iba6110_funcs(dd);
415 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
416 "CONFIG_HT_IRQ is not enabled\n", ent->device);
419 case PCI_DEVICE_ID_INFINIPATH_PE800:
420 #ifdef CONFIG_PCI_MSI
421 ipath_init_iba6120_funcs(dd);
424 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
425 "CONFIG_PCI_MSI is not enabled\n", ent->device);
429 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
430 "failing\n", ent->device);
434 for (j = 0; j < 6; j++) {
435 if (!pdev->resource[j].start)
437 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
438 j, (unsigned long long)pdev->resource[j].start,
439 (unsigned long long)pdev->resource[j].end,
440 (unsigned long long)pci_resource_len(pdev, j));
444 ipath_dev_err(dd, "No valid address in BAR 0!\n");
449 dd->ipath_deviceid = ent->device; /* save for later use */
450 dd->ipath_vendorid = ent->vendor;
452 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
454 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
455 "%u: err %d\n", dd->ipath_unit, -ret);
456 goto bail_regions; /* shouldn't ever happen */
458 dd->ipath_pcirev = rev;
460 #if defined(__powerpc__)
461 /* There isn't a generic way to specify writethrough mappings */
462 dd->ipath_kregbase = __ioremap(addr, len,
463 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
465 dd->ipath_kregbase = ioremap_nocache(addr, len);
468 if (!dd->ipath_kregbase) {
469 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
474 dd->ipath_kregend = (u64 __iomem *)
475 ((void __iomem *)dd->ipath_kregbase + len);
476 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
478 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
479 addr, dd->ipath_kregbase);
482 * clear ipath_flags here instead of in ipath_init_chip as it is set
483 * by ipath_setup_htconfig.
486 dd->ipath_lli_counter = 0;
487 dd->ipath_lli_errors = 0;
489 if (dd->ipath_f_bus(dd, pdev))
490 ipath_dev_err(dd, "Failed to setup config space; "
491 "continuing anyway\n");
494 * set up our interrupt handler; IRQF_SHARED probably not needed,
495 * since MSI interrupts shouldn't be shared but won't hurt for now.
496 * check 0 irq after we return from chip-specific bus setup, since
497 * that can affect this due to setup
500 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
503 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
506 ipath_dev_err(dd, "Couldn't setup irq handler, "
507 "irq=%d: %d\n", dd->ipath_irq, ret);
512 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
516 ret = ipath_enable_wc(dd);
519 ipath_dev_err(dd, "Write combining not enabled "
520 "(err %d): performance may be poor\n",
525 ipath_device_create_group(&pdev->dev, dd);
526 ipathfs_add_device(dd);
529 ipath_register_ib_device(dd);
531 /* Check that card status in STATUS_TIMEOUT seconds. */
532 schedule_delayed_work(&dd->status_work, HZ * STATUS_TIMEOUT);
537 if (pdev->irq) free_irq(pdev->irq, dd);
540 iounmap((volatile void __iomem *) dd->ipath_kregbase);
543 pci_release_regions(pdev);
546 pci_disable_device(pdev);
549 ipath_free_devdata(pdev, dd);
555 static void __devexit cleanup_device(struct ipath_devdata *dd)
559 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
560 /* can't do anything more with chip; needs re-init */
561 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
562 if (dd->ipath_kregbase) {
564 * if we haven't already cleaned up before these are
565 * to ensure any register reads/writes "fail" until
568 dd->ipath_kregbase = NULL;
569 dd->ipath_uregbase = 0;
570 dd->ipath_sregbase = 0;
571 dd->ipath_cregbase = 0;
572 dd->ipath_kregsize = 0;
574 ipath_disable_wc(dd);
577 if (dd->ipath_pioavailregs_dma) {
578 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
579 (void *) dd->ipath_pioavailregs_dma,
580 dd->ipath_pioavailregs_phys);
581 dd->ipath_pioavailregs_dma = NULL;
583 if (dd->ipath_dummy_hdrq) {
584 dma_free_coherent(&dd->pcidev->dev,
585 dd->ipath_pd[0]->port_rcvhdrq_size,
586 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
587 dd->ipath_dummy_hdrq = NULL;
590 if (dd->ipath_pageshadow) {
591 struct page **tmpp = dd->ipath_pageshadow;
592 dma_addr_t *tmpd = dd->ipath_physshadow;
595 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
597 for (port = 0; port < dd->ipath_cfgports; port++) {
598 int port_tidbase = port * dd->ipath_rcvtidcnt;
599 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
600 for (i = port_tidbase; i < maxtid; i++) {
603 pci_unmap_page(dd->pcidev, tmpd[i],
604 PAGE_SIZE, PCI_DMA_FROMDEVICE);
605 ipath_release_user_pages(&tmpp[i], 1);
611 ipath_stats.sps_pageunlocks += cnt;
612 ipath_cdbg(VERBOSE, "There were still %u expTID "
613 "entries locked\n", cnt);
615 if (ipath_stats.sps_pagelocks ||
616 ipath_stats.sps_pageunlocks)
617 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
618 "unlocked via ipath_m{un}lock\n",
620 ipath_stats.sps_pagelocks,
622 ipath_stats.sps_pageunlocks);
624 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
625 dd->ipath_pageshadow);
626 tmpp = dd->ipath_pageshadow;
627 dd->ipath_pageshadow = NULL;
632 * free any resources still in use (usually just kernel ports)
633 * at unload; we do for portcnt, not cfgports, because cfgports
634 * could have changed while we were loaded.
636 for (port = 0; port < dd->ipath_portcnt; port++) {
637 struct ipath_portdata *pd = dd->ipath_pd[port];
638 dd->ipath_pd[port] = NULL;
639 ipath_free_pddata(dd, pd);
643 * debuggability, in case some cleanup path tries to use it
649 static void __devexit ipath_remove_one(struct pci_dev *pdev)
651 struct ipath_devdata *dd = pci_get_drvdata(pdev);
653 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
656 * disable the IB link early, to be sure no new packets arrive, which
657 * complicates the shutdown process
659 ipath_shutdown_device(dd);
661 cancel_delayed_work(&dd->status_work);
662 flush_scheduled_work();
665 ipath_unregister_ib_device(dd->verbs_dev);
667 ipath_diag_remove(dd);
668 ipath_user_remove(dd);
669 ipathfs_remove_device(dd);
670 ipath_device_remove_group(&pdev->dev, dd);
672 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
673 "unit %u\n", dd, (u32) dd->ipath_unit);
678 * turn off rcv, send, and interrupts for all ports, all drivers
679 * should also hard reset the chip here?
680 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
681 * for all versions of the driver, if they were allocated
684 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
685 dd->ipath_unit, dd->ipath_irq);
686 dd->ipath_f_free_irq(dd);
688 ipath_dbg("irq is 0, not doing free_irq "
689 "for unit %u\n", dd->ipath_unit);
691 * we check for NULL here, because it's outside
692 * the kregbase check, and we need to call it
693 * after the free_irq. Thus it's possible that
694 * the function pointers were never initialized.
696 if (dd->ipath_f_cleanup)
697 /* clean up chip-specific stuff */
698 dd->ipath_f_cleanup(dd);
700 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
701 iounmap((volatile void __iomem *) dd->ipath_kregbase);
702 pci_release_regions(pdev);
703 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
704 pci_disable_device(pdev);
706 ipath_free_devdata(pdev, dd);
709 /* general driver use */
710 DEFINE_MUTEX(ipath_mutex);
712 static DEFINE_SPINLOCK(ipath_pioavail_lock);
715 * ipath_disarm_piobufs - cancel a range of PIO buffers
716 * @dd: the infinipath device
717 * @first: the first PIO buffer to cancel
718 * @cnt: the number of PIO buffers to cancel
720 * cancel a range of PIO buffers, used when they might be armed, but
721 * not triggered. Used at init to ensure buffer state, and also user
722 * process close, in case it died while writing to a PIO buffer
725 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
728 unsigned i, last = first + cnt;
729 u64 sendctrl, sendorig;
731 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
732 sendorig = dd->ipath_sendctrl;
733 for (i = first; i < last; i++) {
734 sendctrl = sendorig | INFINIPATH_S_DISARM |
735 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT);
736 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
741 * Write it again with current value, in case ipath_sendctrl changed
742 * while we were looping; no critical bits that would require
745 * disable PIOAVAILUPD, then re-enable, reading scratch in
746 * between. This seems to avoid a chip timing race that causes
747 * pioavail updates to memory to stop.
749 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
750 sendorig & ~IPATH_S_PIOBUFAVAILUPD);
751 sendorig = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
752 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
757 * ipath_wait_linkstate - wait for an IB link state change to occur
758 * @dd: the infinipath device
759 * @state: the state to wait for
760 * @msecs: the number of milliseconds to wait
762 * wait up to msecs milliseconds for IB link state change to occur for
763 * now, take the easy polling route. Currently used only by
764 * ipath_set_linkstate. Returns 0 if state reached, otherwise
765 * -ETIMEDOUT state can have multiple states set, for any of several
768 static int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state,
771 dd->ipath_state_wanted = state;
772 wait_event_interruptible_timeout(ipath_state_wait,
773 (dd->ipath_flags & state),
774 msecs_to_jiffies(msecs));
775 dd->ipath_state_wanted = 0;
777 if (!(dd->ipath_flags & state)) {
779 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
781 /* test INIT ahead of DOWN, both can be set */
782 (state & IPATH_LINKINIT) ? "INIT" :
783 ((state & IPATH_LINKDOWN) ? "DOWN" :
784 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
786 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
787 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
788 (unsigned long long) ipath_read_kreg64(
789 dd, dd->ipath_kregs->kr_ibcctrl),
790 (unsigned long long) val,
791 ipath_ibcstatus_str[val & 0xf]);
793 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
797 * Decode the error status into strings, deciding whether to always
798 * print * it or not depending on "normal packet errors" vs everything
799 * else. Return 1 if "real" errors, otherwise 0 if only packet
800 * errors, so caller can decide what to print with the string.
802 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
806 if (err & INFINIPATH_E_PKTERRS) {
807 if (!(err & ~INFINIPATH_E_PKTERRS))
808 iserr = 0; // if only packet errors.
809 if (ipath_debug & __IPATH_ERRPKTDBG) {
810 if (err & INFINIPATH_E_REBP)
811 strlcat(buf, "EBP ", blen);
812 if (err & INFINIPATH_E_RVCRC)
813 strlcat(buf, "VCRC ", blen);
814 if (err & INFINIPATH_E_RICRC) {
815 strlcat(buf, "CRC ", blen);
816 // clear for check below, so only once
817 err &= INFINIPATH_E_RICRC;
819 if (err & INFINIPATH_E_RSHORTPKTLEN)
820 strlcat(buf, "rshortpktlen ", blen);
821 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
822 strlcat(buf, "sdroppeddatapkt ", blen);
823 if (err & INFINIPATH_E_SPKTLEN)
824 strlcat(buf, "spktlen ", blen);
826 if ((err & INFINIPATH_E_RICRC) &&
827 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
828 strlcat(buf, "CRC ", blen);
832 if (err & INFINIPATH_E_RHDRLEN)
833 strlcat(buf, "rhdrlen ", blen);
834 if (err & INFINIPATH_E_RBADTID)
835 strlcat(buf, "rbadtid ", blen);
836 if (err & INFINIPATH_E_RBADVERSION)
837 strlcat(buf, "rbadversion ", blen);
838 if (err & INFINIPATH_E_RHDR)
839 strlcat(buf, "rhdr ", blen);
840 if (err & INFINIPATH_E_RLONGPKTLEN)
841 strlcat(buf, "rlongpktlen ", blen);
842 if (err & INFINIPATH_E_RMAXPKTLEN)
843 strlcat(buf, "rmaxpktlen ", blen);
844 if (err & INFINIPATH_E_RMINPKTLEN)
845 strlcat(buf, "rminpktlen ", blen);
846 if (err & INFINIPATH_E_SMINPKTLEN)
847 strlcat(buf, "sminpktlen ", blen);
848 if (err & INFINIPATH_E_RFORMATERR)
849 strlcat(buf, "rformaterr ", blen);
850 if (err & INFINIPATH_E_RUNSUPVL)
851 strlcat(buf, "runsupvl ", blen);
852 if (err & INFINIPATH_E_RUNEXPCHAR)
853 strlcat(buf, "runexpchar ", blen);
854 if (err & INFINIPATH_E_RIBFLOW)
855 strlcat(buf, "ribflow ", blen);
856 if (err & INFINIPATH_E_SUNDERRUN)
857 strlcat(buf, "sunderrun ", blen);
858 if (err & INFINIPATH_E_SPIOARMLAUNCH)
859 strlcat(buf, "spioarmlaunch ", blen);
860 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
861 strlcat(buf, "sunexperrpktnum ", blen);
862 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
863 strlcat(buf, "sdroppedsmppkt ", blen);
864 if (err & INFINIPATH_E_SMAXPKTLEN)
865 strlcat(buf, "smaxpktlen ", blen);
866 if (err & INFINIPATH_E_SUNSUPVL)
867 strlcat(buf, "sunsupVL ", blen);
868 if (err & INFINIPATH_E_INVALIDADDR)
869 strlcat(buf, "invalidaddr ", blen);
870 if (err & INFINIPATH_E_RRCVEGRFULL)
871 strlcat(buf, "rcvegrfull ", blen);
872 if (err & INFINIPATH_E_RRCVHDRFULL)
873 strlcat(buf, "rcvhdrfull ", blen);
874 if (err & INFINIPATH_E_IBSTATUSCHANGED)
875 strlcat(buf, "ibcstatuschg ", blen);
876 if (err & INFINIPATH_E_RIBLOSTLINK)
877 strlcat(buf, "riblostlink ", blen);
878 if (err & INFINIPATH_E_HARDWARE)
879 strlcat(buf, "hardware ", blen);
880 if (err & INFINIPATH_E_RESET)
881 strlcat(buf, "reset ", blen);
887 * get_rhf_errstring - decode RHF errors
888 * @err: the err number
889 * @msg: the output buffer
890 * @len: the length of the output buffer
892 * only used one place now, may want more later
894 static void get_rhf_errstring(u32 err, char *msg, size_t len)
896 /* if no errors, and so don't need to check what's first */
899 if (err & INFINIPATH_RHF_H_ICRCERR)
900 strlcat(msg, "icrcerr ", len);
901 if (err & INFINIPATH_RHF_H_VCRCERR)
902 strlcat(msg, "vcrcerr ", len);
903 if (err & INFINIPATH_RHF_H_PARITYERR)
904 strlcat(msg, "parityerr ", len);
905 if (err & INFINIPATH_RHF_H_LENERR)
906 strlcat(msg, "lenerr ", len);
907 if (err & INFINIPATH_RHF_H_MTUERR)
908 strlcat(msg, "mtuerr ", len);
909 if (err & INFINIPATH_RHF_H_IHDRERR)
910 /* infinipath hdr checksum error */
911 strlcat(msg, "ipathhdrerr ", len);
912 if (err & INFINIPATH_RHF_H_TIDERR)
913 strlcat(msg, "tiderr ", len);
914 if (err & INFINIPATH_RHF_H_MKERR)
915 /* bad port, offset, etc. */
916 strlcat(msg, "invalid ipathhdr ", len);
917 if (err & INFINIPATH_RHF_H_IBERR)
918 strlcat(msg, "iberr ", len);
919 if (err & INFINIPATH_RHF_L_SWA)
920 strlcat(msg, "swA ", len);
921 if (err & INFINIPATH_RHF_L_SWB)
922 strlcat(msg, "swB ", len);
926 * ipath_get_egrbuf - get an eager buffer
927 * @dd: the infinipath device
928 * @bufnum: the eager buffer to get
931 * must only be called if ipath_pd[port] is known to be allocated
933 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum,
936 return dd->ipath_port0_skbinfo ?
937 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
941 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
942 * @dd: the infinipath device
943 * @gfp_mask: the sk_buff SFP mask
945 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
952 * Only fully supported way to handle this is to allocate lots
953 * extra, align as needed, and then do skb_reserve(). That wastes
954 * a lot of memory... I'll have to hack this into infinipath_copy
959 * We need 2 extra bytes for ipath_ether data sent in the
960 * key header. In order to keep everything dword aligned,
961 * we'll reserve 4 bytes.
963 len = dd->ipath_ibmaxlen + 4;
965 if (dd->ipath_flags & IPATH_4BYTE_TID) {
966 /* We need a 2KB multiple alignment, and there is no way
967 * to do it except to allocate extra and then skb_reserve
968 * enough to bring it up to the right alignment.
973 skb = __dev_alloc_skb(len, gfp_mask);
975 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
982 if (dd->ipath_flags & IPATH_4BYTE_TID) {
983 u32 una = (unsigned long)skb->data & 2047;
985 skb_reserve(skb, 2048 - una);
992 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
999 struct ipath_message_header *hdr;
1001 get_rhf_errstring(eflags, emsg, sizeof emsg);
1002 hdr = (struct ipath_message_header *)&rc[1];
1003 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1004 "tlen=%x opcode=%x egridx=%x: %s\n",
1006 ipath_hdrget_rcv_type((__le32 *) rc),
1007 ipath_hdrget_length_in_bytes((__le32 *) rc),
1008 be32_to_cpu(hdr->bth[0]) >> 24,
1011 /* Count local link integrity errors. */
1012 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1013 u8 n = (dd->ipath_ibcctrl >>
1014 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1015 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1017 if (++dd->ipath_lli_counter > n) {
1018 dd->ipath_lli_counter = 0;
1019 dd->ipath_lli_errors++;
1025 * ipath_kreceive - receive a packet
1026 * @dd: the infinipath device
1028 * called from interrupt handler for errors or receive interrupt
1030 void ipath_kreceive(struct ipath_devdata *dd)
1034 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1035 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1036 u32 etail = -1, l, hdrqtail;
1037 struct ipath_message_header *hdr;
1038 u32 eflags, i, etype, tlen, pkttot = 0, updegr=0, reloop=0;
1039 static u64 totcalls; /* stats, may eventually remove */
1041 if (!dd->ipath_hdrqtailptr) {
1043 "hdrqtailptr not set, can't do receives\n");
1047 l = dd->ipath_port0head;
1048 hdrqtail = (u32) le64_to_cpu(*dd->ipath_hdrqtailptr);
1053 for (i = 0; l != hdrqtail; i++) {
1057 rc = (u64 *) (dd->ipath_pd[0]->port_rcvhdrq + (l << 2));
1058 hdr = (struct ipath_message_header *)&rc[1];
1060 * could make a network order version of IPATH_KD_QP, and
1061 * do the obvious shift before masking to speed this up.
1063 qp = ntohl(hdr->bth[1]) & 0xffffff;
1064 bthbytes = (u8 *) hdr->bth;
1066 eflags = ipath_hdrget_err_flags((__le32 *) rc);
1067 etype = ipath_hdrget_rcv_type((__le32 *) rc);
1069 tlen = ipath_hdrget_length_in_bytes((__le32 *) rc);
1071 if (etype != RCVHQ_RCV_TYPE_EXPECTED) {
1073 * it turns out that the chips uses an eager buffer
1074 * for all non-expected packets, whether it "needs"
1075 * one or not. So always get the index, but don't
1076 * set ebuf (so we try to copy data) unless the
1077 * length requires it.
1079 etail = ipath_hdrget_index((__le32 *) rc);
1080 if (tlen > sizeof(*hdr) ||
1081 etype == RCVHQ_RCV_TYPE_NON_KD)
1082 ebuf = ipath_get_egrbuf(dd, etail, 0);
1086 * both tiderr and ipathhdrerr are set for all plain IB
1087 * packets; only ipathhdrerr should be set.
1090 if (etype != RCVHQ_RCV_TYPE_NON_KD && etype !=
1091 RCVHQ_RCV_TYPE_ERROR && ipath_hdrget_ipath_ver(
1092 hdr->iph.ver_port_tid_offset) !=
1093 IPS_PROTO_VERSION) {
1094 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1098 if (unlikely(eflags))
1099 ipath_rcv_hdrerr(dd, eflags, l, etail, rc);
1100 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1101 ipath_ib_rcv(dd->verbs_dev, rc + 1, ebuf, tlen);
1102 if (dd->ipath_lli_counter)
1103 dd->ipath_lli_counter--;
1104 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1105 "qp=%x), len %x; ignored\n",
1106 etype, bthbytes[0], qp, tlen);
1108 else if (etype == RCVHQ_RCV_TYPE_EAGER)
1109 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1110 "qp=%x), len %x; ignored\n",
1111 etype, bthbytes[0], qp, tlen);
1112 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1113 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1114 be32_to_cpu(hdr->bth[0]) & 0xff);
1117 * error packet, type of error unknown.
1118 * Probably type 3, but we don't know, so don't
1119 * even try to print the opcode, etc.
1121 ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
1122 "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
1123 "hdr %llx %llx %llx %llx %llx\n",
1124 etail, tlen, (unsigned long) rc, l,
1125 (unsigned long long) rc[0],
1126 (unsigned long long) rc[1],
1127 (unsigned long long) rc[2],
1128 (unsigned long long) rc[3],
1129 (unsigned long long) rc[4],
1130 (unsigned long long) rc[5]);
1135 if (etype != RCVHQ_RCV_TYPE_EXPECTED)
1138 * update head regs on last packet, and every 16 packets.
1139 * Reduce bus traffic, while still trying to prevent
1140 * rcvhdrq overflows, for when the queue is nearly full
1142 if (l == hdrqtail || (i && !(i&0xf))) {
1145 /* request IBA6120 interrupt only on last */
1146 lval = dd->ipath_rhdrhead_intr_off | l;
1149 (void)ipath_write_ureg(dd, ur_rcvhdrhead, lval, 0);
1151 (void)ipath_write_ureg(dd, ur_rcvegrindexhead,
1158 if (!dd->ipath_rhdrhead_intr_off && !reloop) {
1159 /* IBA6110 workaround; we can have a race clearing chip
1160 * interrupt with another interrupt about to be delivered,
1161 * and can clear it before it is delivered on the GPIO
1162 * workaround. By doing the extra check here for the
1163 * in-memory tail register updating while we were doing
1164 * earlier packets, we "almost" guarantee we have covered
1167 u32 hqtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
1168 if (hqtail != hdrqtail) {
1170 reloop = 1; /* loop 1 extra time at most */
1177 dd->ipath_port0head = l;
1179 if (pkttot > ipath_stats.sps_maxpkts_call)
1180 ipath_stats.sps_maxpkts_call = pkttot;
1181 ipath_stats.sps_port0pkts += pkttot;
1182 ipath_stats.sps_avgpkts_call =
1183 ipath_stats.sps_port0pkts / ++totcalls;
1189 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1190 * @dd: the infinipath device
1192 * called whenever our local copy indicates we have run out of send buffers
1193 * NOTE: This can be called from interrupt context by some code
1194 * and from non-interrupt context by ipath_getpiobuf().
1197 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1199 unsigned long flags;
1201 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1203 /* If the generation (check) bits have changed, then we update the
1204 * busy bit for the corresponding PIO buffer. This algorithm will
1205 * modify positions to the value they already have in some cases
1206 * (i.e., no change), but it's faster than changing only the bits
1207 * that have changed.
1209 * We would like to do this atomicly, to avoid spinlocks in the
1210 * critical send path, but that's not really possible, given the
1211 * type of changes, and that this routine could be called on
1212 * multiple cpu's simultaneously, so we lock in this routine only,
1213 * to avoid conflicting updates; all we change is the shadow, and
1214 * it's a single 64 bit memory location, so by definition the update
1215 * is atomic in terms of what other cpu's can see in testing the
1216 * bits. The spin_lock overhead isn't too bad, since it only
1217 * happens when all buffers are in use, so only cpu overhead, not
1218 * latency or bandwidth is affected.
1220 #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL
1221 if (!dd->ipath_pioavailregs_dma) {
1222 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1225 if (ipath_debug & __IPATH_VERBDBG) {
1226 /* only if packet debug and verbose */
1227 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1228 unsigned long *shadow = dd->ipath_pioavailshadow;
1230 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1231 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1233 (unsigned long long) le64_to_cpu(dma[0]),
1235 (unsigned long long) le64_to_cpu(dma[1]),
1237 (unsigned long long) le64_to_cpu(dma[2]),
1239 (unsigned long long) le64_to_cpu(dma[3]),
1243 PKT, "2nd group, dma4=%llx shad4=%lx, "
1244 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1246 (unsigned long long) le64_to_cpu(dma[4]),
1248 (unsigned long long) le64_to_cpu(dma[5]),
1250 (unsigned long long) le64_to_cpu(dma[6]),
1252 (unsigned long long) le64_to_cpu(dma[7]),
1255 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1256 for (i = 0; i < piobregs; i++) {
1257 u64 pchbusy, pchg, piov, pnew;
1259 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1264 dd->ipath_pioavailregs_dma[i - 1]);
1267 dd->ipath_pioavailregs_dma[i + 1]);
1269 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1270 pchg = _IPATH_ALL_CHECKBITS &
1271 ~(dd->ipath_pioavailshadow[i] ^ piov);
1272 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1273 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1274 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1275 pnew |= piov & pchbusy;
1276 dd->ipath_pioavailshadow[i] = pnew;
1279 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1283 * ipath_setrcvhdrsize - set the receive header size
1284 * @dd: the infinipath device
1285 * @rhdrsize: the receive header size
1287 * called from user init code, and also layered driver init
1289 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1293 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1294 if (dd->ipath_rcvhdrsize != rhdrsize) {
1295 dev_info(&dd->pcidev->dev,
1296 "Error: can't set protocol header "
1297 "size %u, already %u\n",
1298 rhdrsize, dd->ipath_rcvhdrsize);
1301 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1302 "size %u\n", dd->ipath_rcvhdrsize);
1303 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1304 (sizeof(u64) / sizeof(u32)))) {
1305 ipath_dbg("Error: can't set protocol header size %u "
1306 "(> max %u)\n", rhdrsize,
1307 dd->ipath_rcvhdrentsize -
1308 (u32) (sizeof(u64) / sizeof(u32)));
1311 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1312 dd->ipath_rcvhdrsize = rhdrsize;
1313 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1314 dd->ipath_rcvhdrsize);
1315 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1316 dd->ipath_rcvhdrsize);
1322 * ipath_getpiobuf - find an available pio buffer
1323 * @dd: the infinipath device
1324 * @pbufnum: the buffer number is placed here
1326 * do appropriate marking as busy, etc.
1327 * returns buffer number if one found (>=0), negative number is error.
1328 * Used by ipath_layer_send
1330 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 * pbufnum)
1332 int i, j, starti, updated = 0;
1333 unsigned piobcnt, iter;
1334 unsigned long flags;
1335 unsigned long *shadow = dd->ipath_pioavailshadow;
1338 piobcnt = (unsigned)(dd->ipath_piobcnt2k
1339 + dd->ipath_piobcnt4k);
1340 starti = dd->ipath_lastport_piobuf;
1341 iter = piobcnt - starti;
1342 if (dd->ipath_upd_pio_shadow) {
1344 * Minor optimization. If we had no buffers on last call,
1345 * start out by doing the update; continue and do scan even
1346 * if no buffers were updated, to be paranoid
1348 ipath_update_pio_bufs(dd);
1349 /* we scanned here, don't do it at end of scan */
1353 i = dd->ipath_lastpioindex;
1357 * while test_and_set_bit() is atomic, we do that and then the
1358 * change_bit(), and the pair is not. See if this is the cause
1359 * of the remaining armlaunch errors.
1361 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1362 for (j = 0; j < iter; j++, i++) {
1366 * To avoid bus lock overhead, we first find a candidate
1367 * buffer, then do the test and set, and continue if that
1370 if (test_bit((2 * i) + 1, shadow) ||
1371 test_and_set_bit((2 * i) + 1, shadow))
1373 /* flip generation bit */
1374 change_bit(2 * i, shadow);
1377 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1380 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1383 * first time through; shadow exhausted, but may be real
1384 * buffers available, so go see; if any updated, rescan
1388 ipath_update_pio_bufs(dd);
1393 dd->ipath_upd_pio_shadow = 1;
1395 * not atomic, but if we lose one once in a while, that's OK
1397 ipath_stats.sps_nopiobufs++;
1398 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1400 "%u pio sends with no bufavail; dmacopy: "
1401 "%llx %llx %llx %llx; shadow: "
1402 "%lx %lx %lx %lx\n",
1403 dd->ipath_consec_nopiobuf,
1404 (unsigned long long) le64_to_cpu(dma[0]),
1405 (unsigned long long) le64_to_cpu(dma[1]),
1406 (unsigned long long) le64_to_cpu(dma[2]),
1407 (unsigned long long) le64_to_cpu(dma[3]),
1408 shadow[0], shadow[1], shadow[2],
1411 * 4 buffers per byte, 4 registers above, cover rest
1414 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1415 (sizeof(shadow[0]) * 4 * 4))
1416 ipath_dbg("2nd group: dmacopy: %llx %llx "
1417 "%llx %llx; shadow: %lx %lx "
1419 (unsigned long long)
1420 le64_to_cpu(dma[4]),
1421 (unsigned long long)
1422 le64_to_cpu(dma[5]),
1423 (unsigned long long)
1424 le64_to_cpu(dma[6]),
1425 (unsigned long long)
1426 le64_to_cpu(dma[7]),
1427 shadow[4], shadow[5],
1428 shadow[6], shadow[7]);
1435 * set next starting place. Since it's just an optimization,
1436 * it doesn't matter who wins on this, so no locking
1438 dd->ipath_lastpioindex = i + 1;
1439 if (dd->ipath_upd_pio_shadow)
1440 dd->ipath_upd_pio_shadow = 0;
1441 if (dd->ipath_consec_nopiobuf)
1442 dd->ipath_consec_nopiobuf = 0;
1443 if (i < dd->ipath_piobcnt2k)
1444 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1445 i * dd->ipath_palign);
1447 buf = (u32 __iomem *)
1448 (dd->ipath_pio4kbase +
1449 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1450 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1451 i, (i < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1460 * ipath_create_rcvhdrq - create a receive header queue
1461 * @dd: the infinipath device
1462 * @pd: the port data
1464 * this must be contiguous memory (from an i/o perspective), and must be
1465 * DMA'able (which means for some systems, it will go through an IOMMU,
1466 * or be forced into a low address range).
1468 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1469 struct ipath_portdata *pd)
1473 if (!pd->port_rcvhdrq) {
1474 dma_addr_t phys_hdrqtail;
1475 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1476 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1477 sizeof(u32), PAGE_SIZE);
1479 pd->port_rcvhdrq = dma_alloc_coherent(
1480 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1483 if (!pd->port_rcvhdrq) {
1484 ipath_dev_err(dd, "attempt to allocate %d bytes "
1485 "for port %u rcvhdrq failed\n",
1486 amt, pd->port_port);
1490 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1491 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, GFP_KERNEL);
1492 if (!pd->port_rcvhdrtail_kvaddr) {
1493 ipath_dev_err(dd, "attempt to allocate 1 page "
1494 "for port %u rcvhdrqtailaddr failed\n",
1497 dma_free_coherent(&dd->pcidev->dev, amt,
1498 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
1499 pd->port_rcvhdrq = NULL;
1502 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1504 pd->port_rcvhdrq_size = amt;
1506 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1507 "for port %u rcvhdr Q\n",
1508 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1509 (unsigned long) pd->port_rcvhdrq_phys,
1510 (unsigned long) pd->port_rcvhdrq_size,
1513 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx physical\n",
1515 (unsigned long long) phys_hdrqtail);
1518 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1519 "hdrtailaddr@%p %llx physical\n",
1520 pd->port_port, pd->port_rcvhdrq,
1521 (unsigned long long) pd->port_rcvhdrq_phys,
1522 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1523 pd->port_rcvhdrqtailaddr_phys);
1525 /* clear for security and sanity on each use */
1526 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1527 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1530 * tell chip each time we init it, even if we are re-using previous
1531 * memory (we zero the register at process close)
1533 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1534 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1535 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1536 pd->port_port, pd->port_rcvhdrq_phys);
1543 int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id,
1544 u64 bits_to_wait_for, u64 * valp)
1546 unsigned long timeout;
1550 lastval = ipath_read_kreg64(dd, reg_id);
1551 /* wait a ridiculously long time */
1552 timeout = jiffies + msecs_to_jiffies(5);
1554 val = ipath_read_kreg64(dd, reg_id);
1555 /* set so they have something, even on failures. */
1557 if ((val & bits_to_wait_for) == bits_to_wait_for) {
1562 ipath_cdbg(VERBOSE, "Changed from %llx to %llx, "
1563 "waiting for %llx bits\n",
1564 (unsigned long long) lastval,
1565 (unsigned long long) val,
1566 (unsigned long long) bits_to_wait_for);
1568 if (time_after(jiffies, timeout)) {
1569 ipath_dbg("Didn't get bits %llx in register 0x%x, "
1571 (unsigned long long) bits_to_wait_for,
1572 reg_id, (unsigned long long) *valp);
1582 * ipath_waitfor_mdio_cmdready - wait for last command to complete
1583 * @dd: the infinipath device
1585 * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go
1586 * away indicating the last command has completed. It doesn't return data
1588 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd)
1590 unsigned long timeout;
1594 /* wait a ridiculously long time */
1595 timeout = jiffies + msecs_to_jiffies(5);
1597 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio);
1598 if (!(val & IPATH_MDIO_CMDVALID)) {
1603 if (time_after(jiffies, timeout)) {
1604 ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n",
1605 (unsigned long long) val);
1616 * Flush all sends that might be in the ready to send state, as well as any
1617 * that are in the process of being sent. Used whenever we need to be
1618 * sure the send side is idle. Cleans up all buffer state by canceling
1619 * all pio buffers, and issuing an abort, which cleans up anything in the
1620 * launch fifo. The cancel is superfluous on some chip versions, but
1621 * it's safer to always do it.
1622 * PIOAvail bits are updated by the chip as if normal send had happened.
1624 void ipath_cancel_sends(struct ipath_devdata *dd)
1626 ipath_dbg("Cancelling all in-progress send buffers\n");
1627 dd->ipath_lastcancel = jiffies+HZ/2; /* skip armlaunch errs a bit */
1629 * the abort bit is auto-clearing. We read scratch to be sure
1630 * that cancels and the abort have taken effect in the chip.
1632 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1633 INFINIPATH_S_ABORT);
1634 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1635 ipath_disarm_piobufs(dd, 0,
1636 (unsigned)(dd->ipath_piobcnt2k + dd->ipath_piobcnt4k));
1638 /* and again, be sure all have hit the chip */
1639 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1643 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int which)
1645 static const char *what[4] = {
1647 [INFINIPATH_IBCC_LINKCMD_INIT] = "INIT",
1648 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1649 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1651 int linkcmd = (which >> INFINIPATH_IBCC_LINKCMD_SHIFT) &
1652 INFINIPATH_IBCC_LINKCMD_MASK;
1654 ipath_cdbg(VERBOSE, "Trying to move unit %u to %s, current ltstate "
1655 "is %s\n", dd->ipath_unit,
1657 ipath_ibcstatus_str[
1659 (dd, dd->ipath_kregs->kr_ibcstatus) >>
1660 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1661 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK]);
1662 /* flush all queued sends when going to DOWN or INIT, to be sure that
1663 * they don't block MAD packets */
1664 if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT)
1665 ipath_cancel_sends(dd);
1667 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1668 dd->ipath_ibcctrl | which);
1671 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
1677 case IPATH_IB_LINKDOWN:
1678 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_POLL <<
1679 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1684 case IPATH_IB_LINKDOWN_SLEEP:
1685 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_SLEEP <<
1686 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1691 case IPATH_IB_LINKDOWN_DISABLE:
1692 ipath_set_ib_lstate(dd,
1693 INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
1694 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1699 case IPATH_IB_LINKINIT:
1700 if (dd->ipath_flags & IPATH_LINKINIT) {
1704 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_INIT <<
1705 INFINIPATH_IBCC_LINKCMD_SHIFT);
1706 lstate = IPATH_LINKINIT;
1709 case IPATH_IB_LINKARM:
1710 if (dd->ipath_flags & IPATH_LINKARMED) {
1714 if (!(dd->ipath_flags &
1715 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
1719 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED <<
1720 INFINIPATH_IBCC_LINKCMD_SHIFT);
1722 * Since the port can transition to ACTIVE by receiving
1723 * a non VL 15 packet, wait for either state.
1725 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
1728 case IPATH_IB_LINKACTIVE:
1729 if (dd->ipath_flags & IPATH_LINKACTIVE) {
1733 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
1737 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE <<
1738 INFINIPATH_IBCC_LINKCMD_SHIFT);
1739 lstate = IPATH_LINKACTIVE;
1742 case IPATH_IB_LINK_LOOPBACK:
1743 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
1744 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
1745 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1748 goto bail; // no state change to wait for
1750 case IPATH_IB_LINK_EXTERNAL:
1751 dev_info(&dd->pcidev->dev, "Disabling IB local loopback (normal)\n");
1752 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
1753 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1756 goto bail; // no state change to wait for
1759 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
1763 ret = ipath_wait_linkstate(dd, lstate, 2000);
1770 * ipath_set_mtu - set the MTU
1771 * @dd: the infinipath device
1774 * we can handle "any" incoming size, the issue here is whether we
1775 * need to restrict our outgoing size. For now, we don't do any
1776 * sanity checking on this, and we don't deal with what happens to
1777 * programs that are already running when the size changes.
1778 * NOTE: changing the MTU will usually cause the IBC to go back to
1779 * link initialize (IPATH_IBSTATE_INIT) state...
1781 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
1788 * mtu is IB data payload max. It's the largest power of 2 less
1789 * than piosize (or even larger, since it only really controls the
1790 * largest we can receive; we can send the max of the mtu and
1791 * piosize). We check that it's one of the valid IB sizes.
1793 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
1795 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
1799 if (dd->ipath_ibmtu == arg) {
1800 ret = 0; /* same as current */
1804 piosize = dd->ipath_ibmaxlen;
1805 dd->ipath_ibmtu = arg;
1807 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
1808 /* Only if it's not the initial value (or reset to it) */
1809 if (piosize != dd->ipath_init_ibmaxlen) {
1810 dd->ipath_ibmaxlen = piosize;
1813 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
1814 piosize = arg + IPATH_PIO_MAXIBHDR;
1815 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
1816 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
1818 dd->ipath_ibmaxlen = piosize;
1824 * set the IBC maxpktlength to the size of our pio
1827 u64 ibc = dd->ipath_ibcctrl;
1828 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
1829 INFINIPATH_IBCC_MAXPKTLEN_SHIFT);
1831 piosize = piosize - 2 * sizeof(u32); /* ignore pbc */
1832 dd->ipath_ibmaxlen = piosize;
1833 piosize /= sizeof(u32); /* in words */
1835 * for ICRC, which we only send in diag test pkt mode, and
1836 * we don't need to worry about that for mtu
1840 ibc |= piosize << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1841 dd->ipath_ibcctrl = ibc;
1842 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1844 dd->ipath_f_tidtemplate(dd);
1853 int ipath_set_lid(struct ipath_devdata *dd, u32 arg, u8 lmc)
1855 dd->ipath_lid = arg;
1856 dd->ipath_lmc = lmc;
1863 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
1864 * @dd: the infinipath device
1865 * @regno: the register number to write
1866 * @port: the port containing the register
1867 * @value: the value to write
1869 * Registers that vary with the chip implementation constants (port)
1872 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
1873 unsigned port, u64 value)
1877 if (port < dd->ipath_portcnt &&
1878 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
1879 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
1880 where = regno + port;
1884 ipath_write_kreg(dd, where, value);
1888 * Following deal with the "obviously simple" task of overriding the state
1889 * of the LEDS, which normally indicate link physical and logical status.
1890 * The complications arise in dealing with different hardware mappings
1891 * and the board-dependent routine being called from interrupts.
1892 * and then there's the requirement to _flash_ them.
1894 #define LED_OVER_FREQ_SHIFT 8
1895 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
1896 /* Below is "non-zero" to force override, but both actual LEDs are off */
1897 #define LED_OVER_BOTH_OFF (8)
1899 void ipath_run_led_override(unsigned long opaque)
1901 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
1904 u64 lstate, ltstate, val;
1906 if (!(dd->ipath_flags & IPATH_INITTED))
1909 pidx = dd->ipath_led_override_phase++ & 1;
1910 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
1911 timeoff = dd->ipath_led_override_timeoff;
1914 * below potentially restores the LED values per current status,
1915 * should also possibly setup the traffic-blink register,
1916 * but leave that to per-chip functions.
1918 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
1919 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1920 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
1921 lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
1922 INFINIPATH_IBCS_LINKSTATE_MASK;
1924 dd->ipath_f_setextled(dd, lstate, ltstate);
1925 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
1928 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
1932 if (!(dd->ipath_flags & IPATH_INITTED))
1935 /* First check if we are blinking. If not, use 1HZ polling */
1937 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
1940 /* For blink, set each phase from one nybble of val */
1941 dd->ipath_led_override_vals[0] = val & 0xF;
1942 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
1943 timeoff = (HZ << 4)/freq;
1945 /* Non-blink set both phases the same. */
1946 dd->ipath_led_override_vals[0] = val & 0xF;
1947 dd->ipath_led_override_vals[1] = val & 0xF;
1949 dd->ipath_led_override_timeoff = timeoff;
1952 * If the timer has not already been started, do so. Use a "quick"
1953 * timeout so the function will be called soon, to look at our request.
1955 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
1956 /* Need to start timer */
1957 init_timer(&dd->ipath_led_override_timer);
1958 dd->ipath_led_override_timer.function =
1959 ipath_run_led_override;
1960 dd->ipath_led_override_timer.data = (unsigned long) dd;
1961 dd->ipath_led_override_timer.expires = jiffies + 1;
1962 add_timer(&dd->ipath_led_override_timer);
1964 atomic_dec(&dd->ipath_led_override_timer_active);
1969 * ipath_shutdown_device - shut down a device
1970 * @dd: the infinipath device
1972 * This is called to make the device quiet when we are about to
1973 * unload the driver, and also when the device is administratively
1974 * disabled. It does not free any data structures.
1975 * Everything it does has to be setup again by ipath_init_chip(dd,1)
1977 void ipath_shutdown_device(struct ipath_devdata *dd)
1979 ipath_dbg("Shutting down the device\n");
1981 dd->ipath_flags |= IPATH_LINKUNK;
1982 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
1983 IPATH_LINKINIT | IPATH_LINKARMED |
1985 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
1986 IPATH_STATUS_IB_READY);
1988 /* mask interrupts, but not errors */
1989 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
1991 dd->ipath_rcvctrl = 0;
1992 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1996 * gracefully stop all sends allowing any in progress to trickle out
1999 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0ULL);
2001 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2003 * enough for anything that's going to trickle out to have actually
2008 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
2009 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
2010 ipath_cancel_sends(dd);
2013 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2014 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2015 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2018 * clear SerdesEnable and turn the leds off; do this here because
2019 * we are unloading, so don't count on interrupts to move along
2020 * Turn the LEDs off explictly for the same reason.
2022 dd->ipath_f_quiet_serdes(dd);
2024 if (dd->ipath_stats_timer_active) {
2025 del_timer_sync(&dd->ipath_stats_timer);
2026 dd->ipath_stats_timer_active = 0;
2030 * clear all interrupts and errors, so that the next time the driver
2031 * is loaded or device is enabled, we know that whatever is set
2032 * happened while we were unloaded
2034 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2035 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2036 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2037 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2039 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2040 ipath_update_eeprom_log(dd);
2044 * ipath_free_pddata - free a port's allocated data
2045 * @dd: the infinipath device
2046 * @pd: the portdata structure
2048 * free up any allocated data for a port
2049 * This should not touch anything that would affect a simultaneous
2050 * re-allocation of port data, because it is called after ipath_mutex
2051 * is released (and can be called from reinit as well).
2052 * It should never change any chip state, or global driver state.
2053 * (The only exception to global state is freeing the port0 port0_skbs.)
2055 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2060 if (pd->port_rcvhdrq) {
2061 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2062 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2063 (unsigned long) pd->port_rcvhdrq_size);
2064 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2065 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2066 pd->port_rcvhdrq = NULL;
2067 if (pd->port_rcvhdrtail_kvaddr) {
2068 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2069 pd->port_rcvhdrtail_kvaddr,
2070 pd->port_rcvhdrqtailaddr_phys);
2071 pd->port_rcvhdrtail_kvaddr = NULL;
2074 if (pd->port_port && pd->port_rcvegrbuf) {
2077 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2078 void *base = pd->port_rcvegrbuf[e];
2079 size_t size = pd->port_rcvegrbuf_size;
2081 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2082 "chunk %u/%u\n", base,
2083 (unsigned long) size,
2084 e, pd->port_rcvegrbuf_chunks);
2085 dma_free_coherent(&dd->pcidev->dev, size,
2086 base, pd->port_rcvegrbuf_phys[e]);
2088 kfree(pd->port_rcvegrbuf);
2089 pd->port_rcvegrbuf = NULL;
2090 kfree(pd->port_rcvegrbuf_phys);
2091 pd->port_rcvegrbuf_phys = NULL;
2092 pd->port_rcvegrbuf_chunks = 0;
2093 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2095 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2097 dd->ipath_port0_skbinfo = NULL;
2098 ipath_cdbg(VERBOSE, "free closed port %d "
2099 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2101 for (e = 0; e < dd->ipath_rcvegrcnt; e++)
2102 if (skbinfo[e].skb) {
2103 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2105 PCI_DMA_FROMDEVICE);
2106 dev_kfree_skb(skbinfo[e].skb);
2110 kfree(pd->port_tid_pg_list);
2111 vfree(pd->subport_uregbase);
2112 vfree(pd->subport_rcvegrbuf);
2113 vfree(pd->subport_rcvhdr_base);
2117 static int __init infinipath_init(void)
2121 if (ipath_debug & __IPATH_DBG)
2122 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2125 * These must be called before the driver is registered with
2126 * the PCI subsystem.
2128 idr_init(&unit_table);
2129 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2134 ret = pci_register_driver(&ipath_driver);
2136 printk(KERN_ERR IPATH_DRV_NAME
2137 ": Unable to register driver: error %d\n", -ret);
2141 ret = ipath_driver_create_group(&ipath_driver.driver);
2143 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create driver "
2144 "sysfs entries: error %d\n", -ret);
2148 ret = ipath_init_ipathfs();
2150 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2151 "ipathfs: error %d\n", -ret);
2158 ipath_driver_remove_group(&ipath_driver.driver);
2161 pci_unregister_driver(&ipath_driver);
2164 idr_destroy(&unit_table);
2170 static void __exit infinipath_cleanup(void)
2172 ipath_exit_ipathfs();
2174 ipath_driver_remove_group(&ipath_driver.driver);
2176 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2177 pci_unregister_driver(&ipath_driver);
2179 idr_destroy(&unit_table);
2183 * ipath_reset_device - reset the chip if possible
2184 * @unit: the device to reset
2186 * Whether or not reset is successful, we attempt to re-initialize the chip
2187 * (that is, much like a driver unload/reload). We clear the INITTED flag
2188 * so that the various entry points will fail until we reinitialize. For
2189 * now, we only allow this if no user ports are open that use chip resources
2191 int ipath_reset_device(int unit)
2194 struct ipath_devdata *dd = ipath_lookup(unit);
2201 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2202 /* Need to stop LED timer, _then_ shut off LEDs */
2203 del_timer_sync(&dd->ipath_led_override_timer);
2204 atomic_set(&dd->ipath_led_override_timer_active, 0);
2207 /* Shut off LEDs after we are sure timer is not running */
2208 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2209 dd->ipath_f_setextled(dd, 0, 0);
2211 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2213 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2214 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2215 "not initialized or not present\n", unit);
2221 for (i = 1; i < dd->ipath_cfgports; i++) {
2222 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2223 ipath_dbg("unit %u port %d is in use "
2224 "(PID %u cmd %s), can't reset\n",
2226 dd->ipath_pd[i]->port_pid,
2227 dd->ipath_pd[i]->port_comm);
2233 dd->ipath_flags &= ~IPATH_INITTED;
2234 ret = dd->ipath_f_reset(dd);
2236 ipath_dbg("reset was not successful\n");
2237 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2239 ret = ipath_init_chip(dd, 1);
2241 ipath_dev_err(dd, "Reinitialize unit %u after "
2242 "reset failed with %d\n", unit, ret);
2244 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2245 "resetting\n", unit);
2251 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2254 if ( new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK ) {
2257 if ( dd->ipath_rx_pol_inv != new_pol_inv ) {
2258 dd->ipath_rx_pol_inv = new_pol_inv;
2259 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2260 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2261 INFINIPATH_XGXS_RX_POL_SHIFT);
2262 val |= ((u64)dd->ipath_rx_pol_inv) <<
2263 INFINIPATH_XGXS_RX_POL_SHIFT;
2264 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2268 module_init(infinipath_init);
2269 module_exit(infinipath_cleanup);