2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include "ipath_kernel.h"
42 #include "ipath_verbs.h"
43 #include "ipath_common.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
47 const char *ipath_get_unit_name(int unit)
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
67 wait_queue_head_t ipath_sma_state_wait;
69 unsigned ipath_debug = __IPATH_INFO;
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
75 MODULE_LICENSE("GPL");
76 MODULE_AUTHOR("QLogic <support@pathscale.com>");
77 MODULE_DESCRIPTION("QLogic InfiniPath driver");
79 const char *ipath_ibcstatus_str[] = {
86 "LState6", /* unused */
87 "LState7", /* unused */
93 "LState0xD", /* unused */
99 * These variables are initialized in the chip-specific files
100 * but are defined here.
102 u16 ipath_gpio_sda_num, ipath_gpio_scl_num;
103 u64 ipath_gpio_sda, ipath_gpio_scl;
104 u64 infinipath_i_bitsextant;
105 ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;
106 u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;
108 static void __devexit ipath_remove_one(struct pci_dev *);
109 static int __devinit ipath_init_one(struct pci_dev *,
110 const struct pci_device_id *);
112 /* Only needed for registration, nothing else needs this info */
113 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
114 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
115 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
117 static const struct pci_device_id ipath_pci_tbl[] = {
118 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
119 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
123 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
125 static struct pci_driver ipath_driver = {
126 .name = IPATH_DRV_NAME,
127 .probe = ipath_init_one,
128 .remove = __devexit_p(ipath_remove_one),
129 .id_table = ipath_pci_tbl,
133 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
134 u32 *bar0, u32 *bar1)
138 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
140 ipath_dev_err(dd, "failed to read bar0 before enable: "
143 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
145 ipath_dev_err(dd, "failed to read bar1 before enable: "
148 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
151 static void ipath_free_devdata(struct pci_dev *pdev,
152 struct ipath_devdata *dd)
156 pci_set_drvdata(pdev, NULL);
158 if (dd->ipath_unit != -1) {
159 spin_lock_irqsave(&ipath_devs_lock, flags);
160 idr_remove(&unit_table, dd->ipath_unit);
161 list_del(&dd->ipath_list);
162 spin_unlock_irqrestore(&ipath_devs_lock, flags);
167 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
170 struct ipath_devdata *dd;
173 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
174 dd = ERR_PTR(-ENOMEM);
178 dd = vmalloc(sizeof(*dd));
180 dd = ERR_PTR(-ENOMEM);
183 memset(dd, 0, sizeof(*dd));
186 spin_lock_irqsave(&ipath_devs_lock, flags);
188 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
190 printk(KERN_ERR IPATH_DRV_NAME
191 ": Could not allocate unit ID: error %d\n", -ret);
192 ipath_free_devdata(pdev, dd);
198 pci_set_drvdata(pdev, dd);
200 list_add(&dd->ipath_list, &ipath_dev_list);
203 spin_unlock_irqrestore(&ipath_devs_lock, flags);
209 static inline struct ipath_devdata *__ipath_lookup(int unit)
211 return idr_find(&unit_table, unit);
214 struct ipath_devdata *ipath_lookup(int unit)
216 struct ipath_devdata *dd;
219 spin_lock_irqsave(&ipath_devs_lock, flags);
220 dd = __ipath_lookup(unit);
221 spin_unlock_irqrestore(&ipath_devs_lock, flags);
226 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp)
228 int nunits, npresent, nup;
229 struct ipath_devdata *dd;
233 nunits = npresent = nup = maxports = 0;
235 spin_lock_irqsave(&ipath_devs_lock, flags);
237 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
239 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
242 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
245 if (dd->ipath_cfgports > maxports)
246 maxports = dd->ipath_cfgports;
249 spin_unlock_irqrestore(&ipath_devs_lock, flags);
252 *npresentp = npresent;
256 *maxportsp = maxports;
262 * These next two routines are placeholders in case we don't have per-arch
263 * code for controlling write combining. If explicit control of write
264 * combining is not available, performance will probably be awful.
267 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
272 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
276 static int __devinit ipath_init_one(struct pci_dev *pdev,
277 const struct pci_device_id *ent)
280 struct ipath_devdata *dd;
281 unsigned long long addr;
282 u32 bar0 = 0, bar1 = 0;
285 dd = ipath_alloc_devdata(pdev);
288 printk(KERN_ERR IPATH_DRV_NAME
289 ": Could not allocate devdata: error %d\n", -ret);
293 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
295 read_bars(dd, pdev, &bar0, &bar1);
297 ret = pci_enable_device(pdev);
299 /* This can happen iff:
301 * We did a chip reset, and then failed to reprogram the
302 * BAR, or the chip reset due to an internal error. We then
303 * unloaded the driver and reloaded it.
305 * Both reset cases set the BAR back to initial state. For
306 * the latter case, the AER sticky error bit at offset 0x718
307 * should be set, but the Linux kernel doesn't yet know
308 * about that, it appears. If the original BAR was retained
309 * in the kernel data structures, this may be OK.
311 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
312 dd->ipath_unit, -ret);
315 addr = pci_resource_start(pdev, 0);
316 len = pci_resource_len(pdev, 0);
317 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %x, vend %x/%x "
318 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
319 ent->device, ent->driver_data);
321 read_bars(dd, pdev, &bar0, &bar1);
323 if (!bar1 && !(bar0 & ~0xf)) {
325 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
326 "rewriting as %llx\n", addr);
327 ret = pci_write_config_dword(
328 pdev, PCI_BASE_ADDRESS_0, addr);
330 ipath_dev_err(dd, "rewrite of BAR0 "
331 "failed: err %d\n", -ret);
334 ret = pci_write_config_dword(
335 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
337 ipath_dev_err(dd, "rewrite of BAR1 "
338 "failed: err %d\n", -ret);
342 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
343 "not usable until reboot\n");
349 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
351 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
352 "err %d\n", dd->ipath_unit, -ret);
356 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
359 * if the 64 bit setup fails, try 32 bit. Some systems
360 * do not setup 64 bit maps on systems with 2GB or less
363 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
366 "Unable to set DMA mask for unit %u: %d\n",
367 dd->ipath_unit, ret);
371 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
372 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
375 "Unable to set DMA consistent mask "
377 dd->ipath_unit, ret);
382 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
385 "Unable to set DMA consistent mask "
387 dd->ipath_unit, ret);
390 pci_set_master(pdev);
393 * Save BARs to rewrite after device reset. Save all 64 bits of
396 dd->ipath_pcibar0 = addr;
397 dd->ipath_pcibar1 = addr >> 32;
398 dd->ipath_deviceid = ent->device; /* save for later use */
399 dd->ipath_vendorid = ent->vendor;
401 /* setup the chip-specific functions, as early as possible. */
402 switch (ent->device) {
403 case PCI_DEVICE_ID_INFINIPATH_HT:
404 ipath_init_ht400_funcs(dd);
406 case PCI_DEVICE_ID_INFINIPATH_PE800:
407 ipath_init_pe800_funcs(dd);
410 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
411 "failing\n", ent->device);
415 for (j = 0; j < 6; j++) {
416 if (!pdev->resource[j].start)
418 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
419 j, (unsigned long long)pdev->resource[j].start,
420 (unsigned long long)pdev->resource[j].end,
421 (unsigned long long)pci_resource_len(pdev, j));
425 ipath_dev_err(dd, "No valid address in BAR 0!\n");
430 dd->ipath_deviceid = ent->device; /* save for later use */
431 dd->ipath_vendorid = ent->vendor;
433 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
435 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
436 "%u: err %d\n", dd->ipath_unit, -ret);
437 goto bail_regions; /* shouldn't ever happen */
439 dd->ipath_pcirev = rev;
441 #if defined(__powerpc__)
442 /* There isn't a generic way to specify writethrough mappings */
443 dd->ipath_kregbase = __ioremap(addr, len,
444 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
446 dd->ipath_kregbase = ioremap_nocache(addr, len);
449 if (!dd->ipath_kregbase) {
450 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
455 dd->ipath_kregend = (u64 __iomem *)
456 ((void __iomem *)dd->ipath_kregbase + len);
457 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
459 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
460 addr, dd->ipath_kregbase);
463 * clear ipath_flags here instead of in ipath_init_chip as it is set
464 * by ipath_setup_htconfig.
467 dd->ipath_lli_counter = 0;
468 dd->ipath_lli_errors = 0;
470 if (dd->ipath_f_bus(dd, pdev))
471 ipath_dev_err(dd, "Failed to setup config space; "
472 "continuing anyway\n");
475 * set up our interrupt handler; IRQF_SHARED probably not needed,
476 * since MSI interrupts shouldn't be shared but won't hurt for now.
477 * check 0 irq after we return from chip-specific bus setup, since
478 * that can affect this due to setup
481 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
484 ret = request_irq(pdev->irq, ipath_intr, IRQF_SHARED,
487 ipath_dev_err(dd, "Couldn't setup irq handler, "
488 "irq=%u: %d\n", pdev->irq, ret);
493 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
497 ret = ipath_enable_wc(dd);
500 ipath_dev_err(dd, "Write combining not enabled "
501 "(err %d): performance may be poor\n",
506 ipath_device_create_group(&pdev->dev, dd);
507 ipathfs_add_device(dd);
510 ipath_register_ib_device(dd);
515 iounmap((volatile void __iomem *) dd->ipath_kregbase);
518 pci_release_regions(pdev);
521 pci_disable_device(pdev);
524 ipath_free_devdata(pdev, dd);
530 static void __devexit ipath_remove_one(struct pci_dev *pdev)
532 struct ipath_devdata *dd;
534 ipath_cdbg(VERBOSE, "removing, pdev=%p\n", pdev);
538 dd = pci_get_drvdata(pdev);
539 ipath_unregister_ib_device(dd->verbs_dev);
540 ipath_diag_remove(dd);
541 ipath_user_remove(dd);
542 ipathfs_remove_device(dd);
543 ipath_device_remove_group(&pdev->dev, dd);
544 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
545 "unit %u\n", dd, (u32) dd->ipath_unit);
546 if (dd->ipath_kregbase) {
547 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n",
549 iounmap((volatile void __iomem *) dd->ipath_kregbase);
550 dd->ipath_kregbase = NULL;
552 pci_release_regions(pdev);
553 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
554 pci_disable_device(pdev);
556 ipath_free_devdata(pdev, dd);
559 /* general driver use */
560 DEFINE_MUTEX(ipath_mutex);
562 static DEFINE_SPINLOCK(ipath_pioavail_lock);
565 * ipath_disarm_piobufs - cancel a range of PIO buffers
566 * @dd: the infinipath device
567 * @first: the first PIO buffer to cancel
568 * @cnt: the number of PIO buffers to cancel
570 * cancel a range of PIO buffers, used when they might be armed, but
571 * not triggered. Used at init to ensure buffer state, and also user
572 * process close, in case it died while writing to a PIO buffer
575 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
578 unsigned i, last = first + cnt;
579 u64 sendctrl, sendorig;
581 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
582 sendorig = dd->ipath_sendctrl | INFINIPATH_S_DISARM;
583 for (i = first; i < last; i++) {
584 sendctrl = sendorig |
585 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT);
586 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
591 * Write it again with current value, in case ipath_sendctrl changed
592 * while we were looping; no critical bits that would require
595 * Write a 0, and then the original value, reading scratch in
596 * between. This seems to avoid a chip timing race that causes
597 * pioavail updates to memory to stop.
599 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
601 sendorig = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
602 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
607 * ipath_wait_linkstate - wait for an IB link state change to occur
608 * @dd: the infinipath device
609 * @state: the state to wait for
610 * @msecs: the number of milliseconds to wait
612 * wait up to msecs milliseconds for IB link state change to occur for
613 * now, take the easy polling route. Currently used only by
614 * ipath_set_linkstate. Returns 0 if state reached, otherwise
615 * -ETIMEDOUT state can have multiple states set, for any of several
618 static int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state,
621 dd->ipath_sma_state_wanted = state;
622 wait_event_interruptible_timeout(ipath_sma_state_wait,
623 (dd->ipath_flags & state),
624 msecs_to_jiffies(msecs));
625 dd->ipath_sma_state_wanted = 0;
627 if (!(dd->ipath_flags & state)) {
629 ipath_cdbg(SMA, "Didn't reach linkstate %s within %u ms\n",
630 /* test INIT ahead of DOWN, both can be set */
631 (state & IPATH_LINKINIT) ? "INIT" :
632 ((state & IPATH_LINKDOWN) ? "DOWN" :
633 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
635 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
636 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
637 (unsigned long long) ipath_read_kreg64(
638 dd, dd->ipath_kregs->kr_ibcctrl),
639 (unsigned long long) val,
640 ipath_ibcstatus_str[val & 0xf]);
642 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
645 void ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
648 if (err & INFINIPATH_E_RHDRLEN)
649 strlcat(buf, "rhdrlen ", blen);
650 if (err & INFINIPATH_E_RBADTID)
651 strlcat(buf, "rbadtid ", blen);
652 if (err & INFINIPATH_E_RBADVERSION)
653 strlcat(buf, "rbadversion ", blen);
654 if (err & INFINIPATH_E_RHDR)
655 strlcat(buf, "rhdr ", blen);
656 if (err & INFINIPATH_E_RLONGPKTLEN)
657 strlcat(buf, "rlongpktlen ", blen);
658 if (err & INFINIPATH_E_RSHORTPKTLEN)
659 strlcat(buf, "rshortpktlen ", blen);
660 if (err & INFINIPATH_E_RMAXPKTLEN)
661 strlcat(buf, "rmaxpktlen ", blen);
662 if (err & INFINIPATH_E_RMINPKTLEN)
663 strlcat(buf, "rminpktlen ", blen);
664 if (err & INFINIPATH_E_RFORMATERR)
665 strlcat(buf, "rformaterr ", blen);
666 if (err & INFINIPATH_E_RUNSUPVL)
667 strlcat(buf, "runsupvl ", blen);
668 if (err & INFINIPATH_E_RUNEXPCHAR)
669 strlcat(buf, "runexpchar ", blen);
670 if (err & INFINIPATH_E_RIBFLOW)
671 strlcat(buf, "ribflow ", blen);
672 if (err & INFINIPATH_E_REBP)
673 strlcat(buf, "EBP ", blen);
674 if (err & INFINIPATH_E_SUNDERRUN)
675 strlcat(buf, "sunderrun ", blen);
676 if (err & INFINIPATH_E_SPIOARMLAUNCH)
677 strlcat(buf, "spioarmlaunch ", blen);
678 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
679 strlcat(buf, "sunexperrpktnum ", blen);
680 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
681 strlcat(buf, "sdroppeddatapkt ", blen);
682 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
683 strlcat(buf, "sdroppedsmppkt ", blen);
684 if (err & INFINIPATH_E_SMAXPKTLEN)
685 strlcat(buf, "smaxpktlen ", blen);
686 if (err & INFINIPATH_E_SMINPKTLEN)
687 strlcat(buf, "sminpktlen ", blen);
688 if (err & INFINIPATH_E_SUNSUPVL)
689 strlcat(buf, "sunsupVL ", blen);
690 if (err & INFINIPATH_E_SPKTLEN)
691 strlcat(buf, "spktlen ", blen);
692 if (err & INFINIPATH_E_INVALIDADDR)
693 strlcat(buf, "invalidaddr ", blen);
694 if (err & INFINIPATH_E_RICRC)
695 strlcat(buf, "CRC ", blen);
696 if (err & INFINIPATH_E_RVCRC)
697 strlcat(buf, "VCRC ", blen);
698 if (err & INFINIPATH_E_RRCVEGRFULL)
699 strlcat(buf, "rcvegrfull ", blen);
700 if (err & INFINIPATH_E_RRCVHDRFULL)
701 strlcat(buf, "rcvhdrfull ", blen);
702 if (err & INFINIPATH_E_IBSTATUSCHANGED)
703 strlcat(buf, "ibcstatuschg ", blen);
704 if (err & INFINIPATH_E_RIBLOSTLINK)
705 strlcat(buf, "riblostlink ", blen);
706 if (err & INFINIPATH_E_HARDWARE)
707 strlcat(buf, "hardware ", blen);
708 if (err & INFINIPATH_E_RESET)
709 strlcat(buf, "reset ", blen);
713 * get_rhf_errstring - decode RHF errors
714 * @err: the err number
715 * @msg: the output buffer
716 * @len: the length of the output buffer
718 * only used one place now, may want more later
720 static void get_rhf_errstring(u32 err, char *msg, size_t len)
722 /* if no errors, and so don't need to check what's first */
725 if (err & INFINIPATH_RHF_H_ICRCERR)
726 strlcat(msg, "icrcerr ", len);
727 if (err & INFINIPATH_RHF_H_VCRCERR)
728 strlcat(msg, "vcrcerr ", len);
729 if (err & INFINIPATH_RHF_H_PARITYERR)
730 strlcat(msg, "parityerr ", len);
731 if (err & INFINIPATH_RHF_H_LENERR)
732 strlcat(msg, "lenerr ", len);
733 if (err & INFINIPATH_RHF_H_MTUERR)
734 strlcat(msg, "mtuerr ", len);
735 if (err & INFINIPATH_RHF_H_IHDRERR)
736 /* infinipath hdr checksum error */
737 strlcat(msg, "ipathhdrerr ", len);
738 if (err & INFINIPATH_RHF_H_TIDERR)
739 strlcat(msg, "tiderr ", len);
740 if (err & INFINIPATH_RHF_H_MKERR)
741 /* bad port, offset, etc. */
742 strlcat(msg, "invalid ipathhdr ", len);
743 if (err & INFINIPATH_RHF_H_IBERR)
744 strlcat(msg, "iberr ", len);
745 if (err & INFINIPATH_RHF_L_SWA)
746 strlcat(msg, "swA ", len);
747 if (err & INFINIPATH_RHF_L_SWB)
748 strlcat(msg, "swB ", len);
752 * ipath_get_egrbuf - get an eager buffer
753 * @dd: the infinipath device
754 * @bufnum: the eager buffer to get
757 * must only be called if ipath_pd[port] is known to be allocated
759 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum,
762 return dd->ipath_port0_skbs ?
763 (void *)dd->ipath_port0_skbs[bufnum]->data : NULL;
767 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
768 * @dd: the infinipath device
769 * @gfp_mask: the sk_buff SFP mask
771 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
778 * Only fully supported way to handle this is to allocate lots
779 * extra, align as needed, and then do skb_reserve(). That wastes
780 * a lot of memory... I'll have to hack this into infinipath_copy
785 * We need 4 extra bytes for unaligned transfer copying
787 if (dd->ipath_flags & IPATH_4BYTE_TID) {
788 /* we need a 4KB multiple alignment, and there is no way
789 * to do it except to allocate extra and then skb_reserve
790 * enough to bring it up to the right alignment.
792 len = dd->ipath_ibmaxlen + 4 + (1 << 11) - 1;
795 len = dd->ipath_ibmaxlen + 4;
796 skb = __dev_alloc_skb(len, gfp_mask);
798 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
802 if (dd->ipath_flags & IPATH_4BYTE_TID) {
803 u32 una = ((1 << 11) - 1) & (unsigned long)(skb->data + 4);
805 skb_reserve(skb, 4 + (1 << 11) - una);
815 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
822 struct ipath_message_header *hdr;
824 get_rhf_errstring(eflags, emsg, sizeof emsg);
825 hdr = (struct ipath_message_header *)&rc[1];
826 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
827 "tlen=%x opcode=%x egridx=%x: %s\n",
829 ipath_hdrget_rcv_type((__le32 *) rc),
830 ipath_hdrget_length_in_bytes((__le32 *) rc),
831 be32_to_cpu(hdr->bth[0]) >> 24,
834 /* Count local link integrity errors. */
835 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
836 u8 n = (dd->ipath_ibcctrl >>
837 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
838 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
840 if (++dd->ipath_lli_counter > n) {
841 dd->ipath_lli_counter = 0;
842 dd->ipath_lli_errors++;
848 * ipath_kreceive - receive a packet
849 * @dd: the infinipath device
851 * called from interrupt handler for errors or receive interrupt
853 void ipath_kreceive(struct ipath_devdata *dd)
857 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
858 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
859 u32 etail = -1, l, hdrqtail;
860 struct ipath_message_header *hdr;
861 u32 eflags, i, etype, tlen, pkttot = 0, updegr=0, reloop=0;
862 static u64 totcalls; /* stats, may eventually remove */
864 if (!dd->ipath_hdrqtailptr) {
866 "hdrqtailptr not set, can't do receives\n");
870 /* There is already a thread processing this queue. */
871 if (test_and_set_bit(0, &dd->ipath_rcv_pending))
874 l = dd->ipath_port0head;
875 hdrqtail = (u32) le64_to_cpu(*dd->ipath_hdrqtailptr);
880 for (i = 0; l != hdrqtail; i++) {
884 rc = (u64 *) (dd->ipath_pd[0]->port_rcvhdrq + (l << 2));
885 hdr = (struct ipath_message_header *)&rc[1];
887 * could make a network order version of IPATH_KD_QP, and
888 * do the obvious shift before masking to speed this up.
890 qp = ntohl(hdr->bth[1]) & 0xffffff;
891 bthbytes = (u8 *) hdr->bth;
893 eflags = ipath_hdrget_err_flags((__le32 *) rc);
894 etype = ipath_hdrget_rcv_type((__le32 *) rc);
896 tlen = ipath_hdrget_length_in_bytes((__le32 *) rc);
898 if (etype != RCVHQ_RCV_TYPE_EXPECTED) {
900 * it turns out that the chips uses an eager buffer
901 * for all non-expected packets, whether it "needs"
902 * one or not. So always get the index, but don't
903 * set ebuf (so we try to copy data) unless the
904 * length requires it.
906 etail = ipath_hdrget_index((__le32 *) rc);
907 if (tlen > sizeof(*hdr) ||
908 etype == RCVHQ_RCV_TYPE_NON_KD)
909 ebuf = ipath_get_egrbuf(dd, etail, 0);
913 * both tiderr and ipathhdrerr are set for all plain IB
914 * packets; only ipathhdrerr should be set.
917 if (etype != RCVHQ_RCV_TYPE_NON_KD && etype !=
918 RCVHQ_RCV_TYPE_ERROR && ipath_hdrget_ipath_ver(
919 hdr->iph.ver_port_tid_offset) !=
921 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
925 if (unlikely(eflags))
926 ipath_rcv_hdrerr(dd, eflags, l, etail, rc);
927 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
928 ipath_ib_rcv(dd->verbs_dev, rc + 1, ebuf, tlen);
929 if (dd->ipath_lli_counter)
930 dd->ipath_lli_counter--;
931 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
932 "qp=%x), len %x; ignored\n",
933 etype, bthbytes[0], qp, tlen);
935 else if (etype == RCVHQ_RCV_TYPE_EAGER)
936 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
937 "qp=%x), len %x; ignored\n",
938 etype, bthbytes[0], qp, tlen);
939 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
940 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
941 be32_to_cpu(hdr->bth[0]) & 0xff);
944 * error packet, type of error unknown.
945 * Probably type 3, but we don't know, so don't
946 * even try to print the opcode, etc.
948 ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
949 "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
950 "hdr %llx %llx %llx %llx %llx\n",
951 etail, tlen, (unsigned long) rc, l,
952 (unsigned long long) rc[0],
953 (unsigned long long) rc[1],
954 (unsigned long long) rc[2],
955 (unsigned long long) rc[3],
956 (unsigned long long) rc[4],
957 (unsigned long long) rc[5]);
962 if (etype != RCVHQ_RCV_TYPE_EXPECTED)
965 * update head regs on last packet, and every 16 packets.
966 * Reduce bus traffic, while still trying to prevent
967 * rcvhdrq overflows, for when the queue is nearly full
969 if (l == hdrqtail || (i && !(i&0xf))) {
971 if (l == hdrqtail) /* PE-800 interrupt only on last */
972 lval = dd->ipath_rhdrhead_intr_off | l;
975 (void)ipath_write_ureg(dd, ur_rcvhdrhead, lval, 0);
977 (void)ipath_write_ureg(dd, ur_rcvegrindexhead,
984 if (!dd->ipath_rhdrhead_intr_off && !reloop) {
985 /* HT-400 workaround; we can have a race clearing chip
986 * interrupt with another interrupt about to be delivered,
987 * and can clear it before it is delivered on the GPIO
988 * workaround. By doing the extra check here for the
989 * in-memory tail register updating while we were doing
990 * earlier packets, we "almost" guarantee we have covered
993 u32 hqtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
994 if (hqtail != hdrqtail) {
996 reloop = 1; /* loop 1 extra time at most */
1003 dd->ipath_port0head = l;
1005 if (pkttot > ipath_stats.sps_maxpkts_call)
1006 ipath_stats.sps_maxpkts_call = pkttot;
1007 ipath_stats.sps_port0pkts += pkttot;
1008 ipath_stats.sps_avgpkts_call =
1009 ipath_stats.sps_port0pkts / ++totcalls;
1012 clear_bit(0, &dd->ipath_rcv_pending);
1013 smp_mb__after_clear_bit();
1019 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1020 * @dd: the infinipath device
1022 * called whenever our local copy indicates we have run out of send buffers
1023 * NOTE: This can be called from interrupt context by some code
1024 * and from non-interrupt context by ipath_getpiobuf().
1027 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1029 unsigned long flags;
1031 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1033 /* If the generation (check) bits have changed, then we update the
1034 * busy bit for the corresponding PIO buffer. This algorithm will
1035 * modify positions to the value they already have in some cases
1036 * (i.e., no change), but it's faster than changing only the bits
1037 * that have changed.
1039 * We would like to do this atomicly, to avoid spinlocks in the
1040 * critical send path, but that's not really possible, given the
1041 * type of changes, and that this routine could be called on
1042 * multiple cpu's simultaneously, so we lock in this routine only,
1043 * to avoid conflicting updates; all we change is the shadow, and
1044 * it's a single 64 bit memory location, so by definition the update
1045 * is atomic in terms of what other cpu's can see in testing the
1046 * bits. The spin_lock overhead isn't too bad, since it only
1047 * happens when all buffers are in use, so only cpu overhead, not
1048 * latency or bandwidth is affected.
1050 #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL
1051 if (!dd->ipath_pioavailregs_dma) {
1052 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1055 if (ipath_debug & __IPATH_VERBDBG) {
1056 /* only if packet debug and verbose */
1057 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1058 unsigned long *shadow = dd->ipath_pioavailshadow;
1060 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1061 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1063 (unsigned long long) le64_to_cpu(dma[0]),
1065 (unsigned long long) le64_to_cpu(dma[1]),
1067 (unsigned long long) le64_to_cpu(dma[2]),
1069 (unsigned long long) le64_to_cpu(dma[3]),
1073 PKT, "2nd group, dma4=%llx shad4=%lx, "
1074 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1076 (unsigned long long) le64_to_cpu(dma[4]),
1078 (unsigned long long) le64_to_cpu(dma[5]),
1080 (unsigned long long) le64_to_cpu(dma[6]),
1082 (unsigned long long) le64_to_cpu(dma[7]),
1085 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1086 for (i = 0; i < piobregs; i++) {
1087 u64 pchbusy, pchg, piov, pnew;
1089 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1094 dd->ipath_pioavailregs_dma[i - 1]);
1097 dd->ipath_pioavailregs_dma[i + 1]);
1099 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1100 pchg = _IPATH_ALL_CHECKBITS &
1101 ~(dd->ipath_pioavailshadow[i] ^ piov);
1102 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1103 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1104 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1105 pnew |= piov & pchbusy;
1106 dd->ipath_pioavailshadow[i] = pnew;
1109 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1113 * ipath_setrcvhdrsize - set the receive header size
1114 * @dd: the infinipath device
1115 * @rhdrsize: the receive header size
1117 * called from user init code, and also layered driver init
1119 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1123 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1124 if (dd->ipath_rcvhdrsize != rhdrsize) {
1125 dev_info(&dd->pcidev->dev,
1126 "Error: can't set protocol header "
1127 "size %u, already %u\n",
1128 rhdrsize, dd->ipath_rcvhdrsize);
1131 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1132 "size %u\n", dd->ipath_rcvhdrsize);
1133 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1134 (sizeof(u64) / sizeof(u32)))) {
1135 ipath_dbg("Error: can't set protocol header size %u "
1136 "(> max %u)\n", rhdrsize,
1137 dd->ipath_rcvhdrentsize -
1138 (u32) (sizeof(u64) / sizeof(u32)));
1141 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1142 dd->ipath_rcvhdrsize = rhdrsize;
1143 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1144 dd->ipath_rcvhdrsize);
1145 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1146 dd->ipath_rcvhdrsize);
1152 * ipath_getpiobuf - find an available pio buffer
1153 * @dd: the infinipath device
1154 * @pbufnum: the buffer number is placed here
1156 * do appropriate marking as busy, etc.
1157 * returns buffer number if one found (>=0), negative number is error.
1158 * Used by ipath_sma_send_pkt and ipath_layer_send
1160 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 * pbufnum)
1162 int i, j, starti, updated = 0;
1163 unsigned piobcnt, iter;
1164 unsigned long flags;
1165 unsigned long *shadow = dd->ipath_pioavailshadow;
1168 piobcnt = (unsigned)(dd->ipath_piobcnt2k
1169 + dd->ipath_piobcnt4k);
1170 starti = dd->ipath_lastport_piobuf;
1171 iter = piobcnt - starti;
1172 if (dd->ipath_upd_pio_shadow) {
1174 * Minor optimization. If we had no buffers on last call,
1175 * start out by doing the update; continue and do scan even
1176 * if no buffers were updated, to be paranoid
1178 ipath_update_pio_bufs(dd);
1179 /* we scanned here, don't do it at end of scan */
1183 i = dd->ipath_lastpioindex;
1187 * while test_and_set_bit() is atomic, we do that and then the
1188 * change_bit(), and the pair is not. See if this is the cause
1189 * of the remaining armlaunch errors.
1191 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1192 for (j = 0; j < iter; j++, i++) {
1196 * To avoid bus lock overhead, we first find a candidate
1197 * buffer, then do the test and set, and continue if that
1200 if (test_bit((2 * i) + 1, shadow) ||
1201 test_and_set_bit((2 * i) + 1, shadow))
1203 /* flip generation bit */
1204 change_bit(2 * i, shadow);
1207 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1210 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1213 * first time through; shadow exhausted, but may be real
1214 * buffers available, so go see; if any updated, rescan
1218 ipath_update_pio_bufs(dd);
1223 dd->ipath_upd_pio_shadow = 1;
1225 * not atomic, but if we lose one once in a while, that's OK
1227 ipath_stats.sps_nopiobufs++;
1228 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1230 "%u pio sends with no bufavail; dmacopy: "
1231 "%llx %llx %llx %llx; shadow: "
1232 "%lx %lx %lx %lx\n",
1233 dd->ipath_consec_nopiobuf,
1234 (unsigned long long) le64_to_cpu(dma[0]),
1235 (unsigned long long) le64_to_cpu(dma[1]),
1236 (unsigned long long) le64_to_cpu(dma[2]),
1237 (unsigned long long) le64_to_cpu(dma[3]),
1238 shadow[0], shadow[1], shadow[2],
1241 * 4 buffers per byte, 4 registers above, cover rest
1244 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1245 (sizeof(shadow[0]) * 4 * 4))
1246 ipath_dbg("2nd group: dmacopy: %llx %llx "
1247 "%llx %llx; shadow: %lx %lx "
1249 (unsigned long long)
1250 le64_to_cpu(dma[4]),
1251 (unsigned long long)
1252 le64_to_cpu(dma[5]),
1253 (unsigned long long)
1254 le64_to_cpu(dma[6]),
1255 (unsigned long long)
1256 le64_to_cpu(dma[7]),
1257 shadow[4], shadow[5],
1258 shadow[6], shadow[7]);
1265 * set next starting place. Since it's just an optimization,
1266 * it doesn't matter who wins on this, so no locking
1268 dd->ipath_lastpioindex = i + 1;
1269 if (dd->ipath_upd_pio_shadow)
1270 dd->ipath_upd_pio_shadow = 0;
1271 if (dd->ipath_consec_nopiobuf)
1272 dd->ipath_consec_nopiobuf = 0;
1273 if (i < dd->ipath_piobcnt2k)
1274 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1275 i * dd->ipath_palign);
1277 buf = (u32 __iomem *)
1278 (dd->ipath_pio4kbase +
1279 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1280 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1281 i, (i < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1290 * ipath_create_rcvhdrq - create a receive header queue
1291 * @dd: the infinipath device
1292 * @pd: the port data
1294 * this must be contiguous memory (from an i/o perspective), and must be
1295 * DMA'able (which means for some systems, it will go through an IOMMU,
1296 * or be forced into a low address range).
1298 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1299 struct ipath_portdata *pd)
1303 if (!pd->port_rcvhdrq) {
1304 dma_addr_t phys_hdrqtail;
1305 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1306 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1307 sizeof(u32), PAGE_SIZE);
1309 pd->port_rcvhdrq = dma_alloc_coherent(
1310 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1313 if (!pd->port_rcvhdrq) {
1314 ipath_dev_err(dd, "attempt to allocate %d bytes "
1315 "for port %u rcvhdrq failed\n",
1316 amt, pd->port_port);
1320 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1321 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, GFP_KERNEL);
1322 if (!pd->port_rcvhdrtail_kvaddr) {
1323 ipath_dev_err(dd, "attempt to allocate 1 page "
1324 "for port %u rcvhdrqtailaddr failed\n",
1329 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1331 pd->port_rcvhdrq_size = amt;
1333 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1334 "for port %u rcvhdr Q\n",
1335 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1336 (unsigned long) pd->port_rcvhdrq_phys,
1337 (unsigned long) pd->port_rcvhdrq_size,
1340 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx physical\n",
1342 (unsigned long long) phys_hdrqtail);
1345 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1346 "hdrtailaddr@%p %llx physical\n",
1347 pd->port_port, pd->port_rcvhdrq,
1348 pd->port_rcvhdrq_phys, pd->port_rcvhdrtail_kvaddr,
1349 (unsigned long long)pd->port_rcvhdrqtailaddr_phys);
1351 /* clear for security and sanity on each use */
1352 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1353 memset((void *)pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1356 * tell chip each time we init it, even if we are re-using previous
1357 * memory (we zero the register at process close)
1359 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1360 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1361 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1362 pd->port_port, pd->port_rcvhdrq_phys);
1369 int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id,
1370 u64 bits_to_wait_for, u64 * valp)
1372 unsigned long timeout;
1376 lastval = ipath_read_kreg64(dd, reg_id);
1377 /* wait a ridiculously long time */
1378 timeout = jiffies + msecs_to_jiffies(5);
1380 val = ipath_read_kreg64(dd, reg_id);
1381 /* set so they have something, even on failures. */
1383 if ((val & bits_to_wait_for) == bits_to_wait_for) {
1388 ipath_cdbg(VERBOSE, "Changed from %llx to %llx, "
1389 "waiting for %llx bits\n",
1390 (unsigned long long) lastval,
1391 (unsigned long long) val,
1392 (unsigned long long) bits_to_wait_for);
1394 if (time_after(jiffies, timeout)) {
1395 ipath_dbg("Didn't get bits %llx in register 0x%x, "
1397 (unsigned long long) bits_to_wait_for,
1398 reg_id, (unsigned long long) *valp);
1408 * ipath_waitfor_mdio_cmdready - wait for last command to complete
1409 * @dd: the infinipath device
1411 * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go
1412 * away indicating the last command has completed. It doesn't return data
1414 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd)
1416 unsigned long timeout;
1420 /* wait a ridiculously long time */
1421 timeout = jiffies + msecs_to_jiffies(5);
1423 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio);
1424 if (!(val & IPATH_MDIO_CMDVALID)) {
1429 if (time_after(jiffies, timeout)) {
1430 ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n",
1431 (unsigned long long) val);
1440 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int which)
1442 static const char *what[4] = {
1444 [INFINIPATH_IBCC_LINKCMD_INIT] = "INIT",
1445 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1446 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1448 int linkcmd = (which >> INFINIPATH_IBCC_LINKCMD_SHIFT) &
1449 INFINIPATH_IBCC_LINKCMD_MASK;
1451 ipath_cdbg(SMA, "Trying to move unit %u to %s, current ltstate "
1452 "is %s\n", dd->ipath_unit,
1454 ipath_ibcstatus_str[
1456 (dd, dd->ipath_kregs->kr_ibcstatus) >>
1457 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1458 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK]);
1459 /* flush all queued sends when going to DOWN or INIT, to be sure that
1460 * they don't block SMA and other MAD packets */
1461 if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT) {
1462 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1463 INFINIPATH_S_ABORT);
1464 ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
1465 (unsigned)(dd->ipath_piobcnt2k +
1466 dd->ipath_piobcnt4k) -
1467 dd->ipath_lastport_piobuf);
1470 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1471 dd->ipath_ibcctrl | which);
1474 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
1480 case IPATH_IB_LINKDOWN:
1481 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_POLL <<
1482 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1487 case IPATH_IB_LINKDOWN_SLEEP:
1488 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_SLEEP <<
1489 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1494 case IPATH_IB_LINKDOWN_DISABLE:
1495 ipath_set_ib_lstate(dd,
1496 INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
1497 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1502 case IPATH_IB_LINKINIT:
1503 if (dd->ipath_flags & IPATH_LINKINIT) {
1507 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_INIT <<
1508 INFINIPATH_IBCC_LINKCMD_SHIFT);
1509 lstate = IPATH_LINKINIT;
1512 case IPATH_IB_LINKARM:
1513 if (dd->ipath_flags & IPATH_LINKARMED) {
1517 if (!(dd->ipath_flags &
1518 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
1522 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED <<
1523 INFINIPATH_IBCC_LINKCMD_SHIFT);
1525 * Since the port can transition to ACTIVE by receiving
1526 * a non VL 15 packet, wait for either state.
1528 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
1531 case IPATH_IB_LINKACTIVE:
1532 if (dd->ipath_flags & IPATH_LINKACTIVE) {
1536 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
1540 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE <<
1541 INFINIPATH_IBCC_LINKCMD_SHIFT);
1542 lstate = IPATH_LINKACTIVE;
1546 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
1550 ret = ipath_wait_linkstate(dd, lstate, 2000);
1557 * ipath_set_mtu - set the MTU
1558 * @dd: the infinipath device
1561 * we can handle "any" incoming size, the issue here is whether we
1562 * need to restrict our outgoing size. For now, we don't do any
1563 * sanity checking on this, and we don't deal with what happens to
1564 * programs that are already running when the size changes.
1565 * NOTE: changing the MTU will usually cause the IBC to go back to
1566 * link initialize (IPATH_IBSTATE_INIT) state...
1568 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
1575 * mtu is IB data payload max. It's the largest power of 2 less
1576 * than piosize (or even larger, since it only really controls the
1577 * largest we can receive; we can send the max of the mtu and
1578 * piosize). We check that it's one of the valid IB sizes.
1580 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
1582 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
1586 if (dd->ipath_ibmtu == arg) {
1587 ret = 0; /* same as current */
1591 piosize = dd->ipath_ibmaxlen;
1592 dd->ipath_ibmtu = arg;
1594 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
1595 /* Only if it's not the initial value (or reset to it) */
1596 if (piosize != dd->ipath_init_ibmaxlen) {
1597 dd->ipath_ibmaxlen = piosize;
1600 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
1601 piosize = arg + IPATH_PIO_MAXIBHDR;
1602 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
1603 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
1605 dd->ipath_ibmaxlen = piosize;
1611 * set the IBC maxpktlength to the size of our pio
1614 u64 ibc = dd->ipath_ibcctrl;
1615 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
1616 INFINIPATH_IBCC_MAXPKTLEN_SHIFT);
1618 piosize = piosize - 2 * sizeof(u32); /* ignore pbc */
1619 dd->ipath_ibmaxlen = piosize;
1620 piosize /= sizeof(u32); /* in words */
1622 * for ICRC, which we only send in diag test pkt mode, and
1623 * we don't need to worry about that for mtu
1627 ibc |= piosize << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1628 dd->ipath_ibcctrl = ibc;
1629 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1631 dd->ipath_f_tidtemplate(dd);
1640 int ipath_set_lid(struct ipath_devdata *dd, u32 arg, u8 lmc)
1642 dd->ipath_lid = arg;
1643 dd->ipath_lmc = lmc;
1649 * ipath_read_kreg64_port - read a device's per-port 64-bit kernel register
1650 * @dd: the infinipath device
1651 * @regno: the register number to read
1652 * @port: the port containing the register
1654 * Registers that vary with the chip implementation constants (port)
1657 u64 ipath_read_kreg64_port(const struct ipath_devdata *dd, ipath_kreg regno,
1662 if (port < dd->ipath_portcnt &&
1663 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
1664 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
1665 where = regno + port;
1669 return ipath_read_kreg64(dd, where);
1673 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
1674 * @dd: the infinipath device
1675 * @regno: the register number to write
1676 * @port: the port containing the register
1677 * @value: the value to write
1679 * Registers that vary with the chip implementation constants (port)
1682 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
1683 unsigned port, u64 value)
1687 if (port < dd->ipath_portcnt &&
1688 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
1689 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
1690 where = regno + port;
1694 ipath_write_kreg(dd, where, value);
1698 * ipath_shutdown_device - shut down a device
1699 * @dd: the infinipath device
1701 * This is called to make the device quiet when we are about to
1702 * unload the driver, and also when the device is administratively
1703 * disabled. It does not free any data structures.
1704 * Everything it does has to be setup again by ipath_init_chip(dd,1)
1706 void ipath_shutdown_device(struct ipath_devdata *dd)
1710 ipath_dbg("Shutting down the device\n");
1712 dd->ipath_flags |= IPATH_LINKUNK;
1713 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
1714 IPATH_LINKINIT | IPATH_LINKARMED |
1716 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
1717 IPATH_STATUS_IB_READY);
1719 /* mask interrupts, but not errors */
1720 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
1722 dd->ipath_rcvctrl = 0;
1723 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1727 * gracefully stop all sends allowing any in progress to trickle out
1730 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0ULL);
1732 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1734 * enough for anything that's going to trickle out to have actually
1740 * abort any armed or launched PIO buffers that didn't go. (self
1741 * clearing). Will cause any packet currently being transmitted to
1742 * go out with an EBP, and may also cause a short packet error on
1745 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1746 INFINIPATH_S_ABORT);
1748 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
1749 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1752 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
1753 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1754 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
1757 * clear SerdesEnable and turn the leds off; do this here because
1758 * we are unloading, so don't count on interrupts to move along
1759 * Turn the LEDs off explictly for the same reason.
1761 dd->ipath_f_quiet_serdes(dd);
1762 dd->ipath_f_setextled(dd, 0, 0);
1764 if (dd->ipath_stats_timer_active) {
1765 del_timer_sync(&dd->ipath_stats_timer);
1766 dd->ipath_stats_timer_active = 0;
1770 * clear all interrupts and errors, so that the next time the driver
1771 * is loaded or device is enabled, we know that whatever is set
1772 * happened while we were unloaded
1774 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1775 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
1776 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
1777 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
1781 * ipath_free_pddata - free a port's allocated data
1782 * @dd: the infinipath device
1783 * @pd: the portdata structure
1785 * free up any allocated data for a port
1786 * This should not touch anything that would affect a simultaneous
1787 * re-allocation of port data, because it is called after ipath_mutex
1788 * is released (and can be called from reinit as well).
1789 * It should never change any chip state, or global driver state.
1790 * (The only exception to global state is freeing the port0 port0_skbs.)
1792 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
1797 if (pd->port_rcvhdrq) {
1798 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
1799 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
1800 (unsigned long) pd->port_rcvhdrq_size);
1801 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
1802 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
1803 pd->port_rcvhdrq = NULL;
1804 if (pd->port_rcvhdrtail_kvaddr) {
1805 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1806 (void *)pd->port_rcvhdrtail_kvaddr,
1807 pd->port_rcvhdrqtailaddr_phys);
1808 pd->port_rcvhdrtail_kvaddr = NULL;
1811 if (pd->port_port && pd->port_rcvegrbuf) {
1814 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
1815 void *base = pd->port_rcvegrbuf[e];
1816 size_t size = pd->port_rcvegrbuf_size;
1818 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
1819 "chunk %u/%u\n", base,
1820 (unsigned long) size,
1821 e, pd->port_rcvegrbuf_chunks);
1822 dma_free_coherent(&dd->pcidev->dev, size,
1823 base, pd->port_rcvegrbuf_phys[e]);
1825 vfree(pd->port_rcvegrbuf);
1826 pd->port_rcvegrbuf = NULL;
1827 vfree(pd->port_rcvegrbuf_phys);
1828 pd->port_rcvegrbuf_phys = NULL;
1829 pd->port_rcvegrbuf_chunks = 0;
1830 } else if (pd->port_port == 0 && dd->ipath_port0_skbs) {
1832 struct sk_buff **skbs = dd->ipath_port0_skbs;
1834 dd->ipath_port0_skbs = NULL;
1835 ipath_cdbg(VERBOSE, "free closed port %d ipath_port0_skbs "
1836 "@ %p\n", pd->port_port, skbs);
1837 for (e = 0; e < dd->ipath_rcvegrcnt; e++)
1839 dev_kfree_skb(skbs[e]);
1842 kfree(pd->port_tid_pg_list);
1846 static int __init infinipath_init(void)
1850 ipath_dbg(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
1853 * These must be called before the driver is registered with
1854 * the PCI subsystem.
1856 idr_init(&unit_table);
1857 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
1862 ret = pci_register_driver(&ipath_driver);
1864 printk(KERN_ERR IPATH_DRV_NAME
1865 ": Unable to register driver: error %d\n", -ret);
1869 ret = ipath_driver_create_group(&ipath_driver.driver);
1871 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create driver "
1872 "sysfs entries: error %d\n", -ret);
1876 ret = ipath_init_ipathfs();
1878 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
1879 "ipathfs: error %d\n", -ret);
1886 ipath_driver_remove_group(&ipath_driver.driver);
1889 pci_unregister_driver(&ipath_driver);
1892 idr_destroy(&unit_table);
1898 static void cleanup_device(struct ipath_devdata *dd)
1902 ipath_shutdown_device(dd);
1904 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
1905 /* can't do anything more with chip; needs re-init */
1906 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
1907 if (dd->ipath_kregbase) {
1909 * if we haven't already cleaned up before these are
1910 * to ensure any register reads/writes "fail" until
1913 dd->ipath_kregbase = NULL;
1914 dd->ipath_uregbase = 0;
1915 dd->ipath_sregbase = 0;
1916 dd->ipath_cregbase = 0;
1917 dd->ipath_kregsize = 0;
1919 ipath_disable_wc(dd);
1922 if (dd->ipath_pioavailregs_dma) {
1923 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1924 (void *) dd->ipath_pioavailregs_dma,
1925 dd->ipath_pioavailregs_phys);
1926 dd->ipath_pioavailregs_dma = NULL;
1928 if (dd->ipath_dummy_hdrq) {
1929 dma_free_coherent(&dd->pcidev->dev,
1930 dd->ipath_pd[0]->port_rcvhdrq_size,
1931 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
1932 dd->ipath_dummy_hdrq = NULL;
1935 if (dd->ipath_pageshadow) {
1936 struct page **tmpp = dd->ipath_pageshadow;
1939 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
1941 for (port = 0; port < dd->ipath_cfgports; port++) {
1942 int port_tidbase = port * dd->ipath_rcvtidcnt;
1943 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
1944 for (i = port_tidbase; i < maxtid; i++) {
1947 ipath_release_user_pages(&tmpp[i], 1);
1953 ipath_stats.sps_pageunlocks += cnt;
1954 ipath_cdbg(VERBOSE, "There were still %u expTID "
1955 "entries locked\n", cnt);
1957 if (ipath_stats.sps_pagelocks ||
1958 ipath_stats.sps_pageunlocks)
1959 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
1960 "unlocked via ipath_m{un}lock\n",
1961 (unsigned long long)
1962 ipath_stats.sps_pagelocks,
1963 (unsigned long long)
1964 ipath_stats.sps_pageunlocks);
1966 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
1967 dd->ipath_pageshadow);
1968 vfree(dd->ipath_pageshadow);
1969 dd->ipath_pageshadow = NULL;
1973 * free any resources still in use (usually just kernel ports)
1974 * at unload; we do for portcnt, not cfgports, because cfgports
1975 * could have changed while we were loaded.
1977 for (port = 0; port < dd->ipath_portcnt; port++) {
1978 struct ipath_portdata *pd = dd->ipath_pd[port];
1979 dd->ipath_pd[port] = NULL;
1980 ipath_free_pddata(dd, pd);
1982 kfree(dd->ipath_pd);
1984 * debuggability, in case some cleanup path tries to use it
1987 dd->ipath_pd = NULL;
1990 static void __exit infinipath_cleanup(void)
1992 struct ipath_devdata *dd, *tmp;
1993 unsigned long flags;
1995 ipath_exit_ipathfs();
1997 ipath_driver_remove_group(&ipath_driver.driver);
1999 spin_lock_irqsave(&ipath_devs_lock, flags);
2002 * turn off rcv, send, and interrupts for all ports, all drivers
2003 * should also hard reset the chip here?
2004 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
2005 * for all versions of the driver, if they were allocated
2007 list_for_each_entry_safe(dd, tmp, &ipath_dev_list, ipath_list) {
2008 spin_unlock_irqrestore(&ipath_devs_lock, flags);
2010 if (dd->ipath_kregbase)
2014 if (dd->pcidev->irq) {
2016 "unit %u free_irq of irq %x\n",
2017 dd->ipath_unit, dd->pcidev->irq);
2018 free_irq(dd->pcidev->irq, dd);
2020 ipath_dbg("irq is 0, not doing free_irq "
2021 "for unit %u\n", dd->ipath_unit);
2024 * we check for NULL here, because it's outside
2025 * the kregbase check, and we need to call it
2026 * after the free_irq. Thus it's possible that
2027 * the function pointers were never initialized.
2029 if (dd->ipath_f_cleanup)
2030 /* clean up chip-specific stuff */
2031 dd->ipath_f_cleanup(dd);
2035 spin_lock_irqsave(&ipath_devs_lock, flags);
2038 spin_unlock_irqrestore(&ipath_devs_lock, flags);
2040 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2041 pci_unregister_driver(&ipath_driver);
2043 idr_destroy(&unit_table);
2047 * ipath_reset_device - reset the chip if possible
2048 * @unit: the device to reset
2050 * Whether or not reset is successful, we attempt to re-initialize the chip
2051 * (that is, much like a driver unload/reload). We clear the INITTED flag
2052 * so that the various entry points will fail until we reinitialize. For
2053 * now, we only allow this if no user ports are open that use chip resources
2055 int ipath_reset_device(int unit)
2058 struct ipath_devdata *dd = ipath_lookup(unit);
2065 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2067 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2068 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2069 "not initialized or not present\n", unit);
2075 for (i = 1; i < dd->ipath_cfgports; i++) {
2076 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2077 ipath_dbg("unit %u port %d is in use "
2078 "(PID %u cmd %s), can't reset\n",
2080 dd->ipath_pd[i]->port_pid,
2081 dd->ipath_pd[i]->port_comm);
2087 dd->ipath_flags &= ~IPATH_INITTED;
2088 ret = dd->ipath_f_reset(dd);
2090 ipath_dbg("reset was not successful\n");
2091 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2093 ret = ipath_init_chip(dd, 1);
2095 ipath_dev_err(dd, "Reinitialize unit %u after "
2096 "reset failed with %d\n", unit, ret);
2098 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2099 "resetting\n", unit);
2105 module_init(infinipath_init);
2106 module_exit(infinipath_cleanup);