2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/sched.h>
35 #include <linux/spinlock.h>
36 #include <linux/idr.h>
37 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <linux/netdevice.h>
41 #include <linux/vmalloc.h>
42 #include <linux/bitmap.h>
43 #include <linux/slab.h>
45 #include "ipath_kernel.h"
46 #include "ipath_verbs.h"
48 static void ipath_update_pio_bufs(struct ipath_devdata *);
50 const char *ipath_get_unit_name(int unit)
52 static char iname[16];
53 snprintf(iname, sizeof iname, "infinipath%u", unit);
57 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
58 #define PFX IPATH_DRV_NAME ": "
61 * The size has to be longer than this string, so we can append
62 * board/chip information to it in the init code.
64 const char ib_ipath_version[] = IPATH_IDSTR "\n";
66 static struct idr unit_table;
67 DEFINE_SPINLOCK(ipath_devs_lock);
68 LIST_HEAD(ipath_dev_list);
70 wait_queue_head_t ipath_state_wait;
72 unsigned ipath_debug = __IPATH_INFO;
74 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
75 MODULE_PARM_DESC(debug, "mask for debug prints");
76 EXPORT_SYMBOL_GPL(ipath_debug);
78 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
79 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
80 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
82 static unsigned ipath_hol_timeout_ms = 13000;
83 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
84 MODULE_PARM_DESC(hol_timeout_ms,
85 "duration of user app suspension after link failure");
87 unsigned ipath_linkrecovery = 1;
88 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
89 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
91 MODULE_LICENSE("GPL");
92 MODULE_AUTHOR("QLogic <support@qlogic.com>");
93 MODULE_DESCRIPTION("QLogic InfiniPath driver");
96 * Table to translate the LINKTRAININGSTATE portion of
97 * IBCStatus to a human-readable form.
99 const char *ipath_ibcstatus_str[] = {
106 "LState6", /* unused */
107 "LState7", /* unused */
113 "CfgTxRevLane", /* unused before IBA7220 */
116 /* below were added for IBA7220 */
120 "CfgWaitCfgEnhanced",
125 "LTState18", "LTState19", "LTState1A", "LTState1B",
126 "LTState1C", "LTState1D", "LTState1E", "LTState1F"
129 static void __devexit ipath_remove_one(struct pci_dev *);
130 static int __devinit ipath_init_one(struct pci_dev *,
131 const struct pci_device_id *);
133 /* Only needed for registration, nothing else needs this info */
134 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
135 #define PCI_VENDOR_ID_QLOGIC 0x1077
136 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
137 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
138 #define PCI_DEVICE_ID_INFINIPATH_7220 0x7220
140 /* Number of seconds before our card status check... */
141 #define STATUS_TIMEOUT 60
143 static const struct pci_device_id ipath_pci_tbl[] = {
144 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
145 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_INFINIPATH_7220) },
150 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
152 static struct pci_driver ipath_driver = {
153 .name = IPATH_DRV_NAME,
154 .probe = ipath_init_one,
155 .remove = __devexit_p(ipath_remove_one),
156 .id_table = ipath_pci_tbl,
158 .groups = ipath_driver_attr_groups,
162 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
163 u32 *bar0, u32 *bar1)
167 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
169 ipath_dev_err(dd, "failed to read bar0 before enable: "
172 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
174 ipath_dev_err(dd, "failed to read bar1 before enable: "
177 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
180 static void ipath_free_devdata(struct pci_dev *pdev,
181 struct ipath_devdata *dd)
185 pci_set_drvdata(pdev, NULL);
187 if (dd->ipath_unit != -1) {
188 spin_lock_irqsave(&ipath_devs_lock, flags);
189 idr_remove(&unit_table, dd->ipath_unit);
190 list_del(&dd->ipath_list);
191 spin_unlock_irqrestore(&ipath_devs_lock, flags);
196 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
199 struct ipath_devdata *dd;
202 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
203 dd = ERR_PTR(-ENOMEM);
207 dd = vmalloc(sizeof(*dd));
209 dd = ERR_PTR(-ENOMEM);
212 memset(dd, 0, sizeof(*dd));
215 spin_lock_irqsave(&ipath_devs_lock, flags);
217 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
219 printk(KERN_ERR IPATH_DRV_NAME
220 ": Could not allocate unit ID: error %d\n", -ret);
221 ipath_free_devdata(pdev, dd);
227 pci_set_drvdata(pdev, dd);
229 list_add(&dd->ipath_list, &ipath_dev_list);
232 spin_unlock_irqrestore(&ipath_devs_lock, flags);
238 static inline struct ipath_devdata *__ipath_lookup(int unit)
240 return idr_find(&unit_table, unit);
243 struct ipath_devdata *ipath_lookup(int unit)
245 struct ipath_devdata *dd;
248 spin_lock_irqsave(&ipath_devs_lock, flags);
249 dd = __ipath_lookup(unit);
250 spin_unlock_irqrestore(&ipath_devs_lock, flags);
255 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
257 int nunits, npresent, nup;
258 struct ipath_devdata *dd;
262 nunits = npresent = nup = maxports = 0;
264 spin_lock_irqsave(&ipath_devs_lock, flags);
266 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
268 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
271 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
274 if (dd->ipath_cfgports > maxports)
275 maxports = dd->ipath_cfgports;
278 spin_unlock_irqrestore(&ipath_devs_lock, flags);
281 *npresentp = npresent;
285 *maxportsp = maxports;
291 * These next two routines are placeholders in case we don't have per-arch
292 * code for controlling write combining. If explicit control of write
293 * combining is not available, performance will probably be awful.
296 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
301 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
306 * Perform a PIO buffer bandwidth write test, to verify proper system
307 * configuration. Even when all the setup calls work, occasionally
308 * BIOS or other issues can prevent write combining from working, or
309 * can cause other bandwidth problems to the chip.
311 * This test simply writes the same buffer over and over again, and
312 * measures close to the peak bandwidth to the chip (not testing
313 * data bandwidth to the wire). On chips that use an address-based
314 * trigger to send packets to the wire, this is easy. On chips that
315 * use a count to trigger, we want to make sure that the packet doesn't
316 * go out on the wire, or trigger flow control checks.
318 static void ipath_verify_pioperf(struct ipath_devdata *dd)
320 u32 pbnum, cnt, lcnt;
325 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
327 dev_info(&dd->pcidev->dev,
328 "No PIObufs for checking perf, skipping\n");
333 * Enough to give us a reasonable test, less than piobuf size, and
334 * likely multiple of store buffer length.
340 dev_info(&dd->pcidev->dev,
341 "Couldn't get memory for checking PIO perf,"
346 preempt_disable(); /* we want reasonably accurate elapsed time */
347 msecs = 1 + jiffies_to_msecs(jiffies);
348 for (lcnt = 0; lcnt < 10000U; lcnt++) {
349 /* wait until we cross msec boundary */
350 if (jiffies_to_msecs(jiffies) >= msecs)
355 ipath_disable_armlaunch(dd);
358 * length 0, no dwords actually sent, and mark as VL15
359 * on chips where that may matter (due to IB flowcontrol)
361 if ((dd->ipath_flags & IPATH_HAS_PBC_CNT))
362 writeq(1UL << 63, piobuf);
368 * this is only roughly accurate, since even with preempt we
369 * still take interrupts that could take a while. Running for
370 * >= 5 msec seems to get us "close enough" to accurate values
372 msecs = jiffies_to_msecs(jiffies);
373 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
374 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
375 emsecs = jiffies_to_msecs(jiffies) - msecs;
378 /* 1 GiB/sec, slightly over IB SDR line rate */
379 if (lcnt < (emsecs * 1024U))
381 "Performance problem: bandwidth to PIO buffers is "
383 lcnt / (u32) emsecs);
385 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
386 lcnt / (u32) emsecs);
393 /* disarm piobuf, so it's available again */
394 ipath_disarm_piobufs(dd, pbnum, 1);
395 ipath_enable_armlaunch(dd);
398 static int __devinit ipath_init_one(struct pci_dev *pdev,
399 const struct pci_device_id *ent)
402 struct ipath_devdata *dd;
403 unsigned long long addr;
404 u32 bar0 = 0, bar1 = 0;
407 dd = ipath_alloc_devdata(pdev);
410 printk(KERN_ERR IPATH_DRV_NAME
411 ": Could not allocate devdata: error %d\n", -ret);
415 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
417 ret = pci_enable_device(pdev);
419 /* This can happen iff:
421 * We did a chip reset, and then failed to reprogram the
422 * BAR, or the chip reset due to an internal error. We then
423 * unloaded the driver and reloaded it.
425 * Both reset cases set the BAR back to initial state. For
426 * the latter case, the AER sticky error bit at offset 0x718
427 * should be set, but the Linux kernel doesn't yet know
428 * about that, it appears. If the original BAR was retained
429 * in the kernel data structures, this may be OK.
431 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
432 dd->ipath_unit, -ret);
435 addr = pci_resource_start(pdev, 0);
436 len = pci_resource_len(pdev, 0);
437 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x "
438 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
439 ent->device, ent->driver_data);
441 read_bars(dd, pdev, &bar0, &bar1);
443 if (!bar1 && !(bar0 & ~0xf)) {
445 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
446 "rewriting as %llx\n", addr);
447 ret = pci_write_config_dword(
448 pdev, PCI_BASE_ADDRESS_0, addr);
450 ipath_dev_err(dd, "rewrite of BAR0 "
451 "failed: err %d\n", -ret);
454 ret = pci_write_config_dword(
455 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
457 ipath_dev_err(dd, "rewrite of BAR1 "
458 "failed: err %d\n", -ret);
462 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
463 "not usable until reboot\n");
469 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
471 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
472 "err %d\n", dd->ipath_unit, -ret);
476 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
479 * if the 64 bit setup fails, try 32 bit. Some systems
480 * do not setup 64 bit maps on systems with 2GB or less
483 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
486 "Unable to set DMA mask for unit %u: %d\n",
487 dd->ipath_unit, ret);
491 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
492 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
495 "Unable to set DMA consistent mask "
497 dd->ipath_unit, ret);
502 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
505 "Unable to set DMA consistent mask "
507 dd->ipath_unit, ret);
510 pci_set_master(pdev);
513 * Save BARs to rewrite after device reset. Save all 64 bits of
516 dd->ipath_pcibar0 = addr;
517 dd->ipath_pcibar1 = addr >> 32;
518 dd->ipath_deviceid = ent->device; /* save for later use */
519 dd->ipath_vendorid = ent->vendor;
521 /* setup the chip-specific functions, as early as possible. */
522 switch (ent->device) {
523 case PCI_DEVICE_ID_INFINIPATH_HT:
525 ipath_init_iba6110_funcs(dd);
528 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
529 "CONFIG_HT_IRQ is not enabled\n", ent->device);
532 case PCI_DEVICE_ID_INFINIPATH_PE800:
533 #ifdef CONFIG_PCI_MSI
534 ipath_init_iba6120_funcs(dd);
537 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
538 "CONFIG_PCI_MSI is not enabled\n", ent->device);
541 case PCI_DEVICE_ID_INFINIPATH_7220:
542 #ifndef CONFIG_PCI_MSI
543 ipath_dbg("CONFIG_PCI_MSI is not enabled, "
544 "using INTx for unit %u\n", dd->ipath_unit);
546 ipath_init_iba7220_funcs(dd);
549 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
550 "failing\n", ent->device);
554 for (j = 0; j < 6; j++) {
555 if (!pdev->resource[j].start)
557 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
558 j, (unsigned long long)pdev->resource[j].start,
559 (unsigned long long)pdev->resource[j].end,
560 (unsigned long long)pci_resource_len(pdev, j));
564 ipath_dev_err(dd, "No valid address in BAR 0!\n");
569 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
571 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
572 "%u: err %d\n", dd->ipath_unit, -ret);
573 goto bail_regions; /* shouldn't ever happen */
575 dd->ipath_pcirev = rev;
577 #if defined(__powerpc__)
578 /* There isn't a generic way to specify writethrough mappings */
579 dd->ipath_kregbase = __ioremap(addr, len,
580 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
582 dd->ipath_kregbase = ioremap_nocache(addr, len);
585 if (!dd->ipath_kregbase) {
586 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
591 dd->ipath_kregend = (u64 __iomem *)
592 ((void __iomem *)dd->ipath_kregbase + len);
593 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
595 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
596 addr, dd->ipath_kregbase);
598 if (dd->ipath_f_bus(dd, pdev))
599 ipath_dev_err(dd, "Failed to setup config space; "
600 "continuing anyway\n");
603 * set up our interrupt handler; IRQF_SHARED probably not needed,
604 * since MSI interrupts shouldn't be shared but won't hurt for now.
605 * check 0 irq after we return from chip-specific bus setup, since
606 * that can affect this due to setup
609 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
612 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
615 ipath_dev_err(dd, "Couldn't setup irq handler, "
616 "irq=%d: %d\n", dd->ipath_irq, ret);
621 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
625 ret = ipath_enable_wc(dd);
628 ipath_dev_err(dd, "Write combining not enabled "
629 "(err %d): performance may be poor\n",
634 ipath_verify_pioperf(dd);
636 ipath_device_create_group(&pdev->dev, dd);
637 ipathfs_add_device(dd);
640 ipath_register_ib_device(dd);
646 free_irq(pdev->irq, dd);
649 iounmap((volatile void __iomem *) dd->ipath_kregbase);
652 pci_release_regions(pdev);
655 pci_disable_device(pdev);
658 ipath_free_devdata(pdev, dd);
664 static void __devexit cleanup_device(struct ipath_devdata *dd)
667 struct ipath_portdata **tmp;
670 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
671 /* can't do anything more with chip; needs re-init */
672 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
673 if (dd->ipath_kregbase) {
675 * if we haven't already cleaned up before these are
676 * to ensure any register reads/writes "fail" until
679 dd->ipath_kregbase = NULL;
680 dd->ipath_uregbase = 0;
681 dd->ipath_sregbase = 0;
682 dd->ipath_cregbase = 0;
683 dd->ipath_kregsize = 0;
685 ipath_disable_wc(dd);
688 if (dd->ipath_spectriggerhit)
689 dev_info(&dd->pcidev->dev, "%lu special trigger hits\n",
690 dd->ipath_spectriggerhit);
692 if (dd->ipath_pioavailregs_dma) {
693 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
694 (void *) dd->ipath_pioavailregs_dma,
695 dd->ipath_pioavailregs_phys);
696 dd->ipath_pioavailregs_dma = NULL;
698 if (dd->ipath_dummy_hdrq) {
699 dma_free_coherent(&dd->pcidev->dev,
700 dd->ipath_pd[0]->port_rcvhdrq_size,
701 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
702 dd->ipath_dummy_hdrq = NULL;
705 if (dd->ipath_pageshadow) {
706 struct page **tmpp = dd->ipath_pageshadow;
707 dma_addr_t *tmpd = dd->ipath_physshadow;
710 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
712 for (port = 0; port < dd->ipath_cfgports; port++) {
713 int port_tidbase = port * dd->ipath_rcvtidcnt;
714 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
715 for (i = port_tidbase; i < maxtid; i++) {
718 pci_unmap_page(dd->pcidev, tmpd[i],
719 PAGE_SIZE, PCI_DMA_FROMDEVICE);
720 ipath_release_user_pages(&tmpp[i], 1);
726 ipath_stats.sps_pageunlocks += cnt;
727 ipath_cdbg(VERBOSE, "There were still %u expTID "
728 "entries locked\n", cnt);
730 if (ipath_stats.sps_pagelocks ||
731 ipath_stats.sps_pageunlocks)
732 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
733 "unlocked via ipath_m{un}lock\n",
735 ipath_stats.sps_pagelocks,
737 ipath_stats.sps_pageunlocks);
739 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
740 dd->ipath_pageshadow);
741 tmpp = dd->ipath_pageshadow;
742 dd->ipath_pageshadow = NULL;
745 dd->ipath_egrtidbase = NULL;
749 * free any resources still in use (usually just kernel ports)
750 * at unload; we do for portcnt, because that's what we allocate.
751 * We acquire lock to be really paranoid that ipath_pd isn't being
752 * accessed from some interrupt-related code (that should not happen,
753 * but best to be sure).
755 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
758 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
759 for (port = 0; port < dd->ipath_portcnt; port++) {
760 struct ipath_portdata *pd = tmp[port];
761 tmp[port] = NULL; /* debugging paranoia */
762 ipath_free_pddata(dd, pd);
767 static void __devexit ipath_remove_one(struct pci_dev *pdev)
769 struct ipath_devdata *dd = pci_get_drvdata(pdev);
771 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
774 * disable the IB link early, to be sure no new packets arrive, which
775 * complicates the shutdown process
777 ipath_shutdown_device(dd);
779 flush_scheduled_work();
782 ipath_unregister_ib_device(dd->verbs_dev);
784 ipath_diag_remove(dd);
785 ipath_user_remove(dd);
786 ipathfs_remove_device(dd);
787 ipath_device_remove_group(&pdev->dev, dd);
789 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
790 "unit %u\n", dd, (u32) dd->ipath_unit);
795 * turn off rcv, send, and interrupts for all ports, all drivers
796 * should also hard reset the chip here?
797 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
798 * for all versions of the driver, if they were allocated
801 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
802 dd->ipath_unit, dd->ipath_irq);
803 dd->ipath_f_free_irq(dd);
805 ipath_dbg("irq is 0, not doing free_irq "
806 "for unit %u\n", dd->ipath_unit);
808 * we check for NULL here, because it's outside
809 * the kregbase check, and we need to call it
810 * after the free_irq. Thus it's possible that
811 * the function pointers were never initialized.
813 if (dd->ipath_f_cleanup)
814 /* clean up chip-specific stuff */
815 dd->ipath_f_cleanup(dd);
817 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
818 iounmap((volatile void __iomem *) dd->ipath_kregbase);
819 pci_release_regions(pdev);
820 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
821 pci_disable_device(pdev);
823 ipath_free_devdata(pdev, dd);
826 /* general driver use */
827 DEFINE_MUTEX(ipath_mutex);
829 static DEFINE_SPINLOCK(ipath_pioavail_lock);
832 * ipath_disarm_piobufs - cancel a range of PIO buffers
833 * @dd: the infinipath device
834 * @first: the first PIO buffer to cancel
835 * @cnt: the number of PIO buffers to cancel
837 * cancel a range of PIO buffers, used when they might be armed, but
838 * not triggered. Used at init to ensure buffer state, and also user
839 * process close, in case it died while writing to a PIO buffer
842 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
845 unsigned i, last = first + cnt;
848 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
849 for (i = first; i < last; i++) {
850 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
852 * The disarm-related bits are write-only, so it
853 * is ok to OR them in with our copy of sendctrl
854 * while we hold the lock.
856 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
857 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
858 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
859 /* can't disarm bufs back-to-back per iba7220 spec */
860 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
861 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
863 /* on some older chips, update may not happen after cancel */
864 ipath_force_pio_avail_update(dd);
868 * ipath_wait_linkstate - wait for an IB link state change to occur
869 * @dd: the infinipath device
870 * @state: the state to wait for
871 * @msecs: the number of milliseconds to wait
873 * wait up to msecs milliseconds for IB link state change to occur for
874 * now, take the easy polling route. Currently used only by
875 * ipath_set_linkstate. Returns 0 if state reached, otherwise
876 * -ETIMEDOUT state can have multiple states set, for any of several
879 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
881 dd->ipath_state_wanted = state;
882 wait_event_interruptible_timeout(ipath_state_wait,
883 (dd->ipath_flags & state),
884 msecs_to_jiffies(msecs));
885 dd->ipath_state_wanted = 0;
887 if (!(dd->ipath_flags & state)) {
889 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
891 /* test INIT ahead of DOWN, both can be set */
892 (state & IPATH_LINKINIT) ? "INIT" :
893 ((state & IPATH_LINKDOWN) ? "DOWN" :
894 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
896 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
897 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
898 (unsigned long long) ipath_read_kreg64(
899 dd, dd->ipath_kregs->kr_ibcctrl),
900 (unsigned long long) val,
901 ipath_ibcstatus_str[val & dd->ibcs_lts_mask]);
903 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
906 static void decode_sdma_errs(struct ipath_devdata *dd, ipath_err_t err,
907 char *buf, size_t blen)
909 static const struct {
913 { INFINIPATH_E_SDMAGENMISMATCH, "SDmaGenMismatch" },
914 { INFINIPATH_E_SDMAOUTOFBOUND, "SDmaOutOfBound" },
915 { INFINIPATH_E_SDMATAILOUTOFBOUND, "SDmaTailOutOfBound" },
916 { INFINIPATH_E_SDMABASE, "SDmaBase" },
917 { INFINIPATH_E_SDMA1STDESC, "SDma1stDesc" },
918 { INFINIPATH_E_SDMARPYTAG, "SDmaRpyTag" },
919 { INFINIPATH_E_SDMADWEN, "SDmaDwEn" },
920 { INFINIPATH_E_SDMAMISSINGDW, "SDmaMissingDw" },
921 { INFINIPATH_E_SDMAUNEXPDATA, "SDmaUnexpData" },
922 { INFINIPATH_E_SDMADESCADDRMISALIGN, "SDmaDescAddrMisalign" },
923 { INFINIPATH_E_SENDBUFMISUSE, "SendBufMisuse" },
924 { INFINIPATH_E_SDMADISABLED, "SDmaDisabled" },
930 for (i = 0; i < ARRAY_SIZE(errs); i++) {
931 expected = (errs[i].err != INFINIPATH_E_SDMADISABLED) ? 0 :
932 test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status);
933 if ((err & errs[i].err) && !expected)
934 bidx += snprintf(buf + bidx, blen - bidx,
940 * Decode the error status into strings, deciding whether to always
941 * print * it or not depending on "normal packet errors" vs everything
942 * else. Return 1 if "real" errors, otherwise 0 if only packet
943 * errors, so caller can decide what to print with the string.
945 int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen,
950 if (err & INFINIPATH_E_PKTERRS) {
951 if (!(err & ~INFINIPATH_E_PKTERRS))
952 iserr = 0; // if only packet errors.
953 if (ipath_debug & __IPATH_ERRPKTDBG) {
954 if (err & INFINIPATH_E_REBP)
955 strlcat(buf, "EBP ", blen);
956 if (err & INFINIPATH_E_RVCRC)
957 strlcat(buf, "VCRC ", blen);
958 if (err & INFINIPATH_E_RICRC) {
959 strlcat(buf, "CRC ", blen);
960 // clear for check below, so only once
961 err &= INFINIPATH_E_RICRC;
963 if (err & INFINIPATH_E_RSHORTPKTLEN)
964 strlcat(buf, "rshortpktlen ", blen);
965 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
966 strlcat(buf, "sdroppeddatapkt ", blen);
967 if (err & INFINIPATH_E_SPKTLEN)
968 strlcat(buf, "spktlen ", blen);
970 if ((err & INFINIPATH_E_RICRC) &&
971 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
972 strlcat(buf, "CRC ", blen);
976 if (err & INFINIPATH_E_RHDRLEN)
977 strlcat(buf, "rhdrlen ", blen);
978 if (err & INFINIPATH_E_RBADTID)
979 strlcat(buf, "rbadtid ", blen);
980 if (err & INFINIPATH_E_RBADVERSION)
981 strlcat(buf, "rbadversion ", blen);
982 if (err & INFINIPATH_E_RHDR)
983 strlcat(buf, "rhdr ", blen);
984 if (err & INFINIPATH_E_SENDSPECIALTRIGGER)
985 strlcat(buf, "sendspecialtrigger ", blen);
986 if (err & INFINIPATH_E_RLONGPKTLEN)
987 strlcat(buf, "rlongpktlen ", blen);
988 if (err & INFINIPATH_E_RMAXPKTLEN)
989 strlcat(buf, "rmaxpktlen ", blen);
990 if (err & INFINIPATH_E_RMINPKTLEN)
991 strlcat(buf, "rminpktlen ", blen);
992 if (err & INFINIPATH_E_SMINPKTLEN)
993 strlcat(buf, "sminpktlen ", blen);
994 if (err & INFINIPATH_E_RFORMATERR)
995 strlcat(buf, "rformaterr ", blen);
996 if (err & INFINIPATH_E_RUNSUPVL)
997 strlcat(buf, "runsupvl ", blen);
998 if (err & INFINIPATH_E_RUNEXPCHAR)
999 strlcat(buf, "runexpchar ", blen);
1000 if (err & INFINIPATH_E_RIBFLOW)
1001 strlcat(buf, "ribflow ", blen);
1002 if (err & INFINIPATH_E_SUNDERRUN)
1003 strlcat(buf, "sunderrun ", blen);
1004 if (err & INFINIPATH_E_SPIOARMLAUNCH)
1005 strlcat(buf, "spioarmlaunch ", blen);
1006 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
1007 strlcat(buf, "sunexperrpktnum ", blen);
1008 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
1009 strlcat(buf, "sdroppedsmppkt ", blen);
1010 if (err & INFINIPATH_E_SMAXPKTLEN)
1011 strlcat(buf, "smaxpktlen ", blen);
1012 if (err & INFINIPATH_E_SUNSUPVL)
1013 strlcat(buf, "sunsupVL ", blen);
1014 if (err & INFINIPATH_E_INVALIDADDR)
1015 strlcat(buf, "invalidaddr ", blen);
1016 if (err & INFINIPATH_E_RRCVEGRFULL)
1017 strlcat(buf, "rcvegrfull ", blen);
1018 if (err & INFINIPATH_E_RRCVHDRFULL)
1019 strlcat(buf, "rcvhdrfull ", blen);
1020 if (err & INFINIPATH_E_IBSTATUSCHANGED)
1021 strlcat(buf, "ibcstatuschg ", blen);
1022 if (err & INFINIPATH_E_RIBLOSTLINK)
1023 strlcat(buf, "riblostlink ", blen);
1024 if (err & INFINIPATH_E_HARDWARE)
1025 strlcat(buf, "hardware ", blen);
1026 if (err & INFINIPATH_E_RESET)
1027 strlcat(buf, "reset ", blen);
1028 if (err & INFINIPATH_E_SDMAERRS)
1029 decode_sdma_errs(dd, err, buf, blen);
1030 if (err & INFINIPATH_E_INVALIDEEPCMD)
1031 strlcat(buf, "invalideepromcmd ", blen);
1037 * get_rhf_errstring - decode RHF errors
1038 * @err: the err number
1039 * @msg: the output buffer
1040 * @len: the length of the output buffer
1042 * only used one place now, may want more later
1044 static void get_rhf_errstring(u32 err, char *msg, size_t len)
1046 /* if no errors, and so don't need to check what's first */
1049 if (err & INFINIPATH_RHF_H_ICRCERR)
1050 strlcat(msg, "icrcerr ", len);
1051 if (err & INFINIPATH_RHF_H_VCRCERR)
1052 strlcat(msg, "vcrcerr ", len);
1053 if (err & INFINIPATH_RHF_H_PARITYERR)
1054 strlcat(msg, "parityerr ", len);
1055 if (err & INFINIPATH_RHF_H_LENERR)
1056 strlcat(msg, "lenerr ", len);
1057 if (err & INFINIPATH_RHF_H_MTUERR)
1058 strlcat(msg, "mtuerr ", len);
1059 if (err & INFINIPATH_RHF_H_IHDRERR)
1060 /* infinipath hdr checksum error */
1061 strlcat(msg, "ipathhdrerr ", len);
1062 if (err & INFINIPATH_RHF_H_TIDERR)
1063 strlcat(msg, "tiderr ", len);
1064 if (err & INFINIPATH_RHF_H_MKERR)
1065 /* bad port, offset, etc. */
1066 strlcat(msg, "invalid ipathhdr ", len);
1067 if (err & INFINIPATH_RHF_H_IBERR)
1068 strlcat(msg, "iberr ", len);
1069 if (err & INFINIPATH_RHF_L_SWA)
1070 strlcat(msg, "swA ", len);
1071 if (err & INFINIPATH_RHF_L_SWB)
1072 strlcat(msg, "swB ", len);
1076 * ipath_get_egrbuf - get an eager buffer
1077 * @dd: the infinipath device
1078 * @bufnum: the eager buffer to get
1080 * must only be called if ipath_pd[port] is known to be allocated
1082 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1084 return dd->ipath_port0_skbinfo ?
1085 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1089 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1090 * @dd: the infinipath device
1091 * @gfp_mask: the sk_buff SFP mask
1093 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1096 struct sk_buff *skb;
1100 * Only fully supported way to handle this is to allocate lots
1101 * extra, align as needed, and then do skb_reserve(). That wastes
1102 * a lot of memory... I'll have to hack this into infinipath_copy
1107 * We need 2 extra bytes for ipath_ether data sent in the
1108 * key header. In order to keep everything dword aligned,
1109 * we'll reserve 4 bytes.
1111 len = dd->ipath_ibmaxlen + 4;
1113 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1114 /* We need a 2KB multiple alignment, and there is no way
1115 * to do it except to allocate extra and then skb_reserve
1116 * enough to bring it up to the right alignment.
1121 skb = __dev_alloc_skb(len, gfp_mask);
1123 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1128 skb_reserve(skb, 4);
1130 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1131 u32 una = (unsigned long)skb->data & 2047;
1133 skb_reserve(skb, 2048 - una);
1140 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1145 struct ipath_message_header *hdr)
1149 get_rhf_errstring(eflags, emsg, sizeof emsg);
1150 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1151 "tlen=%x opcode=%x egridx=%x: %s\n",
1153 ipath_hdrget_rcv_type(rhf_addr),
1154 ipath_hdrget_length_in_bytes(rhf_addr),
1155 be32_to_cpu(hdr->bth[0]) >> 24,
1158 /* Count local link integrity errors. */
1159 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1160 u8 n = (dd->ipath_ibcctrl >>
1161 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1162 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1164 if (++dd->ipath_lli_counter > n) {
1165 dd->ipath_lli_counter = 0;
1166 dd->ipath_lli_errors++;
1172 * ipath_kreceive - receive a packet
1173 * @pd: the infinipath port
1175 * called from interrupt handler for errors or receive interrupt
1177 void ipath_kreceive(struct ipath_portdata *pd)
1179 struct ipath_devdata *dd = pd->port_dd;
1182 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1183 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1184 u32 etail = -1, l, hdrqtail;
1185 struct ipath_message_header *hdr;
1186 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1187 static u64 totcalls; /* stats, may eventually remove */
1191 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1192 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1193 u32 seq = ipath_hdrget_seq(rhf_addr);
1195 if (seq != pd->port_seq_cnt)
1199 hdrqtail = ipath_get_rcvhdrtail(pd);
1206 for (last = 0, i = 1; !last; i += !last) {
1207 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1208 eflags = ipath_hdrget_err_flags(rhf_addr);
1209 etype = ipath_hdrget_rcv_type(rhf_addr);
1211 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1213 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1214 ipath_hdrget_use_egr_buf(rhf_addr) :
1215 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1217 * It turns out that the chip uses an eager buffer
1218 * for all non-expected packets, whether it "needs"
1219 * one or not. So always get the index, but don't
1220 * set ebuf (so we try to copy data) unless the
1221 * length requires it.
1223 etail = ipath_hdrget_index(rhf_addr);
1225 if (tlen > sizeof(*hdr) ||
1226 etype == RCVHQ_RCV_TYPE_NON_KD)
1227 ebuf = ipath_get_egrbuf(dd, etail);
1231 * both tiderr and ipathhdrerr are set for all plain IB
1232 * packets; only ipathhdrerr should be set.
1235 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1236 etype != RCVHQ_RCV_TYPE_ERROR &&
1237 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1239 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1242 if (unlikely(eflags))
1243 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1244 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1245 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1246 if (dd->ipath_lli_counter)
1247 dd->ipath_lli_counter--;
1248 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1249 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1250 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1251 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1252 "qp=%x), len %x; ignored\n",
1253 etype, opcode, qp, tlen);
1255 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1256 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1257 be32_to_cpu(hdr->bth[0]) >> 24);
1260 * error packet, type of error unknown.
1261 * Probably type 3, but we don't know, so don't
1262 * even try to print the opcode, etc.
1263 * Usually caused by a "bad packet", that has no
1264 * BTH, when the LRH says it should.
1266 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1267 " %x, len %x hdrq+%x rhf: %Lx\n",
1268 etail, tlen, l, (unsigned long long)
1269 le64_to_cpu(*(__le64 *) rhf_addr));
1270 if (ipath_debug & __IPATH_ERRPKTDBG) {
1271 u32 j, *d, dw = rsize-2;
1272 if (rsize > (tlen>>2))
1275 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1277 for (j = 0; j < dw; j++)
1278 printk(KERN_DEBUG "%8x%s", d[j],
1279 (j%8) == 7 ? "\n" : " ");
1280 printk(KERN_DEBUG ".\n");
1286 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1287 l + dd->ipath_rhf_offset;
1288 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1289 u32 seq = ipath_hdrget_seq(rhf_addr);
1291 if (++pd->port_seq_cnt > 13)
1292 pd->port_seq_cnt = 1;
1293 if (seq != pd->port_seq_cnt)
1295 } else if (l == hdrqtail)
1298 * update head regs on last packet, and every 16 packets.
1299 * Reduce bus traffic, while still trying to prevent
1300 * rcvhdrq overflows, for when the queue is nearly full
1302 if (last || !(i & 0xf)) {
1305 /* request IBA6120 and 7220 interrupt only on last */
1307 lval |= dd->ipath_rhdrhead_intr_off;
1308 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1311 ipath_write_ureg(dd, ur_rcvegrindexhead,
1312 etail, pd->port_port);
1318 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1319 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1320 /* IBA6110 workaround; we can have a race clearing chip
1321 * interrupt with another interrupt about to be delivered,
1322 * and can clear it before it is delivered on the GPIO
1323 * workaround. By doing the extra check here for the
1324 * in-memory tail register updating while we were doing
1325 * earlier packets, we "almost" guarantee we have covered
1328 u32 hqtail = ipath_get_rcvhdrtail(pd);
1329 if (hqtail != hdrqtail) {
1331 reloop = 1; /* loop 1 extra time at most */
1340 if (pkttot > ipath_stats.sps_maxpkts_call)
1341 ipath_stats.sps_maxpkts_call = pkttot;
1342 ipath_stats.sps_port0pkts += pkttot;
1343 ipath_stats.sps_avgpkts_call =
1344 ipath_stats.sps_port0pkts / ++totcalls;
1350 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1351 * @dd: the infinipath device
1353 * called whenever our local copy indicates we have run out of send buffers
1354 * NOTE: This can be called from interrupt context by some code
1355 * and from non-interrupt context by ipath_getpiobuf().
1358 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1360 unsigned long flags;
1362 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1364 /* If the generation (check) bits have changed, then we update the
1365 * busy bit for the corresponding PIO buffer. This algorithm will
1366 * modify positions to the value they already have in some cases
1367 * (i.e., no change), but it's faster than changing only the bits
1368 * that have changed.
1370 * We would like to do this atomicly, to avoid spinlocks in the
1371 * critical send path, but that's not really possible, given the
1372 * type of changes, and that this routine could be called on
1373 * multiple cpu's simultaneously, so we lock in this routine only,
1374 * to avoid conflicting updates; all we change is the shadow, and
1375 * it's a single 64 bit memory location, so by definition the update
1376 * is atomic in terms of what other cpu's can see in testing the
1377 * bits. The spin_lock overhead isn't too bad, since it only
1378 * happens when all buffers are in use, so only cpu overhead, not
1379 * latency or bandwidth is affected.
1381 if (!dd->ipath_pioavailregs_dma) {
1382 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1385 if (ipath_debug & __IPATH_VERBDBG) {
1386 /* only if packet debug and verbose */
1387 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1388 unsigned long *shadow = dd->ipath_pioavailshadow;
1390 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1391 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1393 (unsigned long long) le64_to_cpu(dma[0]),
1395 (unsigned long long) le64_to_cpu(dma[1]),
1397 (unsigned long long) le64_to_cpu(dma[2]),
1399 (unsigned long long) le64_to_cpu(dma[3]),
1403 PKT, "2nd group, dma4=%llx shad4=%lx, "
1404 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1406 (unsigned long long) le64_to_cpu(dma[4]),
1408 (unsigned long long) le64_to_cpu(dma[5]),
1410 (unsigned long long) le64_to_cpu(dma[6]),
1412 (unsigned long long) le64_to_cpu(dma[7]),
1415 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1416 for (i = 0; i < piobregs; i++) {
1417 u64 pchbusy, pchg, piov, pnew;
1419 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1421 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1422 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1424 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1425 pchg = dd->ipath_pioavailkernel[i] &
1426 ~(dd->ipath_pioavailshadow[i] ^ piov);
1427 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1428 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1429 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1430 pnew |= piov & pchbusy;
1431 dd->ipath_pioavailshadow[i] = pnew;
1434 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1438 * used to force update of pioavailshadow if we can't get a pio buffer.
1439 * Needed primarily due to exitting freeze mode after recovering
1440 * from errors. Done lazily, because it's safer (known to not
1441 * be writing pio buffers).
1443 static void ipath_reset_availshadow(struct ipath_devdata *dd)
1446 unsigned long flags;
1448 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1449 for (i = 0; i < dd->ipath_pioavregs; i++) {
1451 /* deal with 6110 chip bug on high register #s */
1452 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1454 val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]);
1456 * busy out the buffers not in the kernel avail list,
1457 * without changing the generation bits.
1459 oldval = dd->ipath_pioavailshadow[i];
1460 dd->ipath_pioavailshadow[i] = val |
1461 ((~dd->ipath_pioavailkernel[i] <<
1462 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) &
1463 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
1464 if (oldval != dd->ipath_pioavailshadow[i])
1465 ipath_dbg("shadow[%d] was %Lx, now %lx\n",
1466 i, (unsigned long long) oldval,
1467 dd->ipath_pioavailshadow[i]);
1469 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1473 * ipath_setrcvhdrsize - set the receive header size
1474 * @dd: the infinipath device
1475 * @rhdrsize: the receive header size
1477 * called from user init code, and also layered driver init
1479 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1483 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1484 if (dd->ipath_rcvhdrsize != rhdrsize) {
1485 dev_info(&dd->pcidev->dev,
1486 "Error: can't set protocol header "
1487 "size %u, already %u\n",
1488 rhdrsize, dd->ipath_rcvhdrsize);
1491 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1492 "size %u\n", dd->ipath_rcvhdrsize);
1493 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1494 (sizeof(u64) / sizeof(u32)))) {
1495 ipath_dbg("Error: can't set protocol header size %u "
1496 "(> max %u)\n", rhdrsize,
1497 dd->ipath_rcvhdrentsize -
1498 (u32) (sizeof(u64) / sizeof(u32)));
1501 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1502 dd->ipath_rcvhdrsize = rhdrsize;
1503 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1504 dd->ipath_rcvhdrsize);
1505 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1506 dd->ipath_rcvhdrsize);
1512 * debugging code and stats updates if no pio buffers available.
1514 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1516 unsigned long *shadow = dd->ipath_pioavailshadow;
1517 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1519 dd->ipath_upd_pio_shadow = 1;
1522 * not atomic, but if we lose a stat count in a while, that's OK
1524 ipath_stats.sps_nopiobufs++;
1525 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1526 ipath_force_pio_avail_update(dd); /* at start */
1527 ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: "
1528 "%llx %llx %llx %llx\n"
1529 "ipath shadow: %lx %lx %lx %lx\n",
1530 dd->ipath_consec_nopiobuf,
1531 (unsigned long)get_cycles(),
1532 (unsigned long long) le64_to_cpu(dma[0]),
1533 (unsigned long long) le64_to_cpu(dma[1]),
1534 (unsigned long long) le64_to_cpu(dma[2]),
1535 (unsigned long long) le64_to_cpu(dma[3]),
1536 shadow[0], shadow[1], shadow[2], shadow[3]);
1538 * 4 buffers per byte, 4 registers above, cover rest
1541 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1542 (sizeof(shadow[0]) * 4 * 4))
1543 ipath_dbg("2nd group: dmacopy: "
1544 "%llx %llx %llx %llx\n"
1545 "ipath shadow: %lx %lx %lx %lx\n",
1546 (unsigned long long)le64_to_cpu(dma[4]),
1547 (unsigned long long)le64_to_cpu(dma[5]),
1548 (unsigned long long)le64_to_cpu(dma[6]),
1549 (unsigned long long)le64_to_cpu(dma[7]),
1550 shadow[4], shadow[5], shadow[6], shadow[7]);
1552 /* at end, so update likely happened */
1553 ipath_reset_availshadow(dd);
1558 * common code for normal driver pio buffer allocation, and reserved
1561 * do appropriate marking as busy, etc.
1562 * returns buffer number if one found (>=0), negative number is error.
1564 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1565 u32 *pbufnum, u32 first, u32 last, u32 firsti)
1567 int i, j, updated = 0;
1569 unsigned long flags;
1570 unsigned long *shadow = dd->ipath_pioavailshadow;
1573 piobcnt = last - first;
1574 if (dd->ipath_upd_pio_shadow) {
1576 * Minor optimization. If we had no buffers on last call,
1577 * start out by doing the update; continue and do scan even
1578 * if no buffers were updated, to be paranoid
1580 ipath_update_pio_bufs(dd);
1587 * while test_and_set_bit() is atomic, we do that and then the
1588 * change_bit(), and the pair is not. See if this is the cause
1589 * of the remaining armlaunch errors.
1591 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1592 for (j = 0; j < piobcnt; j++, i++) {
1595 if (__test_and_set_bit((2 * i) + 1, shadow))
1597 /* flip generation bit */
1598 __change_bit(2 * i, shadow);
1601 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1606 * first time through; shadow exhausted, but may be
1607 * buffers available, try an update and then rescan.
1609 ipath_update_pio_bufs(dd);
1613 } else if (updated == 1 && piobcnt <=
1614 ((dd->ipath_sendctrl
1615 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1616 INFINIPATH_S_UPDTHRESH_MASK)) {
1618 * for chips supporting and using the update
1619 * threshold we need to force an update of the
1620 * in-memory copy if the count is less than the
1621 * thershold, then check one more time.
1623 ipath_force_pio_avail_update(dd);
1624 ipath_update_pio_bufs(dd);
1633 if (i < dd->ipath_piobcnt2k)
1634 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1635 i * dd->ipath_palign);
1637 buf = (u32 __iomem *)
1638 (dd->ipath_pio4kbase +
1639 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1648 * ipath_getpiobuf - find an available pio buffer
1649 * @dd: the infinipath device
1650 * @plen: the size of the PIO buffer needed in 32-bit words
1651 * @pbufnum: the buffer number is placed here
1653 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1659 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1660 first = dd->ipath_piobcnt2k;
1661 lasti = dd->ipath_lastpioindexl;
1664 lasti = dd->ipath_lastpioindex;
1666 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1667 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1671 * Set next starting place. It's just an optimization,
1672 * it doesn't matter who wins on this, so no locking
1674 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1675 dd->ipath_lastpioindexl = pnum + 1;
1677 dd->ipath_lastpioindex = pnum + 1;
1678 if (dd->ipath_upd_pio_shadow)
1679 dd->ipath_upd_pio_shadow = 0;
1680 if (dd->ipath_consec_nopiobuf)
1681 dd->ipath_consec_nopiobuf = 0;
1682 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1683 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1692 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1693 * @dd: the infinipath device
1694 * @start: the starting send buffer number
1695 * @len: the number of send buffers
1696 * @avail: true if the buffers are available for kernel use, false otherwise
1698 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1699 unsigned len, int avail)
1701 unsigned long flags;
1702 unsigned end, cnt = 0;
1704 /* There are two bits per send buffer (busy and generation) */
1706 end = start + len * 2;
1708 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1709 /* Set or clear the busy bit in the shadow. */
1710 while (start < end) {
1715 * the BUSY bit will never be set, because we disarm
1716 * the user buffers before we hand them back to the
1717 * kernel. We do have to make sure the generation
1718 * bit is set correctly in shadow, since it could
1719 * have changed many times while allocated to user.
1720 * We can't use the bitmap functions on the full
1721 * dma array because it is always little-endian, so
1722 * we have to flip to host-order first.
1723 * BITS_PER_LONG is slightly wrong, since it's
1724 * always 64 bits per register in chip...
1725 * We only work on 64 bit kernels, so that's OK.
1727 /* deal with 6110 chip bug on high register #s */
1728 i = start / BITS_PER_LONG;
1729 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1731 __clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
1732 + start, dd->ipath_pioavailshadow);
1733 dma = (unsigned long) le64_to_cpu(
1734 dd->ipath_pioavailregs_dma[im]);
1735 if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1736 + start) % BITS_PER_LONG, &dma))
1737 __set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1738 + start, dd->ipath_pioavailshadow);
1740 __clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1741 + start, dd->ipath_pioavailshadow);
1742 __set_bit(start, dd->ipath_pioavailkernel);
1744 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1745 dd->ipath_pioavailshadow);
1746 __clear_bit(start, dd->ipath_pioavailkernel);
1751 if (dd->ipath_pioupd_thresh) {
1752 end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1753 cnt = bitmap_weight(dd->ipath_pioavailkernel, end);
1755 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1758 * When moving buffers from kernel to user, if number assigned to
1759 * the user is less than the pio update threshold, and threshold
1760 * is supported (cnt was computed > 0), drop the update threshold
1761 * so we update at least once per allocated number of buffers.
1762 * In any case, if the kernel buffers are less than the threshold,
1763 * drop the threshold. We don't bother increasing it, having once
1764 * decreased it, since it would typically just cycle back and forth.
1765 * If we don't decrease below buffers in use, we can wait a long
1766 * time for an update, until some other context uses PIO buffers.
1768 if (!avail && len < cnt)
1770 if (cnt < dd->ipath_pioupd_thresh) {
1771 dd->ipath_pioupd_thresh = cnt;
1772 ipath_dbg("Decreased pio update threshold to %u\n",
1773 dd->ipath_pioupd_thresh);
1774 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1775 dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
1776 << INFINIPATH_S_UPDTHRESH_SHIFT);
1777 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
1778 << INFINIPATH_S_UPDTHRESH_SHIFT;
1779 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1780 dd->ipath_sendctrl);
1781 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1786 * ipath_create_rcvhdrq - create a receive header queue
1787 * @dd: the infinipath device
1788 * @pd: the port data
1790 * this must be contiguous memory (from an i/o perspective), and must be
1791 * DMA'able (which means for some systems, it will go through an IOMMU,
1792 * or be forced into a low address range).
1794 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1795 struct ipath_portdata *pd)
1799 if (!pd->port_rcvhdrq) {
1800 dma_addr_t phys_hdrqtail;
1801 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1802 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1803 sizeof(u32), PAGE_SIZE);
1805 pd->port_rcvhdrq = dma_alloc_coherent(
1806 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1809 if (!pd->port_rcvhdrq) {
1810 ipath_dev_err(dd, "attempt to allocate %d bytes "
1811 "for port %u rcvhdrq failed\n",
1812 amt, pd->port_port);
1817 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1818 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1819 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1821 if (!pd->port_rcvhdrtail_kvaddr) {
1822 ipath_dev_err(dd, "attempt to allocate 1 page "
1823 "for port %u rcvhdrqtailaddr "
1824 "failed\n", pd->port_port);
1826 dma_free_coherent(&dd->pcidev->dev, amt,
1828 pd->port_rcvhdrq_phys);
1829 pd->port_rcvhdrq = NULL;
1832 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1833 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1834 "physical\n", pd->port_port,
1835 (unsigned long long) phys_hdrqtail);
1838 pd->port_rcvhdrq_size = amt;
1840 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1841 "for port %u rcvhdr Q\n",
1842 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1843 (unsigned long) pd->port_rcvhdrq_phys,
1844 (unsigned long) pd->port_rcvhdrq_size,
1848 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1849 "hdrtailaddr@%p %llx physical\n",
1850 pd->port_port, pd->port_rcvhdrq,
1851 (unsigned long long) pd->port_rcvhdrq_phys,
1852 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1853 pd->port_rcvhdrqtailaddr_phys);
1855 /* clear for security and sanity on each use */
1856 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1857 if (pd->port_rcvhdrtail_kvaddr)
1858 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1861 * tell chip each time we init it, even if we are re-using previous
1862 * memory (we zero the register at process close)
1864 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1865 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1866 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1867 pd->port_port, pd->port_rcvhdrq_phys);
1875 * Flush all sends that might be in the ready to send state, as well as any
1876 * that are in the process of being sent. Used whenever we need to be
1877 * sure the send side is idle. Cleans up all buffer state by canceling
1878 * all pio buffers, and issuing an abort, which cleans up anything in the
1879 * launch fifo. The cancel is superfluous on some chip versions, but
1880 * it's safer to always do it.
1881 * PIOAvail bits are updated by the chip as if normal send had happened.
1883 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1885 unsigned long flags;
1887 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
1888 ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n");
1892 * If we have SDMA, and it's not disabled, we have to kick off the
1893 * abort state machine, provided we aren't already aborting.
1894 * If we are in the process of aborting SDMA (!DISABLED, but ABORTING),
1895 * we skip the rest of this routine. It is already "in progress"
1897 if (dd->ipath_flags & IPATH_HAS_SEND_DMA) {
1899 unsigned long *statp = &dd->ipath_sdma_status;
1901 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1903 test_and_set_bit(IPATH_SDMA_ABORTING, statp)
1904 && !test_bit(IPATH_SDMA_DISABLED, statp);
1905 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1910 ipath_dbg("Cancelling all in-progress send buffers\n");
1912 /* skip armlaunch errs for a while */
1913 dd->ipath_lastcancel = jiffies + HZ / 2;
1916 * The abort bit is auto-clearing. We also don't want pioavail
1917 * update happening during this, and we don't want any other
1918 * sends going out, so turn those off for the duration. We read
1919 * the scratch register to be sure that cancels and the abort
1920 * have taken effect in the chip. Otherwise two parts are same
1921 * as ipath_force_pio_avail_update()
1923 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1924 dd->ipath_sendctrl &= ~(INFINIPATH_S_PIOBUFAVAILUPD
1925 | INFINIPATH_S_PIOENABLE);
1926 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1927 dd->ipath_sendctrl | INFINIPATH_S_ABORT);
1928 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1929 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1931 /* disarm all send buffers */
1932 ipath_disarm_piobufs(dd, 0,
1933 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1935 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1936 set_bit(IPATH_SDMA_DISARMED, &dd->ipath_sdma_status);
1938 if (restore_sendctrl) {
1939 /* else done by caller later if needed */
1940 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1941 dd->ipath_sendctrl |= INFINIPATH_S_PIOBUFAVAILUPD |
1942 INFINIPATH_S_PIOENABLE;
1943 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1944 dd->ipath_sendctrl);
1945 /* and again, be sure all have hit the chip */
1946 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1947 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1950 if ((dd->ipath_flags & IPATH_HAS_SEND_DMA) &&
1951 !test_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status) &&
1952 test_bit(IPATH_SDMA_RUNNING, &dd->ipath_sdma_status)) {
1953 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1954 /* only wait so long for intr */
1955 dd->ipath_sdma_abort_intr_timeout = jiffies + HZ;
1956 dd->ipath_sdma_reset_wait = 200;
1957 if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
1958 tasklet_hi_schedule(&dd->ipath_sdma_abort_task);
1959 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1965 * Force an update of in-memory copy of the pioavail registers, when
1966 * needed for any of a variety of reasons. We read the scratch register
1967 * to make it highly likely that the update will have happened by the
1968 * time we return. If already off (as in cancel_sends above), this
1969 * routine is a nop, on the assumption that the caller will "do the
1972 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1974 unsigned long flags;
1976 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1977 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1978 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1979 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1980 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1981 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1982 dd->ipath_sendctrl);
1983 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1985 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1988 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1992 static const char *what[4] = {
1994 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1995 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1996 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1999 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
2001 * If we are told to disable, note that so link-recovery
2002 * code does not attempt to bring us back up.
2005 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
2007 } else if (linitcmd) {
2009 * Any other linkinitcmd will lead to LINKDOWN and then
2010 * to INIT (if all is well), so clear flag to let
2011 * link-recovery code attempt to bring us back up.
2014 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
2018 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
2019 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
2021 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
2022 dd->ipath_unit, what[linkcmd], linitcmd,
2023 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
2024 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
2026 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2027 dd->ipath_ibcctrl | mod_wd);
2028 /* read from chip so write is flushed */
2029 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2032 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
2038 case IPATH_IB_LINKDOWN_ONLY:
2039 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
2044 case IPATH_IB_LINKDOWN:
2045 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2046 INFINIPATH_IBCC_LINKINITCMD_POLL);
2051 case IPATH_IB_LINKDOWN_SLEEP:
2052 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2053 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
2058 case IPATH_IB_LINKDOWN_DISABLE:
2059 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2060 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2065 case IPATH_IB_LINKARM:
2066 if (dd->ipath_flags & IPATH_LINKARMED) {
2070 if (!(dd->ipath_flags &
2071 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
2075 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
2078 * Since the port can transition to ACTIVE by receiving
2079 * a non VL 15 packet, wait for either state.
2081 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
2084 case IPATH_IB_LINKACTIVE:
2085 if (dd->ipath_flags & IPATH_LINKACTIVE) {
2089 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
2093 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
2094 lstate = IPATH_LINKACTIVE;
2097 case IPATH_IB_LINK_LOOPBACK:
2098 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
2099 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
2100 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2103 /* turn heartbeat off, as it causes loopback to fail */
2104 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2105 IPATH_IB_HRTBT_OFF);
2110 case IPATH_IB_LINK_EXTERNAL:
2111 dev_info(&dd->pcidev->dev,
2112 "Disabling IB local loopback (normal)\n");
2113 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2115 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
2116 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2123 * Heartbeat can be explicitly enabled by the user via
2124 * "hrtbt_enable" "file", and if disabled, trying to enable here
2125 * will have no effect. Implicit changes (heartbeat off when
2126 * loopback on, and vice versa) are included to ease testing.
2128 case IPATH_IB_LINK_HRTBT:
2129 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2133 case IPATH_IB_LINK_NO_HRTBT:
2134 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2135 IPATH_IB_HRTBT_OFF);
2139 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
2143 ret = ipath_wait_linkstate(dd, lstate, 2000);
2150 * ipath_set_mtu - set the MTU
2151 * @dd: the infinipath device
2154 * we can handle "any" incoming size, the issue here is whether we
2155 * need to restrict our outgoing size. For now, we don't do any
2156 * sanity checking on this, and we don't deal with what happens to
2157 * programs that are already running when the size changes.
2158 * NOTE: changing the MTU will usually cause the IBC to go back to
2159 * link INIT state...
2161 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
2168 * mtu is IB data payload max. It's the largest power of 2 less
2169 * than piosize (or even larger, since it only really controls the
2170 * largest we can receive; we can send the max of the mtu and
2171 * piosize). We check that it's one of the valid IB sizes.
2173 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
2174 (arg != 4096 || !ipath_mtu4096)) {
2175 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
2179 if (dd->ipath_ibmtu == arg) {
2180 ret = 0; /* same as current */
2184 piosize = dd->ipath_ibmaxlen;
2185 dd->ipath_ibmtu = arg;
2187 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
2188 /* Only if it's not the initial value (or reset to it) */
2189 if (piosize != dd->ipath_init_ibmaxlen) {
2190 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
2191 piosize = dd->ipath_init_ibmaxlen;
2192 dd->ipath_ibmaxlen = piosize;
2195 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
2196 piosize = arg + IPATH_PIO_MAXIBHDR;
2197 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
2198 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
2200 dd->ipath_ibmaxlen = piosize;
2205 u64 ibc = dd->ipath_ibcctrl, ibdw;
2207 * update our housekeeping variables, and set IBC max
2208 * size, same as init code; max IBC is max we allow in
2209 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2211 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
2212 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
2213 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
2214 dd->ibcc_mpl_shift);
2215 ibc |= ibdw << dd->ibcc_mpl_shift;
2216 dd->ipath_ibcctrl = ibc;
2217 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2219 dd->ipath_f_tidtemplate(dd);
2228 int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
2230 dd->ipath_lid = lid;
2231 dd->ipath_lmc = lmc;
2233 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
2234 (~((1U << lmc) - 1)) << 16);
2236 dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2243 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2244 * @dd: the infinipath device
2245 * @regno: the register number to write
2246 * @port: the port containing the register
2247 * @value: the value to write
2249 * Registers that vary with the chip implementation constants (port)
2252 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2253 unsigned port, u64 value)
2257 if (port < dd->ipath_portcnt &&
2258 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2259 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2260 where = regno + port;
2264 ipath_write_kreg(dd, where, value);
2268 * Following deal with the "obviously simple" task of overriding the state
2269 * of the LEDS, which normally indicate link physical and logical status.
2270 * The complications arise in dealing with different hardware mappings
2271 * and the board-dependent routine being called from interrupts.
2272 * and then there's the requirement to _flash_ them.
2274 #define LED_OVER_FREQ_SHIFT 8
2275 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2276 /* Below is "non-zero" to force override, but both actual LEDs are off */
2277 #define LED_OVER_BOTH_OFF (8)
2279 static void ipath_run_led_override(unsigned long opaque)
2281 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2284 u64 lstate, ltstate, val;
2286 if (!(dd->ipath_flags & IPATH_INITTED))
2289 pidx = dd->ipath_led_override_phase++ & 1;
2290 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2291 timeoff = dd->ipath_led_override_timeoff;
2294 * below potentially restores the LED values per current status,
2295 * should also possibly setup the traffic-blink register,
2296 * but leave that to per-chip functions.
2298 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2299 ltstate = ipath_ib_linktrstate(dd, val);
2300 lstate = ipath_ib_linkstate(dd, val);
2302 dd->ipath_f_setextled(dd, lstate, ltstate);
2303 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2306 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2310 if (!(dd->ipath_flags & IPATH_INITTED))
2313 /* First check if we are blinking. If not, use 1HZ polling */
2315 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2318 /* For blink, set each phase from one nybble of val */
2319 dd->ipath_led_override_vals[0] = val & 0xF;
2320 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2321 timeoff = (HZ << 4)/freq;
2323 /* Non-blink set both phases the same. */
2324 dd->ipath_led_override_vals[0] = val & 0xF;
2325 dd->ipath_led_override_vals[1] = val & 0xF;
2327 dd->ipath_led_override_timeoff = timeoff;
2330 * If the timer has not already been started, do so. Use a "quick"
2331 * timeout so the function will be called soon, to look at our request.
2333 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2334 /* Need to start timer */
2335 init_timer(&dd->ipath_led_override_timer);
2336 dd->ipath_led_override_timer.function =
2337 ipath_run_led_override;
2338 dd->ipath_led_override_timer.data = (unsigned long) dd;
2339 dd->ipath_led_override_timer.expires = jiffies + 1;
2340 add_timer(&dd->ipath_led_override_timer);
2342 atomic_dec(&dd->ipath_led_override_timer_active);
2346 * ipath_shutdown_device - shut down a device
2347 * @dd: the infinipath device
2349 * This is called to make the device quiet when we are about to
2350 * unload the driver, and also when the device is administratively
2351 * disabled. It does not free any data structures.
2352 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2354 void ipath_shutdown_device(struct ipath_devdata *dd)
2356 unsigned long flags;
2358 ipath_dbg("Shutting down the device\n");
2360 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2362 dd->ipath_flags |= IPATH_LINKUNK;
2363 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2364 IPATH_LINKINIT | IPATH_LINKARMED |
2366 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2367 IPATH_STATUS_IB_READY);
2369 /* mask interrupts, but not errors */
2370 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2372 dd->ipath_rcvctrl = 0;
2373 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2376 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2380 * gracefully stop all sends allowing any in progress to trickle out
2383 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2384 dd->ipath_sendctrl = 0;
2385 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2387 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2388 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2391 * enough for anything that's going to trickle out to have actually
2396 dd->ipath_f_setextled(dd, 0, 0); /* make sure LEDs are off */
2398 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2399 ipath_cancel_sends(dd, 0);
2402 * we are shutting down, so tell components that care. We don't do
2403 * this on just a link state change, much like ethernet, a cable
2404 * unplug, etc. doesn't change driver state
2406 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2409 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2410 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2411 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2414 * clear SerdesEnable and turn the leds off; do this here because
2415 * we are unloading, so don't count on interrupts to move along
2416 * Turn the LEDs off explictly for the same reason.
2418 dd->ipath_f_quiet_serdes(dd);
2420 /* stop all the timers that might still be running */
2421 del_timer_sync(&dd->ipath_hol_timer);
2422 if (dd->ipath_stats_timer_active) {
2423 del_timer_sync(&dd->ipath_stats_timer);
2424 dd->ipath_stats_timer_active = 0;
2426 if (dd->ipath_intrchk_timer.data) {
2427 del_timer_sync(&dd->ipath_intrchk_timer);
2428 dd->ipath_intrchk_timer.data = 0;
2430 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2431 del_timer_sync(&dd->ipath_led_override_timer);
2432 atomic_set(&dd->ipath_led_override_timer_active, 0);
2436 * clear all interrupts and errors, so that the next time the driver
2437 * is loaded or device is enabled, we know that whatever is set
2438 * happened while we were unloaded
2440 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2441 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2442 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2443 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2445 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2446 ipath_update_eeprom_log(dd);
2450 * ipath_free_pddata - free a port's allocated data
2451 * @dd: the infinipath device
2452 * @pd: the portdata structure
2454 * free up any allocated data for a port
2455 * This should not touch anything that would affect a simultaneous
2456 * re-allocation of port data, because it is called after ipath_mutex
2457 * is released (and can be called from reinit as well).
2458 * It should never change any chip state, or global driver state.
2459 * (The only exception to global state is freeing the port0 port0_skbs.)
2461 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2466 if (pd->port_rcvhdrq) {
2467 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2468 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2469 (unsigned long) pd->port_rcvhdrq_size);
2470 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2471 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2472 pd->port_rcvhdrq = NULL;
2473 if (pd->port_rcvhdrtail_kvaddr) {
2474 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2475 pd->port_rcvhdrtail_kvaddr,
2476 pd->port_rcvhdrqtailaddr_phys);
2477 pd->port_rcvhdrtail_kvaddr = NULL;
2480 if (pd->port_port && pd->port_rcvegrbuf) {
2483 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2484 void *base = pd->port_rcvegrbuf[e];
2485 size_t size = pd->port_rcvegrbuf_size;
2487 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2488 "chunk %u/%u\n", base,
2489 (unsigned long) size,
2490 e, pd->port_rcvegrbuf_chunks);
2491 dma_free_coherent(&dd->pcidev->dev, size,
2492 base, pd->port_rcvegrbuf_phys[e]);
2494 kfree(pd->port_rcvegrbuf);
2495 pd->port_rcvegrbuf = NULL;
2496 kfree(pd->port_rcvegrbuf_phys);
2497 pd->port_rcvegrbuf_phys = NULL;
2498 pd->port_rcvegrbuf_chunks = 0;
2499 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2501 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2503 dd->ipath_port0_skbinfo = NULL;
2504 ipath_cdbg(VERBOSE, "free closed port %d "
2505 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2507 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2508 if (skbinfo[e].skb) {
2509 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2511 PCI_DMA_FROMDEVICE);
2512 dev_kfree_skb(skbinfo[e].skb);
2516 kfree(pd->port_tid_pg_list);
2517 vfree(pd->subport_uregbase);
2518 vfree(pd->subport_rcvegrbuf);
2519 vfree(pd->subport_rcvhdr_base);
2523 static int __init infinipath_init(void)
2527 if (ipath_debug & __IPATH_DBG)
2528 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2531 * These must be called before the driver is registered with
2532 * the PCI subsystem.
2534 idr_init(&unit_table);
2535 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2536 printk(KERN_ERR IPATH_DRV_NAME ": idr_pre_get() failed\n");
2541 ret = pci_register_driver(&ipath_driver);
2543 printk(KERN_ERR IPATH_DRV_NAME
2544 ": Unable to register driver: error %d\n", -ret);
2548 ret = ipath_init_ipathfs();
2550 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2551 "ipathfs: error %d\n", -ret);
2558 pci_unregister_driver(&ipath_driver);
2561 idr_destroy(&unit_table);
2567 static void __exit infinipath_cleanup(void)
2569 ipath_exit_ipathfs();
2571 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2572 pci_unregister_driver(&ipath_driver);
2574 idr_destroy(&unit_table);
2578 * ipath_reset_device - reset the chip if possible
2579 * @unit: the device to reset
2581 * Whether or not reset is successful, we attempt to re-initialize the chip
2582 * (that is, much like a driver unload/reload). We clear the INITTED flag
2583 * so that the various entry points will fail until we reinitialize. For
2584 * now, we only allow this if no user ports are open that use chip resources
2586 int ipath_reset_device(int unit)
2589 struct ipath_devdata *dd = ipath_lookup(unit);
2590 unsigned long flags;
2597 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2598 /* Need to stop LED timer, _then_ shut off LEDs */
2599 del_timer_sync(&dd->ipath_led_override_timer);
2600 atomic_set(&dd->ipath_led_override_timer_active, 0);
2603 /* Shut off LEDs after we are sure timer is not running */
2604 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2605 dd->ipath_f_setextled(dd, 0, 0);
2607 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2609 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2610 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2611 "not initialized or not present\n", unit);
2616 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
2618 for (i = 1; i < dd->ipath_cfgports; i++) {
2619 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2621 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2622 ipath_dbg("unit %u port %d is in use "
2623 "(PID %u cmd %s), can't reset\n",
2625 pid_nr(dd->ipath_pd[i]->port_pid),
2626 dd->ipath_pd[i]->port_comm);
2630 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2632 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2635 dd->ipath_flags &= ~IPATH_INITTED;
2636 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2637 ret = dd->ipath_f_reset(dd);
2639 ipath_dbg("Reinitializing unit %u after reset attempt\n",
2641 ret = ipath_init_chip(dd, 1);
2645 ipath_dev_err(dd, "Reinitialize unit %u after "
2646 "reset failed with %d\n", unit, ret);
2648 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2649 "resetting\n", unit);
2656 * send a signal to all the processes that have the driver open
2657 * through the normal interfaces (i.e., everything other than diags
2658 * interface). Returns number of signalled processes.
2660 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2662 int i, sub, any = 0;
2664 unsigned long flags;
2669 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
2670 for (i = 1; i < dd->ipath_cfgports; i++) {
2671 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2673 pid = dd->ipath_pd[i]->port_pid;
2677 dev_info(&dd->pcidev->dev, "context %d in use "
2678 "(PID %u), sending signal %d\n",
2679 i, pid_nr(pid), sig);
2680 kill_pid(pid, sig, 1);
2682 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2683 pid = dd->ipath_pd[i]->port_subpid[sub];
2686 dev_info(&dd->pcidev->dev, "sub-context "
2687 "%d:%d in use (PID %u), sending "
2688 "signal %d\n", i, sub, pid_nr(pid), sig);
2689 kill_pid(pid, sig, 1);
2693 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2697 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2699 if (ipath_signal_procs(dd, SIGSTOP))
2700 ipath_dbg("Stopped some processes\n");
2701 ipath_cancel_sends(dd, 1);
2705 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2707 if (ipath_signal_procs(dd, SIGCONT))
2708 ipath_dbg("Continued some processes\n");
2712 * link is down, stop any users processes, and flush pending sends
2713 * to prevent HoL blocking, then start the HoL timer that
2714 * periodically continues, then stop procs, so they can detect
2715 * link down if they want, and do something about it.
2716 * Timer may already be running, so use mod_timer, not add_timer.
2718 void ipath_hol_down(struct ipath_devdata *dd)
2720 dd->ipath_hol_state = IPATH_HOL_DOWN;
2721 ipath_hol_signal_down(dd);
2722 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2723 dd->ipath_hol_timer.expires = jiffies +
2724 msecs_to_jiffies(ipath_hol_timeout_ms);
2725 mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2729 * link is up, continue any user processes, and ensure timer
2730 * is a nop, if running. Let timer keep running, if set; it
2731 * will nop when it sees the link is up
2733 void ipath_hol_up(struct ipath_devdata *dd)
2735 ipath_hol_signal_up(dd);
2736 dd->ipath_hol_state = IPATH_HOL_UP;
2740 * toggle the running/not running state of user proceses
2741 * to prevent HoL blocking on chip resources, but still allow
2742 * user processes to do link down special case handling.
2743 * Should only be called via the timer
2745 void ipath_hol_event(unsigned long opaque)
2747 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2749 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2750 && dd->ipath_hol_state != IPATH_HOL_UP) {
2751 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2752 ipath_dbg("Stopping processes\n");
2753 ipath_hol_signal_down(dd);
2754 } else { /* may do "extra" if also in ipath_hol_up() */
2755 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2756 ipath_dbg("Continuing processes\n");
2757 ipath_hol_signal_up(dd);
2759 if (dd->ipath_hol_state == IPATH_HOL_UP)
2760 ipath_dbg("link's up, don't resched timer\n");
2762 dd->ipath_hol_timer.expires = jiffies +
2763 msecs_to_jiffies(ipath_hol_timeout_ms);
2764 mod_timer(&dd->ipath_hol_timer,
2765 dd->ipath_hol_timer.expires);
2769 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2773 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2775 if (dd->ipath_rx_pol_inv != new_pol_inv) {
2776 dd->ipath_rx_pol_inv = new_pol_inv;
2777 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2778 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2779 INFINIPATH_XGXS_RX_POL_SHIFT);
2780 val |= ((u64)dd->ipath_rx_pol_inv) <<
2781 INFINIPATH_XGXS_RX_POL_SHIFT;
2782 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2788 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2789 * the 7220, which is count-based, rather than trigger-based. Safe for the
2790 * driver check, since it's at init. Not completely safe when used for
2791 * user-mode checking, since some error checking can be lost, but not
2792 * particularly risky, and only has problematic side-effects in the face of
2793 * very buggy user code. There is no reference counting, but that's also
2794 * fine, given the intended use.
2796 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2798 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2799 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2800 INFINIPATH_E_SPIOARMLAUNCH);
2801 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2802 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2803 dd->ipath_errormask);
2806 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2808 /* so don't re-enable if already set */
2809 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2810 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2811 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2812 dd->ipath_errormask);
2815 module_init(infinipath_init);
2816 module_exit(infinipath_cleanup);