drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
  47
  48 /*
  49  * This file contains all the chip-specific register information and
  50  * access functions for the QLogic InfiniPath PCI-Express chip.
  51  *
  52  * This lists the InfiniPath registers, in the actual chip layout.
  53  * This structure should never be directly accessed.
  54  */
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long Reserved0;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long Reserved1;
  67         unsigned long long Reserved2;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long Reserved3;
 103         unsigned long long RcvPktLEDCnt;
 104         unsigned long long Reserved4[8];
 105         unsigned long long SendCtrl;
 106         unsigned long long SendPIOBufBase;
 107         unsigned long long SendPIOSize;
 108         unsigned long long SendPIOBufCnt;
 109         unsigned long long SendPIOAvailAddr;
 110         unsigned long long TxIntMemBase;
 111         unsigned long long TxIntMemSize;
 112         unsigned long long Reserved5;
 113         unsigned long long PCIeRBufTestReg0;
 114         unsigned long long PCIeRBufTestReg1;
 115         unsigned long long Reserved51[6];
 116         unsigned long long SendBufferError;
 117         unsigned long long SendBufferErrorCONT1;
 118         unsigned long long Reserved6SBE[6];
 119         unsigned long long RcvHdrAddr0;
 120         unsigned long long RcvHdrAddr1;
 121         unsigned long long RcvHdrAddr2;
 122         unsigned long long RcvHdrAddr3;
 123         unsigned long long RcvHdrAddr4;
 124         unsigned long long Reserved7RHA[11];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long Reserved8RHTA[11];
 131         unsigned long long Reserved9SW[8];
 132         unsigned long long SerdesConfig0;
 133         unsigned long long SerdesConfig1;
 134         unsigned long long SerdesStatus;
 135         unsigned long long XGXSConfig;
 136         unsigned long long IBPLLCfg;
 137         unsigned long long Reserved10SW2[3];
 138         unsigned long long PCIEQ0SerdesConfig0;
 139         unsigned long long PCIEQ0SerdesConfig1;
 140         unsigned long long PCIEQ0SerdesStatus;
 141         unsigned long long Reserved11;
 142         unsigned long long PCIEQ1SerdesConfig0;
 143         unsigned long long PCIEQ1SerdesConfig1;
 144         unsigned long long PCIEQ1SerdesStatus;
 145         unsigned long long Reserved12;
 146 };
 147
 148 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 149     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 150 #define IPATH_CREG_OFFSET(field) (offsetof( \
 151     struct infinipath_counters, field) / sizeof(u64))
 152
 153 static const struct ipath_kregs ipath_pe_kregs = {
 154         .kr_control = IPATH_KREG_OFFSET(Control),
 155         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 156         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 157         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 158         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 159         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 160         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 161         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 162         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 163         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 164         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 165         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 166         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 167         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 168         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 169         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 170         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 171         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 172         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 173         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 174         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 175         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 176         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 177         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 178         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 179         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 180         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 181         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 182         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 183         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 184         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 185         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 186         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 187         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 188         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 189         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 190         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 191         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 192         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 193         .kr_revision = IPATH_KREG_OFFSET(Revision),
 194         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 195         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 196         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 197         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 198         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 199         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 200         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 201         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 202         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 203         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 204         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 205         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 206         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 207         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 208         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 209         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 210
 211         /*
 212          * These should not be used directly via ipath_write_kreg64(),
 213          * use them with ipath_write_kreg64_port(),
 214          */
 215         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 216         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 217
 218         /* The rcvpktled register controls one of the debug port signals, so
 219          * a packet activity LED can be connected to it. */
 220         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 221         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 222         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 223         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 224         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 225         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 226         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 227         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 228         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 229 };
 230
 231 static const struct ipath_cregs ipath_pe_cregs = {
 232         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 233         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 234         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 235         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 236         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 237         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 238         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 239         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 240         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 241         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 242         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 243         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 244         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 245         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 246         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 247         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 248         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 249         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 250         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 251         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 252         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 253         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 254         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 255         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 256         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 257         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 258         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 259         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 260         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 261         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 262         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 263         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 264         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 265 };
 266
 267 /* kr_intstatus, kr_intclear, kr_intmask bits */
 268 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
 269 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
 270
 271 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 272 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 273 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 274 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 275 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 276 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 277 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 278 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 279 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 280 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 281 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 282 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 283 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 284
 285 /* kr_extstatus bits */
 286 #define INFINIPATH_EXTS_FREQSEL 0x2
 287 #define INFINIPATH_EXTS_SERDESSEL 0x4
 288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 289 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 290
 291 #define _IPATH_GPIO_SDA_NUM 1
 292 #define _IPATH_GPIO_SCL_NUM 0
 293
 294 #define IPATH_GPIO_SDA (1ULL << \
 295         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 296 #define IPATH_GPIO_SCL (1ULL << \
 297         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 298
 299 /* 6120 specific hardware errors... */
 300 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 301         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 302         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 303         /*
 304          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 305          * parity or memory parity error failures, because most likely we
 306          * won't be able to talk to the core of the chip.  Nonetheless, we
 307          * might see them, if they are in parts of the PCIe core that aren't
 308          * essential.
 309          */
 310         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 311         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 312         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 313         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 314         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 315         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 316         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 317 };
 318
 319 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 320                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 321                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 322
 323 static int ipath_pe_txe_recover(struct ipath_devdata *);
 324
 325 /**
 326  * ipath_pe_handle_hwerrors - display hardware errors.
 327  * @dd: the infinipath device
 328  * @msg: the output buffer
 329  * @msgl: the size of the output buffer
 330  *
 331  * Use same msg buffer as regular errors to avoid excessive stack
 332  * use.  Most hardware errors are catastrophic, but for right now,
 333  * we'll print them and continue.  We reuse the same message buffer as
 334  * ipath_handle_errors() to avoid excessive stack usage.
 335  */
 336 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 337                                      size_t msgl)
 338 {
 339         ipath_err_t hwerrs;
 340         u32 bits, ctrl;
 341         int isfatal = 0;
 342         char bitsmsg[64];
 343         int log_idx;
 344
 345         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 346         if (!hwerrs) {
 347                 /*
 348                  * better than printing cofusing messages
 349                  * This seems to be related to clearing the crc error, or
 350                  * the pll error during init.
 351                  */
 352                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 353                 return;
 354         } else if (hwerrs == ~0ULL) {
 355                 ipath_dev_err(dd, "Read of hardware error status failed "
 356                               "(all bits set); ignoring\n");
 357                 return;
 358         }
 359         ipath_stats.sps_hwerrs++;
 360
 361         /* Always clear the error status register, except MEMBISTFAIL,
 362          * regardless of whether we continue or stop using the chip.
 363          * We want that set so we know it failed, even across driver reload.
 364          * We'll still ignore it in the hwerrmask.  We do this partly for
 365          * diagnostics, but also for support */
 366         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 367                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 368
 369         hwerrs &= dd->ipath_hwerrmask;
 370
 371         /* We log some errors to EEPROM, check if we have any of those. */
 372         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 373                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 374                         ipath_inc_eeprom_err(dd, log_idx, 1);
 375
 376         /*
 377          * make sure we get this much out, unless told to be quiet,
 378          * or it's occurred within the last 5 seconds
 379          */
 380         if ((hwerrs & ~(dd->ipath_lasthwerror |
 381                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 382                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 383                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 384             (ipath_debug & __IPATH_VERBDBG))
 385                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 386                          "(cleared)\n", (unsigned long long) hwerrs);
 387         dd->ipath_lasthwerror |= hwerrs;
 388
 389         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 390                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 391                               "%llx set\n", (unsigned long long)
 392                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 393
 394         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 395         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 396                 /*
 397                  * parity errors in send memory are recoverable,
 398                  * just cancel the send (if indicated in * sendbuffererror),
 399                  * count the occurrence, unfreeze (if no other handled
 400                  * hardware error bits are set), and continue. They can
 401                  * occur if a processor speculative read is done to the PIO
 402                  * buffer while we are sending a packet, for example.
 403                  */
 404                 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
 405                         hwerrs &= ~TXE_PIO_PARITY;
 406                 if (hwerrs) {
 407                         /*
 408                          * if any set that we aren't ignoring only make the
 409                          * complaint once, in case it's stuck or recurring,
 410                          * and we get here multiple times
 411                          * Force link down, so switch knows, and
 412                          * LEDs are turned off
 413                          */
 414                         if (dd->ipath_flags & IPATH_INITTED) {
 415                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 416                                 ipath_setup_pe_setextled(dd,
 417                                         INFINIPATH_IBCS_L_STATE_DOWN,
 418                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
 419                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 420                                               "mode), no longer usable, SN %.16s\n",
 421                                                   dd->ipath_serial);
 422                                 isfatal = 1;
 423                         }
 424                         /*
 425                          * Mark as having had an error for driver, and also
 426                          * for /sys and status word mapped to user programs.
 427                          * This marks unit as not usable, until reset
 428                          */
 429                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 430                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 431                         dd->ipath_flags &= ~IPATH_INITTED;
 432                 } else {
 433                         static u32 freeze_cnt;
 434
 435                         freeze_cnt++;
 436                         ipath_dbg("Clearing freezemode on ignored or recovered "
 437                                   "hardware error (%u)\n", freeze_cnt);
 438                         /*
 439                          * clear all sends, becauase they have may been
 440                          * completed by usercode while in freeze mode, and
 441                          * therefore would not be sent, and eventually
 442                          * might cause the process to run out of bufs
 443                          */
 444                         ipath_cancel_sends(dd);
 445                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 446                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 447                                          dd->ipath_control);
 448                 }
 449         }
 450
 451         *msg = '\0';
 452
 453         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 454                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 455                         msgl);
 456                 /* ignore from now on, so disable until driver reloaded */
 457                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 458                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 459                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 460                                  dd->ipath_hwerrmask);
 461         }
 462
 463         ipath_format_hwerrors(hwerrs,
 464                               ipath_6120_hwerror_msgs,
 465                               sizeof(ipath_6120_hwerror_msgs)/
 466                               sizeof(ipath_6120_hwerror_msgs[0]),
 467                               msg, msgl);
 468
 469         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 470                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 471                 bits = (u32) ((hwerrs >>
 472                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 473                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 474                 snprintf(bitsmsg, sizeof bitsmsg,
 475                          "[PCIe Mem Parity Errs %x] ", bits);
 476                 strlcat(msg, bitsmsg, msgl);
 477         }
 478
 479 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 480                          INFINIPATH_HWE_COREPLL_RFSLIP )
 481
 482         if (hwerrs & _IPATH_PLL_FAIL) {
 483                 snprintf(bitsmsg, sizeof bitsmsg,
 484                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 485                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 486                 strlcat(msg, bitsmsg, msgl);
 487                 /* ignore from now on, so disable until driver reloaded */
 488                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 489                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 490                                  dd->ipath_hwerrmask);
 491         }
 492
 493         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 494                 /*
 495                  * If it occurs, it is left masked since the eternal
 496                  * interface is unused
 497                  */
 498                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 499                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 500                                  dd->ipath_hwerrmask);
 501         }
 502
 503         if (*msg)
 504                 ipath_dev_err(dd, "%s hardware error\n", msg);
 505         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 506                 /*
 507                  * for /sys status file ; if no trailing } is copied, we'll
 508                  * know it was truncated.
 509                  */
 510                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 511                          "{%s}", msg);
 512         }
 513 }
 514
 515 /**
 516  * ipath_pe_boardname - fill in the board name
 517  * @dd: the infinipath device
 518  * @name: the output buffer
 519  * @namelen: the size of the output buffer
 520  *
 521  * info is based on the board revision register
 522  */
 523 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 524                               size_t namelen)
 525 {
 526         char *n = NULL;
 527         u8 boardrev = dd->ipath_boardrev;
 528         int ret;
 529
 530         switch (boardrev) {
 531         case 0:
 532                 n = "InfiniPath_Emulation";
 533                 break;
 534         case 1:
 535                 n = "InfiniPath_QLE7140-Bringup";
 536                 break;
 537         case 2:
 538                 n = "InfiniPath_QLE7140";
 539                 break;
 540         case 3:
 541                 n = "InfiniPath_QMI7140";
 542                 break;
 543         case 4:
 544                 n = "InfiniPath_QEM7140";
 545                 break;
 546         case 5:
 547                 n = "InfiniPath_QMH7140";
 548                 break;
 549         case 6:
 550                 n = "InfiniPath_QLE7142";
 551                 break;
 552         default:
 553                 ipath_dev_err(dd,
 554                               "Don't yet know about board with ID %u\n",
 555                               boardrev);
 556                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 557                          boardrev);
 558                 break;
 559         }
 560         if (n)
 561                 snprintf(name, namelen, "%s", n);
 562
 563         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 564                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 565                               dd->ipath_majrev, dd->ipath_minrev);
 566                 ret = 1;
 567         } else
 568                 ret = 0;
 569
 570         return ret;
 571 }
 572
 573 /**
 574  * ipath_pe_init_hwerrors - enable hardware errors
 575  * @dd: the infinipath device
 576  *
 577  * now that we have finished initializing everything that might reasonably
 578  * cause a hardware error, and cleared those errors bits as they occur,
 579  * we can enable hardware errors in the mask (potentially enabling
 580  * freeze mode), and enable hardware errors as errors (along with
 581  * everything else) in errormask
 582  */
 583 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 584 {
 585         ipath_err_t val;
 586         u64 extsval;
 587
 588         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 589
 590         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 591                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 592         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
 593                 ipath_dbg("MemBIST corrected\n");
 594
 595         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 596
 597         if (!dd->ipath_boardrev)        // no PLL for Emulator
 598                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 599
 600         if (dd->ipath_minrev < 2) {
 601                 /* workaround bug 9460 in internal interface bus parity
 602                  * checking. Fixed (HW bug 9490) in Rev2.
 603                  */
 604                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 605         }
 606         dd->ipath_hwerrmask = val;
 607 }
 608
 609 /**
 610  * ipath_pe_bringup_serdes - bring up the serdes
 611  * @dd: the infinipath device
 612  */
 613 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 614 {
 615         u64 val, config1, prev_val;
 616         int ret = 0;
 617
 618         ipath_dbg("Trying to bringup serdes\n");
 619
 620         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 621             INFINIPATH_HWE_SERDESPLLFAILED) {
 622                 ipath_dbg("At start, serdes PLL failed bit set "
 623                           "in hwerrstatus, clearing and continuing\n");
 624                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 625                                  INFINIPATH_HWE_SERDESPLLFAILED);
 626         }
 627
 628         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 629         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 630
 631         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 632                    "xgxsconfig %llx\n", (unsigned long long) val,
 633                    (unsigned long long) config1, (unsigned long long)
 634                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 635
 636         /*
 637          * Force reset on, also set rxdetect enable.  Must do before reading
 638          * serdesstatus at least for simulation, or some of the bits in
 639          * serdes status will come back as undefined and cause simulation
 640          * failures
 641          */
 642         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 643                 | INFINIPATH_SERDC0_L1PWR_DN;
 644         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 645         /* be sure chip saw it */
 646         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 647         udelay(5);              /* need pll reset set at least for a bit */
 648         /*
 649          * after PLL is reset, set the per-lane Resets and TxIdle and
 650          * clear the PLL reset and rxdetect (to get falling edge).
 651          * Leave L1PWR bits set (permanently)
 652          */
 653         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 654                  | INFINIPATH_SERDC0_L1PWR_DN);
 655         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 656         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 657                    "and txidle (%llx)\n", (unsigned long long) val);
 658         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 659         /* be sure chip saw it */
 660         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 661         /* need PLL reset clear for at least 11 usec before lane
 662          * resets cleared; give it a few more to be sure */
 663         udelay(15);
 664         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 665
 666         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 667                    "(writing %llx)\n", (unsigned long long) val);
 668         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 669         /* be sure chip saw it */
 670         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 671
 672         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 673         prev_val = val;
 674         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
 675              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
 676                 val &=
 677                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
 678                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
 679                 /* MDIO address 3 */
 680                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
 681         }
 682         if (val & INFINIPATH_XGXS_RESET) {
 683                 val &= ~INFINIPATH_XGXS_RESET;
 684         }
 685         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 686              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 687                 /* need to compensate for Tx inversion in partner */
 688                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 689                          INFINIPATH_XGXS_RX_POL_SHIFT);
 690                 val |= dd->ipath_rx_pol_inv <<
 691                         INFINIPATH_XGXS_RX_POL_SHIFT;
 692         }
 693         if (val != prev_val)
 694                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 695
 696         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 697
 698         /* clear current and de-emphasis bits */
 699         config1 &= ~0x0ffffffff00ULL;
 700         /* set current to 20ma */
 701         config1 |= 0x00000000000ULL;
 702         /* set de-emphasis to -5.68dB */
 703         config1 |= 0x0cccc000000ULL;
 704         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 705
 706         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 707                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 708                    (unsigned long long) val, (unsigned long long) config1,
 709                    (unsigned long long)
 710                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 711                    (unsigned long long)
 712                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 713
 714         if (!ipath_waitfor_mdio_cmdready(dd)) {
 715                 ipath_write_kreg(
 716                         dd, dd->ipath_kregs->kr_mdio,
 717                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
 718                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
 719                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
 720                                            IPATH_MDIO_DATAVALID, &val))
 721                         ipath_dbg("Never got MDIO data for XGXS "
 722                                   "status read\n");
 723                 else
 724                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
 725                                    "'bank' 31 %x\n", (u32) val);
 726         } else
 727                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
 728
 729         return ret;
 730 }
 731
 732 /**
 733  * ipath_pe_quiet_serdes - set serdes to txidle
 734  * @dd: the infinipath device
 735  * Called when driver is being unloaded
 736  */
 737 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 738 {
 739         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 740
 741         val |= INFINIPATH_SERDC0_TXIDLE;
 742         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 743                   (unsigned long long) val);
 744         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 745 }
 746
 747 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 748 {
 749         u32 chiprev;
 750
 751         /*
 752          * If the chip supports added error indication via GPIO pins,
 753          * enable interrupts on those bits so the interrupt routine
 754          * can count the events. Also set flag so interrupt routine
 755          * can know they are expected.
 756          */
 757         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 758         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 759                 /* Rev2+ reports extra errors via internal GPIO pins */
 760                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 761                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
 762                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
 763                                  dd->ipath_gpio_mask);
 764         }
 765         return 0;
 766 }
 767
 768 /**
 769  * ipath_setup_pe_setextled - set the state of the two external LEDs
 770  * @dd: the infinipath device
 771  * @lst: the L state
 772  * @ltst: the LT state
 773
 774  * These LEDs indicate the physical and logical state of IB link.
 775  * For this chip (at least with recommended board pinouts), LED1
 776  * is Yellow (logical state) and LED2 is Green (physical state),
 777  *
 778  * Note:  We try to match the Mellanox HCA LED behavior as best
 779  * we can.  Green indicates physical link state is OK (something is
 780  * plugged in, and we can train).
 781  * Amber indicates the link is logically up (ACTIVE).
 782  * Mellanox further blinks the amber LED to indicate data packet
 783  * activity, but we have no hardware support for that, so it would
 784  * require waking up every 10-20 msecs and checking the counters
 785  * on the chip, and then turning the LED off if appropriate.  That's
 786  * visible overhead, so not something we will do.
 787  *
 788  */
 789 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 790                                      u64 ltst)
 791 {
 792         u64 extctl;
 793         unsigned long flags = 0;
 794
 795         /* the diags use the LED to indicate diag info, so we leave
 796          * the external LED alone when the diags are running */
 797         if (ipath_diag_inuse)
 798                 return;
 799
 800         /* Allow override of LED display for, e.g. Locating system in rack */
 801         if (dd->ipath_led_override) {
 802                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
 803                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
 804                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
 805                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
 806                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
 807                         : INFINIPATH_IBCS_L_STATE_DOWN;
 808         }
 809
 810         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
 811         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 812                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 813
 814         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 815                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 816         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 817                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 818         dd->ipath_extctrl = extctl;
 819         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 820         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
 821 }
 822
 823 /**
 824  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 825  * @dd: the infinipath device
 826  *
 827  * This is called during driver unload.
 828  * We do the pci_disable_msi here, not in generic code, because it
 829  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 830  * at some point in the future for HT, we'll move the call back
 831  * into the main init_one code.
 832  */
 833 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 834 {
 835         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 836         pci_disable_msi(dd->pcidev);
 837 }
 838
 839 /**
 840  * ipath_setup_pe_config - setup PCIe config related stuff
 841  * @dd: the infinipath device
 842  * @pdev: the PCI device
 843  *
 844  * The pci_enable_msi() call will fail on systems with MSI quirks
 845  * such as those with AMD8131, even if the device of interest is not
 846  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 847  * late in 2.6.16).
 848  * All that can be done is to edit the kernel source to remove the quirk
 849  * check until that is fixed.
 850  * We do not need to call enable_msi() for our HyperTransport chip,
 851  * even though it uses MSI, and we want to avoid the quirk warning, so
 852  * So we call enable_msi only for PCIe.  If we do end up needing
 853  * pci_enable_msi at some point in the future for HT, we'll move the
 854  * call back into the main init_one code.
 855  * We save the msi lo and hi values, so we can restore them after
 856  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 857  * correctly).
 858  */
 859 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 860                                  struct pci_dev *pdev)
 861 {
 862         int pos, ret;
 863
 864         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 865         ret = pci_enable_msi(dd->pcidev);
 866         if (ret)
 867                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 868                               "interrupts may not work\n", ret);
 869         /* continue even if it fails, we may still be OK... */
 870         dd->ipath_irq = pdev->irq;
 871
 872         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 873                 u16 control;
 874                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 875                                       &dd->ipath_msi_lo);
 876                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 877                                       &dd->ipath_msi_hi);
 878                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 879                                      &control);
 880                 /* now save the data (vector) info */
 881                 pci_read_config_word(dd->pcidev,
 882                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 883                                             ? 12 : 8),
 884                                      &dd->ipath_msi_data);
 885                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 886                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 887                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 888                            control);
 889                 /* we save the cachelinesize also, although it doesn't
 890                  * really matter */
 891                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 892                                      &dd->ipath_pci_cacheline);
 893         } else
 894                 ipath_dev_err(dd, "Can't find MSI capability, "
 895                               "can't save MSI settings for reset\n");
 896         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 897                 u16 linkstat;
 898                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 899                                      &linkstat);
 900                 linkstat >>= 4;
 901                 linkstat &= 0x1f;
 902                 if (linkstat != 8)
 903                         ipath_dev_err(dd, "PCIe width %u, "
 904                                       "performance reduced\n", linkstat);
 905         }
 906         else
 907                 ipath_dev_err(dd, "Can't find PCI Express "
 908                               "capability!\n");
 909         return 0;
 910 }
 911
 912 static void ipath_init_pe_variables(struct ipath_devdata *dd)
 913 {
 914         /*
 915          * bits for selecting i2c direction and values,
 916          * used for I2C serial flash
 917          */
 918         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 919         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 920         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
 921         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
 922
 923         /* variables for sanity checking interrupt and errors */
 924         dd->ipath_hwe_bitsextant =
 925                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 926                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
 927                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 928                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
 929                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
 930                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
 931                 INFINIPATH_HWE_PCIE1PLLFAILED |
 932                 INFINIPATH_HWE_PCIE0PLLFAILED |
 933                 INFINIPATH_HWE_PCIEPOISONEDTLP |
 934                 INFINIPATH_HWE_PCIECPLTIMEOUT |
 935                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
 936                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
 937                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
 938                 INFINIPATH_HWE_MEMBISTFAILED |
 939                 INFINIPATH_HWE_COREPLL_FBSLIP |
 940                 INFINIPATH_HWE_COREPLL_RFSLIP |
 941                 INFINIPATH_HWE_SERDESPLLFAILED |
 942                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
 943                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
 944         dd->ipath_i_bitsextant =
 945                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
 946                 (INFINIPATH_I_RCVAVAIL_MASK <<
 947                  INFINIPATH_I_RCVAVAIL_SHIFT) |
 948                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
 949                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
 950         dd->ipath_e_bitsextant =
 951                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
 952                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
 953                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
 954                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
 955                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
 956                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
 957                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
 958                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
 959                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
 960                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
 961                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
 962                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
 963                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
 964                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
 965                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
 966                 INFINIPATH_E_HARDWARE;
 967
 968         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
 969         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
 970
 971         /*
 972          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
 973          * 2 is Some Misc, 3 is reserved for future.
 974          */
 975         dd->ipath_eep_st_masks[0].hwerrs_to_log =
 976                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 977                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
 978
 979         /* Ignore errors in PIO/PBC on systems with unordered write-combining */
 980         if (ipath_unordered_wc())
 981                 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
 982
 983         dd->ipath_eep_st_masks[1].hwerrs_to_log =
 984                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 985                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
 986
 987         dd->ipath_eep_st_masks[2].errs_to_log =
 988                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
 989
 990
 991 }
 992
 993 /* setup the MSI stuff again after a reset.  I'd like to just call
 994  * pci_enable_msi() and request_irq() again, but when I do that,
 995  * the MSI enable bit doesn't get set in the command word, and
 996  * we switch to to a different interrupt vector, which is confusing,
 997  * so I instead just do it all inline.  Perhaps somehow can tie this
 998  * into the PCIe hotplug support at some point
 999  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1000  * or free_irq() at the start of ipath_setup_pe_reset().
1001  */
1002 static int ipath_reinit_msi(struct ipath_devdata *dd)
1003 {
1004         int pos;
1005         u16 control;
1006         int ret;
1007
1008         if (!dd->ipath_msi_lo) {
1009                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1010                          "initial setup failed?\n");
1011                 ret = 0;
1012                 goto bail;
1013         }
1014
1015         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1016                 ipath_dev_err(dd, "Can't find MSI capability, "
1017                               "can't restore MSI settings\n");
1018                 ret = 0;
1019                 goto bail;
1020         }
1021         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1022                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1023         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1024                                dd->ipath_msi_lo);
1025         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1026                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1027         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1028                                dd->ipath_msi_hi);
1029         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1030         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1031                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1032                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1033                            control, control | PCI_MSI_FLAGS_ENABLE);
1034                 control |= PCI_MSI_FLAGS_ENABLE;
1035                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1036                                       control);
1037         }
1038         /* now rewrite the data (vector) info */
1039         pci_write_config_word(dd->pcidev, pos +
1040                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1041                               dd->ipath_msi_data);
1042         /* we restore the cachelinesize also, although it doesn't really
1043          * matter */
1044         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1045                               dd->ipath_pci_cacheline);
1046         /* and now set the pci master bit again */
1047         pci_set_master(dd->pcidev);
1048         ret = 1;
1049
1050 bail:
1051         return ret;
1052 }
1053
1054 /* This routine sleeps, so it can only be called from user context, not
1055  * from interrupt context.  If we need interrupt context, we can split
1056  * it into two routines.
1057 */
1058 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1059 {
1060         u64 val;
1061         int i;
1062         int ret;
1063
1064         /* Use ERROR so it shows up in logs, etc. */
1065         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1066         /* keep chip from being accessed in a few places */
1067         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1068         val = dd->ipath_control | INFINIPATH_C_RESET;
1069         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1070         mb();
1071
1072         for (i = 1; i <= 5; i++) {
1073                 int r;
1074                 /* allow MBIST, etc. to complete; longer on each retry.
1075                  * We sometimes get machine checks from bus timeout if no
1076                  * response, so for now, make it *really* long.
1077                  */
1078                 msleep(1000 + (1 + i) * 2000);
1079                 if ((r =
1080                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1081                                             dd->ipath_pcibar0)))
1082                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1083                                       r);
1084                 if ((r =
1085                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1086                                             dd->ipath_pcibar1)))
1087                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1088                                       r);
1089                 /* now re-enable memory access */
1090                 if ((r = pci_enable_device(dd->pcidev)))
1091                         ipath_dev_err(dd, "pci_enable_device failed after "
1092                                       "reset: %d\n", r);
1093                 /* whether it worked or not, mark as present, again */
1094                 dd->ipath_flags |= IPATH_PRESENT;
1095                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1096                 if (val == dd->ipath_revision) {
1097                         ipath_cdbg(VERBOSE, "Got matching revision "
1098                                    "register %llx on try %d\n",
1099                                    (unsigned long long) val, i);
1100                         ret = ipath_reinit_msi(dd);
1101                         goto bail;
1102                 }
1103                 /* Probably getting -1 back */
1104                 ipath_dbg("Didn't get expected revision register, "
1105                           "got %llx, try %d\n", (unsigned long long) val,
1106                           i + 1);
1107         }
1108         ret = 0; /* failed */
1109
1110 bail:
1111         return ret;
1112 }
1113
1114 /**
1115  * ipath_pe_put_tid - write a TID in chip
1116  * @dd: the infinipath device
1117  * @tidptr: pointer to the expected TID (in chip) to udpate
1118  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1119  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1120  *
1121  * This exists as a separate routine to allow for special locking etc.
1122  * It's used for both the full cleanup on exit, as well as the normal
1123  * setup and teardown.
1124  */
1125 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1126                              u32 type, unsigned long pa)
1127 {
1128         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1129         unsigned long flags = 0; /* keep gcc quiet */
1130
1131         if (pa != dd->ipath_tidinvalid) {
1132                 if (pa & ((1U << 11) - 1)) {
1133                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1134                                  "not 4KB aligned!\n", pa);
1135                         return;
1136                 }
1137                 pa >>= 11;
1138                 /* paranoia check */
1139                 if (pa & (7<<29))
1140                         ipath_dev_err(dd,
1141                                       "BUG: Physical page address 0x%lx "
1142                                       "has bits set in 31-29\n", pa);
1143
1144                 if (type == RCVHQ_RCV_TYPE_EAGER)
1145                         pa |= dd->ipath_tidtemplate;
1146                 else /* for now, always full 4KB page */
1147                         pa |= 2 << 29;
1148         }
1149
1150         /* workaround chip bug 9437 by writing each TID twice
1151          * and holding a spinlock around the writes, so they don't
1152          * intermix with other TID (eager or expected) writes
1153          * Unfortunately, this call can be done from interrupt level
1154          * for the port 0 eager TIDs, so we have to use irqsave
1155          */
1156         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1157         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1158         if (dd->ipath_kregbase)
1159                 writel(pa, tidp32);
1160         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1161         mmiowb();
1162         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1163 }
1164 /**
1165  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1166  * @dd: the infinipath device
1167  * @tidptr: pointer to the expected TID (in chip) to udpate
1168  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1169  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1170  *
1171  * This exists as a separate routine to allow for selection of the
1172  * appropriate "flavor". The static calls in cleanup just use the
1173  * revision-agnostic form, as they are not performance critical.
1174  */
1175 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1176                              u32 type, unsigned long pa)
1177 {
1178         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1179
1180         if (pa != dd->ipath_tidinvalid) {
1181                 if (pa & ((1U << 11) - 1)) {
1182                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1183                                  "not 2KB aligned!\n", pa);
1184                         return;
1185                 }
1186                 pa >>= 11;
1187                 /* paranoia check */
1188                 if (pa & (7<<29))
1189                         ipath_dev_err(dd,
1190                                       "BUG: Physical page address 0x%lx "
1191                                       "has bits set in 31-29\n", pa);
1192
1193                 if (type == RCVHQ_RCV_TYPE_EAGER)
1194                         pa |= dd->ipath_tidtemplate;
1195                 else /* for now, always full 4KB page */
1196                         pa |= 2 << 29;
1197         }
1198         if (dd->ipath_kregbase)
1199                 writel(pa, tidp32);
1200         mmiowb();
1201 }
1202
1203
1204 /**
1205  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1206  * @dd: the infinipath device
1207  * @port: the port
1208  *
1209  * clear all TID entries for a port, expected and eager.
1210  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1211  * not 64, but they are still on 64 bit boundaries, so tidbase
1212  * is declared as u64 * for the pointer math, even though we write 32 bits
1213  */
1214 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1215 {
1216         u64 __iomem *tidbase;
1217         unsigned long tidinv;
1218         int i;
1219
1220         if (!dd->ipath_kregbase)
1221                 return;
1222
1223         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1224
1225         tidinv = dd->ipath_tidinvalid;
1226         tidbase = (u64 __iomem *)
1227                 ((char __iomem *)(dd->ipath_kregbase) +
1228                  dd->ipath_rcvtidbase +
1229                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1230
1231         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1232                 ipath_pe_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1233                                  tidinv);
1234
1235         tidbase = (u64 __iomem *)
1236                 ((char __iomem *)(dd->ipath_kregbase) +
1237                  dd->ipath_rcvegrbase +
1238                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1239
1240         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1241                 ipath_pe_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1242                                  tidinv);
1243 }
1244
1245 /**
1246  * ipath_pe_tidtemplate - setup constants for TID updates
1247  * @dd: the infinipath device
1248  *
1249  * We setup stuff that we use a lot, to avoid calculating each time
1250  */
1251 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1252 {
1253         u32 egrsize = dd->ipath_rcvegrbufsize;
1254
1255         /* For now, we always allocate 4KB buffers (at init) so we can
1256          * receive max size packets.  We may want a module parameter to
1257          * specify 2KB or 4KB and/or make be per port instead of per device
1258          * for those who want to reduce memory footprint.  Note that the
1259          * ipath_rcvhdrentsize size must be large enough to hold the largest
1260          * IB header (currently 96 bytes) that we expect to handle (plus of
1261          * course the 2 dwords of RHF).
1262          */
1263         if (egrsize == 2048)
1264                 dd->ipath_tidtemplate = 1U << 29;
1265         else if (egrsize == 4096)
1266                 dd->ipath_tidtemplate = 2U << 29;
1267         else {
1268                 egrsize = 4096;
1269                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1270                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1271                          egrsize);
1272                 dd->ipath_tidtemplate = 2U << 29;
1273         }
1274         dd->ipath_tidinvalid = 0;
1275 }
1276
1277 static int ipath_pe_early_init(struct ipath_devdata *dd)
1278 {
1279         dd->ipath_flags |= IPATH_4BYTE_TID;
1280
1281         /*
1282          * For openfabrics, we need to be able to handle an IB header of
1283          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1284          * made them the same size as the PIO buffers.  This chip does not
1285          * handle arbitrary size buffers, so we need the header large enough
1286          * to handle largest IB header, but still have room for a 2KB MTU
1287          * standard IB packet.
1288          */
1289         dd->ipath_rcvhdrentsize = 24;
1290         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1291
1292         /*
1293          * To truly support a 4KB MTU (for usermode), we need to
1294          * bump this to a larger value.  For now, we use them for
1295          * the kernel only.
1296          */
1297         dd->ipath_rcvegrbufsize = 2048;
1298         /*
1299          * the min() check here is currently a nop, but it may not always
1300          * be, depending on just how we do ipath_rcvegrbufsize
1301          */
1302         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1303                                  dd->ipath_rcvegrbufsize +
1304                                  (dd->ipath_rcvhdrentsize << 2));
1305         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1306
1307         /*
1308          * We can request a receive interrupt for 1 or
1309          * more packets from current offset.  For now, we set this
1310          * up for a single packet.
1311          */
1312         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1313
1314         ipath_get_eeprom_info(dd);
1315
1316         return 0;
1317 }
1318
1319 int __attribute__((weak)) ipath_unordered_wc(void)
1320 {
1321         return 0;
1322 }
1323
1324 /**
1325  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1326  * @pd: the infinipath port
1327  * @kbase: ipath_base_info pointer
1328  *
1329  * We set the PCIE flag because the lower bandwidth on PCIe vs
1330  * HyperTransport can affect some user packet algorithms.
1331  */
1332 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1333 {
1334         struct ipath_base_info *kinfo = kbase;
1335         struct ipath_devdata *dd;
1336
1337         if (ipath_unordered_wc()) {
1338                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1339                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1340         }
1341         else
1342                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1343
1344         if (pd == NULL)
1345                 goto done;
1346
1347         dd = pd->port_dd;
1348
1349 done:
1350         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1351         return 0;
1352 }
1353
1354 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1355 {
1356         free_irq(dd->ipath_irq, dd);
1357         dd->ipath_irq = 0;
1358 }
1359
1360 /*
1361  * On platforms using this chip, and not having ordered WC stores, we
1362  * can get TXE parity errors due to speculative reads to the PIO buffers,
1363  * and this, due to a chip bug can result in (many) false parity error
1364  * reports.  So it's a debug print on those, and an info print on systems
1365  * where the speculative reads don't occur.
1366  * Because we can get lots of false errors, we have no upper limit
1367  * on recovery attempts on those platforms.
1368  */
1369 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1370 {
1371         if (ipath_unordered_wc())
1372                 ipath_dbg("Recovering from TXE PIO parity error\n");
1373         else {
1374                 int cnt = ++ipath_stats.sps_txeparity;
1375                 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1376                         if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1377                                 ipath_dev_err(dd,
1378                                         "Too many attempts to recover from "
1379                                         "TXE parity, giving up\n");
1380                         return 0;
1381                 }
1382                 dev_info(&dd->pcidev->dev,
1383                         "Recovering from TXE PIO parity error\n");
1384         }
1385         return 1;
1386 }
1387
1388 /**
1389  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1390  * @dd: the infinipath device
1391  *
1392  * This is global, and is called directly at init to set up the
1393  * chip-specific function pointers for later use.
1394  */
1395 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1396 {
1397         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1398         dd->ipath_f_bus = ipath_setup_pe_config;
1399         dd->ipath_f_reset = ipath_setup_pe_reset;
1400         dd->ipath_f_get_boardname = ipath_pe_boardname;
1401         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1402         dd->ipath_f_early_init = ipath_pe_early_init;
1403         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1404         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1405         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1406         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1407         if (dd->ipath_minrev >= 2)
1408                 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1409         else
1410                 dd->ipath_f_put_tid = ipath_pe_put_tid;
1411         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1412         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1413         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1414         dd->ipath_f_free_irq = ipath_pe_free_irq;
1415
1416         /* initialize chip-specific variables */
1417         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1418
1419         /*
1420          * setup the register offsets, since they are different for each
1421          * chip
1422          */
1423         dd->ipath_kregs = &ipath_pe_kregs;
1424         dd->ipath_cregs = &ipath_pe_cregs;
1425
1426         ipath_init_pe_variables(dd);
1427 }
1428