2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * This file contains all of the code that is specific to the
35 * InfiniPath PCIe chip.
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
43 #include "ipath_kernel.h"
44 #include "ipath_registers.h"
46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
49 * This file contains all the chip-specific register information and
50 * access functions for the QLogic InfiniPath PCI-Express chip.
52 * This lists the InfiniPath registers, in the actual chip layout.
53 * This structure should never be directly accessed.
55 struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
148 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
149 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
150 #define IPATH_CREG_OFFSET(field) (offsetof( \
151 struct infinipath_counters, field) / sizeof(u64))
153 static const struct ipath_kregs ipath_pe_kregs = {
154 .kr_control = IPATH_KREG_OFFSET(Control),
155 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
156 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
157 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
158 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
159 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
160 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
161 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
162 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
163 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
164 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
165 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
166 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
167 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
168 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
169 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
170 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
171 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
172 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
173 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
174 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
175 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
176 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
177 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
178 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
179 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
180 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
181 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
182 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
183 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
184 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
185 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
186 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
187 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
188 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
189 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
190 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
191 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
192 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
193 .kr_revision = IPATH_KREG_OFFSET(Revision),
194 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
195 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
196 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
197 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
198 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
199 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
200 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
201 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
202 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
203 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
204 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
205 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
206 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
207 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
208 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
209 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
212 * These should not be used directly via ipath_write_kreg64(),
213 * use them with ipath_write_kreg64_port(),
215 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
216 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
218 /* The rcvpktled register controls one of the debug port signals, so
219 * a packet activity LED can be connected to it. */
220 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
221 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
222 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
223 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
224 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
225 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
226 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
227 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
228 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
231 static const struct ipath_cregs ipath_pe_cregs = {
232 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
233 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
234 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
235 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
236 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
237 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
238 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
239 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
240 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
241 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
242 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
243 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
244 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
245 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
246 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
247 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
248 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
249 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
250 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
251 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
252 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
253 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
254 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
255 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
256 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
257 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
258 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
259 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
260 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
261 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
262 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
263 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
264 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
267 /* kr_intstatus, kr_intclear, kr_intmask bits */
268 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
269 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
271 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
272 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
273 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
274 #define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
275 #define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
276 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
277 #define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
278 #define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
279 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
280 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
281 #define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
282 #define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
283 #define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
285 /* kr_extstatus bits */
286 #define INFINIPATH_EXTS_FREQSEL 0x2
287 #define INFINIPATH_EXTS_SERDESSEL 0x4
288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
289 #define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
291 #define _IPATH_GPIO_SDA_NUM 1
292 #define _IPATH_GPIO_SCL_NUM 0
294 #define IPATH_GPIO_SDA (1ULL << \
295 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
296 #define IPATH_GPIO_SCL (1ULL << \
297 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
299 /* 6120 specific hardware errors... */
300 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
301 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
302 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
304 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
305 * parity or memory parity error failures, because most likely we
306 * won't be able to talk to the core of the chip. Nonetheless, we
307 * might see them, if they are in parts of the PCIe core that aren't
310 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
311 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
312 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
313 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
314 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
315 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
316 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
319 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
320 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
321 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
323 static int ipath_pe_txe_recover(struct ipath_devdata *);
326 * ipath_pe_handle_hwerrors - display hardware errors.
327 * @dd: the infinipath device
328 * @msg: the output buffer
329 * @msgl: the size of the output buffer
331 * Use same msg buffer as regular errors to avoid excessive stack
332 * use. Most hardware errors are catastrophic, but for right now,
333 * we'll print them and continue. We reuse the same message buffer as
334 * ipath_handle_errors() to avoid excessive stack usage.
336 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
345 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
348 * better than printing cofusing messages
349 * This seems to be related to clearing the crc error, or
350 * the pll error during init.
352 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
354 } else if (hwerrs == ~0ULL) {
355 ipath_dev_err(dd, "Read of hardware error status failed "
356 "(all bits set); ignoring\n");
359 ipath_stats.sps_hwerrs++;
361 /* Always clear the error status register, except MEMBISTFAIL,
362 * regardless of whether we continue or stop using the chip.
363 * We want that set so we know it failed, even across driver reload.
364 * We'll still ignore it in the hwerrmask. We do this partly for
365 * diagnostics, but also for support */
366 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
367 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
369 hwerrs &= dd->ipath_hwerrmask;
371 /* We log some errors to EEPROM, check if we have any of those. */
372 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
373 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
374 ipath_inc_eeprom_err(dd, log_idx, 1);
377 * make sure we get this much out, unless told to be quiet,
378 * or it's occurred within the last 5 seconds
380 if ((hwerrs & ~(dd->ipath_lasthwerror |
381 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
382 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
383 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
384 (ipath_debug & __IPATH_VERBDBG))
385 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
386 "(cleared)\n", (unsigned long long) hwerrs);
387 dd->ipath_lasthwerror |= hwerrs;
389 if (hwerrs & ~dd->ipath_hwe_bitsextant)
390 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
391 "%llx set\n", (unsigned long long)
392 (hwerrs & ~dd->ipath_hwe_bitsextant));
394 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
395 if (ctrl & INFINIPATH_C_FREEZEMODE) {
397 * parity errors in send memory are recoverable,
398 * just cancel the send (if indicated in * sendbuffererror),
399 * count the occurrence, unfreeze (if no other handled
400 * hardware error bits are set), and continue. They can
401 * occur if a processor speculative read is done to the PIO
402 * buffer while we are sending a packet, for example.
404 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
405 hwerrs &= ~TXE_PIO_PARITY;
408 * if any set that we aren't ignoring only make the
409 * complaint once, in case it's stuck or recurring,
410 * and we get here multiple times
411 * Force link down, so switch knows, and
412 * LEDs are turned off
414 if (dd->ipath_flags & IPATH_INITTED) {
415 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
416 ipath_setup_pe_setextled(dd,
417 INFINIPATH_IBCS_L_STATE_DOWN,
418 INFINIPATH_IBCS_LT_STATE_DISABLED);
419 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
420 "mode), no longer usable, SN %.16s\n",
425 * Mark as having had an error for driver, and also
426 * for /sys and status word mapped to user programs.
427 * This marks unit as not usable, until reset
429 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
430 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
431 dd->ipath_flags &= ~IPATH_INITTED;
433 ipath_dbg("Clearing freezemode on ignored hardware "
435 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
442 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
443 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
445 /* ignore from now on, so disable until driver reloaded */
446 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
447 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
448 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
449 dd->ipath_hwerrmask);
452 ipath_format_hwerrors(hwerrs,
453 ipath_6120_hwerror_msgs,
454 sizeof(ipath_6120_hwerror_msgs)/
455 sizeof(ipath_6120_hwerror_msgs[0]),
458 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
459 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
460 bits = (u32) ((hwerrs >>
461 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
462 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
463 snprintf(bitsmsg, sizeof bitsmsg,
464 "[PCIe Mem Parity Errs %x] ", bits);
465 strlcat(msg, bitsmsg, msgl);
468 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
469 INFINIPATH_HWE_COREPLL_RFSLIP )
471 if (hwerrs & _IPATH_PLL_FAIL) {
472 snprintf(bitsmsg, sizeof bitsmsg,
473 "[PLL failed (%llx), InfiniPath hardware unusable]",
474 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
475 strlcat(msg, bitsmsg, msgl);
476 /* ignore from now on, so disable until driver reloaded */
477 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
478 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
479 dd->ipath_hwerrmask);
482 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
484 * If it occurs, it is left masked since the eternal
485 * interface is unused
487 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
488 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
489 dd->ipath_hwerrmask);
493 ipath_dev_err(dd, "%s hardware error\n", msg);
494 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
496 * for /sys status file ; if no trailing } is copied, we'll
497 * know it was truncated.
499 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
505 * ipath_pe_boardname - fill in the board name
506 * @dd: the infinipath device
507 * @name: the output buffer
508 * @namelen: the size of the output buffer
510 * info is based on the board revision register
512 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
516 u8 boardrev = dd->ipath_boardrev;
521 n = "InfiniPath_Emulation";
524 n = "InfiniPath_QLE7140-Bringup";
527 n = "InfiniPath_QLE7140";
530 n = "InfiniPath_QMI7140";
533 n = "InfiniPath_QEM7140";
536 n = "InfiniPath_QMH7140";
539 n = "InfiniPath_QLE7142";
543 "Don't yet know about board with ID %u\n",
545 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
550 snprintf(name, namelen, "%s", n);
552 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
553 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
554 dd->ipath_majrev, dd->ipath_minrev);
563 * ipath_pe_init_hwerrors - enable hardware errors
564 * @dd: the infinipath device
566 * now that we have finished initializing everything that might reasonably
567 * cause a hardware error, and cleared those errors bits as they occur,
568 * we can enable hardware errors in the mask (potentially enabling
569 * freeze mode), and enable hardware errors as errors (along with
570 * everything else) in errormask
572 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
577 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
579 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
580 ipath_dev_err(dd, "MemBIST did not complete!\n");
581 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
582 ipath_dbg("MemBIST corrected\n");
584 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
586 if (!dd->ipath_boardrev) // no PLL for Emulator
587 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
589 if (dd->ipath_minrev < 2) {
590 /* workaround bug 9460 in internal interface bus parity
591 * checking. Fixed (HW bug 9490) in Rev2.
593 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
595 dd->ipath_hwerrmask = val;
599 * ipath_pe_bringup_serdes - bring up the serdes
600 * @dd: the infinipath device
602 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
604 u64 val, config1, prev_val;
607 ipath_dbg("Trying to bringup serdes\n");
609 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
610 INFINIPATH_HWE_SERDESPLLFAILED) {
611 ipath_dbg("At start, serdes PLL failed bit set "
612 "in hwerrstatus, clearing and continuing\n");
613 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
614 INFINIPATH_HWE_SERDESPLLFAILED);
617 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
618 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
620 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
621 "xgxsconfig %llx\n", (unsigned long long) val,
622 (unsigned long long) config1, (unsigned long long)
623 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
626 * Force reset on, also set rxdetect enable. Must do before reading
627 * serdesstatus at least for simulation, or some of the bits in
628 * serdes status will come back as undefined and cause simulation
631 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
632 | INFINIPATH_SERDC0_L1PWR_DN;
633 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
634 /* be sure chip saw it */
635 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
636 udelay(5); /* need pll reset set at least for a bit */
638 * after PLL is reset, set the per-lane Resets and TxIdle and
639 * clear the PLL reset and rxdetect (to get falling edge).
640 * Leave L1PWR bits set (permanently)
642 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
643 | INFINIPATH_SERDC0_L1PWR_DN);
644 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
645 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
646 "and txidle (%llx)\n", (unsigned long long) val);
647 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
648 /* be sure chip saw it */
649 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
650 /* need PLL reset clear for at least 11 usec before lane
651 * resets cleared; give it a few more to be sure */
653 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
655 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
656 "(writing %llx)\n", (unsigned long long) val);
657 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
658 /* be sure chip saw it */
659 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
661 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
663 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
664 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
666 ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
667 INFINIPATH_XGXS_MDIOADDR_SHIFT);
669 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
671 if (val & INFINIPATH_XGXS_RESET) {
672 val &= ~INFINIPATH_XGXS_RESET;
674 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
675 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
676 /* need to compensate for Tx inversion in partner */
677 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
678 INFINIPATH_XGXS_RX_POL_SHIFT);
679 val |= dd->ipath_rx_pol_inv <<
680 INFINIPATH_XGXS_RX_POL_SHIFT;
683 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
685 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
687 /* clear current and de-emphasis bits */
688 config1 &= ~0x0ffffffff00ULL;
689 /* set current to 20ma */
690 config1 |= 0x00000000000ULL;
691 /* set de-emphasis to -5.68dB */
692 config1 |= 0x0cccc000000ULL;
693 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
695 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
696 "config1=%llx, sstatus=%llx xgxs=%llx\n",
697 (unsigned long long) val, (unsigned long long) config1,
699 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
701 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
703 if (!ipath_waitfor_mdio_cmdready(dd)) {
705 dd, dd->ipath_kregs->kr_mdio,
706 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
707 IPATH_MDIO_CTRL_XGXS_REG_8, 0));
708 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
709 IPATH_MDIO_DATAVALID, &val))
710 ipath_dbg("Never got MDIO data for XGXS "
713 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
714 "'bank' 31 %x\n", (u32) val);
716 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
722 * ipath_pe_quiet_serdes - set serdes to txidle
723 * @dd: the infinipath device
724 * Called when driver is being unloaded
726 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
728 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
730 val |= INFINIPATH_SERDC0_TXIDLE;
731 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
732 (unsigned long long) val);
733 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
736 static int ipath_pe_intconfig(struct ipath_devdata *dd)
741 * If the chip supports added error indication via GPIO pins,
742 * enable interrupts on those bits so the interrupt routine
743 * can count the events. Also set flag so interrupt routine
744 * can know they are expected.
746 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
747 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
748 /* Rev2+ reports extra errors via internal GPIO pins */
749 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
750 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
751 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
752 dd->ipath_gpio_mask);
758 * ipath_setup_pe_setextled - set the state of the two external LEDs
759 * @dd: the infinipath device
761 * @ltst: the LT state
763 * These LEDs indicate the physical and logical state of IB link.
764 * For this chip (at least with recommended board pinouts), LED1
765 * is Yellow (logical state) and LED2 is Green (physical state),
767 * Note: We try to match the Mellanox HCA LED behavior as best
768 * we can. Green indicates physical link state is OK (something is
769 * plugged in, and we can train).
770 * Amber indicates the link is logically up (ACTIVE).
771 * Mellanox further blinks the amber LED to indicate data packet
772 * activity, but we have no hardware support for that, so it would
773 * require waking up every 10-20 msecs and checking the counters
774 * on the chip, and then turning the LED off if appropriate. That's
775 * visible overhead, so not something we will do.
778 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
782 unsigned long flags = 0;
784 /* the diags use the LED to indicate diag info, so we leave
785 * the external LED alone when the diags are running */
786 if (ipath_diag_inuse)
789 /* Allow override of LED display for, e.g. Locating system in rack */
790 if (dd->ipath_led_override) {
791 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
792 ? INFINIPATH_IBCS_LT_STATE_LINKUP
793 : INFINIPATH_IBCS_LT_STATE_DISABLED;
794 lst = (dd->ipath_led_override & IPATH_LED_LOG)
795 ? INFINIPATH_IBCS_L_STATE_ACTIVE
796 : INFINIPATH_IBCS_L_STATE_DOWN;
799 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
800 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
801 INFINIPATH_EXTC_LED2PRIPORT_ON);
803 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
804 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
805 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
806 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
807 dd->ipath_extctrl = extctl;
808 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
809 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
813 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
814 * @dd: the infinipath device
816 * This is called during driver unload.
817 * We do the pci_disable_msi here, not in generic code, because it
818 * isn't used for the HT chips. If we do end up needing pci_enable_msi
819 * at some point in the future for HT, we'll move the call back
820 * into the main init_one code.
822 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
824 dd->ipath_msi_lo = 0; /* just in case unload fails */
825 pci_disable_msi(dd->pcidev);
829 * ipath_setup_pe_config - setup PCIe config related stuff
830 * @dd: the infinipath device
831 * @pdev: the PCI device
833 * The pci_enable_msi() call will fail on systems with MSI quirks
834 * such as those with AMD8131, even if the device of interest is not
835 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
837 * All that can be done is to edit the kernel source to remove the quirk
838 * check until that is fixed.
839 * We do not need to call enable_msi() for our HyperTransport chip,
840 * even though it uses MSI, and we want to avoid the quirk warning, so
841 * So we call enable_msi only for PCIe. If we do end up needing
842 * pci_enable_msi at some point in the future for HT, we'll move the
843 * call back into the main init_one code.
844 * We save the msi lo and hi values, so we can restore them after
845 * chip reset (the kernel PCI infrastructure doesn't yet handle that
848 static int ipath_setup_pe_config(struct ipath_devdata *dd,
849 struct pci_dev *pdev)
853 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
854 ret = pci_enable_msi(dd->pcidev);
856 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
857 "interrupts may not work\n", ret);
858 /* continue even if it fails, we may still be OK... */
859 dd->ipath_irq = pdev->irq;
861 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
863 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
865 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
867 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
869 /* now save the data (vector) info */
870 pci_read_config_word(dd->pcidev,
871 pos + ((control & PCI_MSI_FLAGS_64BIT)
873 &dd->ipath_msi_data);
874 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
875 "0x%x, control=0x%x\n", dd->ipath_msi_data,
876 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
878 /* we save the cachelinesize also, although it doesn't
880 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
881 &dd->ipath_pci_cacheline);
883 ipath_dev_err(dd, "Can't find MSI capability, "
884 "can't save MSI settings for reset\n");
885 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
887 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
892 ipath_dev_err(dd, "PCIe width %u, "
893 "performance reduced\n", linkstat);
896 ipath_dev_err(dd, "Can't find PCI Express "
901 static void ipath_init_pe_variables(struct ipath_devdata *dd)
904 * bits for selecting i2c direction and values,
905 * used for I2C serial flash
907 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
908 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
909 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
910 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
912 /* variables for sanity checking interrupt and errors */
913 dd->ipath_hwe_bitsextant =
914 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
915 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
916 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
917 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
918 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
919 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
920 INFINIPATH_HWE_PCIE1PLLFAILED |
921 INFINIPATH_HWE_PCIE0PLLFAILED |
922 INFINIPATH_HWE_PCIEPOISONEDTLP |
923 INFINIPATH_HWE_PCIECPLTIMEOUT |
924 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
925 INFINIPATH_HWE_PCIEBUSPARITYXADM |
926 INFINIPATH_HWE_PCIEBUSPARITYRADM |
927 INFINIPATH_HWE_MEMBISTFAILED |
928 INFINIPATH_HWE_COREPLL_FBSLIP |
929 INFINIPATH_HWE_COREPLL_RFSLIP |
930 INFINIPATH_HWE_SERDESPLLFAILED |
931 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
932 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
933 dd->ipath_i_bitsextant =
934 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
935 (INFINIPATH_I_RCVAVAIL_MASK <<
936 INFINIPATH_I_RCVAVAIL_SHIFT) |
937 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
938 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
939 dd->ipath_e_bitsextant =
940 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
941 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
942 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
943 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
944 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
945 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
946 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
947 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
948 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
949 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
950 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
951 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
952 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
953 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
954 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
955 INFINIPATH_E_HARDWARE;
957 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
958 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
961 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
962 * 2 is Some Misc, 3 is reserved for future.
964 dd->ipath_eep_st_masks[0].hwerrs_to_log =
965 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
966 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
968 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
969 if (ipath_unordered_wc())
970 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
972 dd->ipath_eep_st_masks[1].hwerrs_to_log =
973 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
974 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
976 dd->ipath_eep_st_masks[2].errs_to_log =
977 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
982 /* setup the MSI stuff again after a reset. I'd like to just call
983 * pci_enable_msi() and request_irq() again, but when I do that,
984 * the MSI enable bit doesn't get set in the command word, and
985 * we switch to to a different interrupt vector, which is confusing,
986 * so I instead just do it all inline. Perhaps somehow can tie this
987 * into the PCIe hotplug support at some point
988 * Note, because I'm doing it all here, I don't call pci_disable_msi()
989 * or free_irq() at the start of ipath_setup_pe_reset().
991 static int ipath_reinit_msi(struct ipath_devdata *dd)
997 if (!dd->ipath_msi_lo) {
998 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
999 "initial setup failed?\n");
1004 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1005 ipath_dev_err(dd, "Can't find MSI capability, "
1006 "can't restore MSI settings\n");
1010 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1011 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1012 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1014 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1015 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1016 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1018 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1019 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1020 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1021 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1022 control, control | PCI_MSI_FLAGS_ENABLE);
1023 control |= PCI_MSI_FLAGS_ENABLE;
1024 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1027 /* now rewrite the data (vector) info */
1028 pci_write_config_word(dd->pcidev, pos +
1029 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1030 dd->ipath_msi_data);
1031 /* we restore the cachelinesize also, although it doesn't really
1033 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1034 dd->ipath_pci_cacheline);
1035 /* and now set the pci master bit again */
1036 pci_set_master(dd->pcidev);
1043 /* This routine sleeps, so it can only be called from user context, not
1044 * from interrupt context. If we need interrupt context, we can split
1045 * it into two routines.
1047 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1053 /* Use ERROR so it shows up in logs, etc. */
1054 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1055 /* keep chip from being accessed in a few places */
1056 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1057 val = dd->ipath_control | INFINIPATH_C_RESET;
1058 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1061 for (i = 1; i <= 5; i++) {
1063 /* allow MBIST, etc. to complete; longer on each retry.
1064 * We sometimes get machine checks from bus timeout if no
1065 * response, so for now, make it *really* long.
1067 msleep(1000 + (1 + i) * 2000);
1069 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1070 dd->ipath_pcibar0)))
1071 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1074 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1075 dd->ipath_pcibar1)))
1076 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1078 /* now re-enable memory access */
1079 if ((r = pci_enable_device(dd->pcidev)))
1080 ipath_dev_err(dd, "pci_enable_device failed after "
1082 /* whether it worked or not, mark as present, again */
1083 dd->ipath_flags |= IPATH_PRESENT;
1084 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1085 if (val == dd->ipath_revision) {
1086 ipath_cdbg(VERBOSE, "Got matching revision "
1087 "register %llx on try %d\n",
1088 (unsigned long long) val, i);
1089 ret = ipath_reinit_msi(dd);
1092 /* Probably getting -1 back */
1093 ipath_dbg("Didn't get expected revision register, "
1094 "got %llx, try %d\n", (unsigned long long) val,
1097 ret = 0; /* failed */
1104 * ipath_pe_put_tid - write a TID in chip
1105 * @dd: the infinipath device
1106 * @tidptr: pointer to the expected TID (in chip) to udpate
1107 * @tidtype: 0 for eager, 1 for expected
1108 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1110 * This exists as a separate routine to allow for special locking etc.
1111 * It's used for both the full cleanup on exit, as well as the normal
1112 * setup and teardown.
1114 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1115 u32 type, unsigned long pa)
1117 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1118 unsigned long flags = 0; /* keep gcc quiet */
1120 if (pa != dd->ipath_tidinvalid) {
1121 if (pa & ((1U << 11) - 1)) {
1122 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1123 "not 4KB aligned!\n", pa);
1127 /* paranoia check */
1130 "BUG: Physical page address 0x%lx "
1131 "has bits set in 31-29\n", pa);
1134 pa |= dd->ipath_tidtemplate;
1135 else /* for now, always full 4KB page */
1139 /* workaround chip bug 9437 by writing each TID twice
1140 * and holding a spinlock around the writes, so they don't
1141 * intermix with other TID (eager or expected) writes
1142 * Unfortunately, this call can be done from interrupt level
1143 * for the port 0 eager TIDs, so we have to use irqsave
1145 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1146 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1147 if (dd->ipath_kregbase)
1149 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1151 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1154 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1155 * @dd: the infinipath device
1156 * @tidptr: pointer to the expected TID (in chip) to udpate
1157 * @tidtype: 0 for eager, 1 for expected
1158 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1160 * This exists as a separate routine to allow for selection of the
1161 * appropriate "flavor". The static calls in cleanup just use the
1162 * revision-agnostic form, as they are not performance critical.
1164 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1165 u32 type, unsigned long pa)
1167 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1169 if (pa != dd->ipath_tidinvalid) {
1170 if (pa & ((1U << 11) - 1)) {
1171 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1172 "not 2KB aligned!\n", pa);
1176 /* paranoia check */
1179 "BUG: Physical page address 0x%lx "
1180 "has bits set in 31-29\n", pa);
1183 pa |= dd->ipath_tidtemplate;
1184 else /* for now, always full 4KB page */
1187 if (dd->ipath_kregbase)
1194 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1195 * @dd: the infinipath device
1198 * clear all TID entries for a port, expected and eager.
1199 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1200 * not 64, but they are still on 64 bit boundaries, so tidbase
1201 * is declared as u64 * for the pointer math, even though we write 32 bits
1203 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1205 u64 __iomem *tidbase;
1206 unsigned long tidinv;
1209 if (!dd->ipath_kregbase)
1212 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1214 tidinv = dd->ipath_tidinvalid;
1215 tidbase = (u64 __iomem *)
1216 ((char __iomem *)(dd->ipath_kregbase) +
1217 dd->ipath_rcvtidbase +
1218 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1220 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1221 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1223 tidbase = (u64 __iomem *)
1224 ((char __iomem *)(dd->ipath_kregbase) +
1225 dd->ipath_rcvegrbase +
1226 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1228 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1229 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1233 * ipath_pe_tidtemplate - setup constants for TID updates
1234 * @dd: the infinipath device
1236 * We setup stuff that we use a lot, to avoid calculating each time
1238 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1240 u32 egrsize = dd->ipath_rcvegrbufsize;
1242 /* For now, we always allocate 4KB buffers (at init) so we can
1243 * receive max size packets. We may want a module parameter to
1244 * specify 2KB or 4KB and/or make be per port instead of per device
1245 * for those who want to reduce memory footprint. Note that the
1246 * ipath_rcvhdrentsize size must be large enough to hold the largest
1247 * IB header (currently 96 bytes) that we expect to handle (plus of
1248 * course the 2 dwords of RHF).
1250 if (egrsize == 2048)
1251 dd->ipath_tidtemplate = 1U << 29;
1252 else if (egrsize == 4096)
1253 dd->ipath_tidtemplate = 2U << 29;
1256 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1257 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1259 dd->ipath_tidtemplate = 2U << 29;
1261 dd->ipath_tidinvalid = 0;
1264 static int ipath_pe_early_init(struct ipath_devdata *dd)
1266 dd->ipath_flags |= IPATH_4BYTE_TID;
1269 * For openfabrics, we need to be able to handle an IB header of
1270 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1271 * made them the same size as the PIO buffers. This chip does not
1272 * handle arbitrary size buffers, so we need the header large enough
1273 * to handle largest IB header, but still have room for a 2KB MTU
1274 * standard IB packet.
1276 dd->ipath_rcvhdrentsize = 24;
1277 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1280 * To truly support a 4KB MTU (for usermode), we need to
1281 * bump this to a larger value. For now, we use them for
1284 dd->ipath_rcvegrbufsize = 2048;
1286 * the min() check here is currently a nop, but it may not always
1287 * be, depending on just how we do ipath_rcvegrbufsize
1289 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1290 dd->ipath_rcvegrbufsize +
1291 (dd->ipath_rcvhdrentsize << 2));
1292 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1295 * We can request a receive interrupt for 1 or
1296 * more packets from current offset. For now, we set this
1297 * up for a single packet.
1299 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1301 ipath_get_eeprom_info(dd);
1306 int __attribute__((weak)) ipath_unordered_wc(void)
1312 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1313 * @pd: the infinipath port
1314 * @kbase: ipath_base_info pointer
1316 * We set the PCIE flag because the lower bandwidth on PCIe vs
1317 * HyperTransport can affect some user packet algorithms.
1319 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1321 struct ipath_base_info *kinfo = kbase;
1322 struct ipath_devdata *dd;
1324 if (ipath_unordered_wc()) {
1325 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1326 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1329 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1337 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1341 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1343 free_irq(dd->ipath_irq, dd);
1348 * On platforms using this chip, and not having ordered WC stores, we
1349 * can get TXE parity errors due to speculative reads to the PIO buffers,
1350 * and this, due to a chip bug can result in (many) false parity error
1351 * reports. So it's a debug print on those, and an info print on systems
1352 * where the speculative reads don't occur.
1353 * Because we can get lots of false errors, we have no upper limit
1354 * on recovery attempts on those platforms.
1356 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1358 if (ipath_unordered_wc())
1359 ipath_dbg("Recovering from TXE PIO parity error\n");
1361 int cnt = ++ipath_stats.sps_txeparity;
1362 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1363 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1365 "Too many attempts to recover from "
1366 "TXE parity, giving up\n");
1369 dev_info(&dd->pcidev->dev,
1370 "Recovering from TXE PIO parity error\n");
1372 ipath_disarm_senderrbufs(dd, 1);
1377 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1378 * @dd: the infinipath device
1380 * This is global, and is called directly at init to set up the
1381 * chip-specific function pointers for later use.
1383 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1385 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1386 dd->ipath_f_bus = ipath_setup_pe_config;
1387 dd->ipath_f_reset = ipath_setup_pe_reset;
1388 dd->ipath_f_get_boardname = ipath_pe_boardname;
1389 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1390 dd->ipath_f_early_init = ipath_pe_early_init;
1391 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1392 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1393 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1394 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1395 if (dd->ipath_minrev >= 2)
1396 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1398 dd->ipath_f_put_tid = ipath_pe_put_tid;
1399 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1400 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1401 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1402 dd->ipath_f_free_irq = ipath_pe_free_irq;
1404 /* initialize chip-specific variables */
1405 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1408 * setup the register offsets, since they are different for each
1411 dd->ipath_kregs = &ipath_pe_kregs;
1412 dd->ipath_cregs = &ipath_pe_cregs;
1414 ipath_init_pe_variables(dd);