drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <ib_verbs.h>
  38 #include <ib_cache.h>
  39 #include <ib_pack.h>
  40
  41 #include "mthca_dev.h"
  42 #include "mthca_cmd.h"
  43 #include "mthca_memfree.h"
  44
  45 enum {
  46         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  47         MTHCA_ACK_REQ_FREQ       = 10,
  48         MTHCA_FLIGHT_LIMIT       = 9,
  49         MTHCA_UD_HEADER_SIZE     = 72 /* largest UD header possible */
  50 };
  51
  52 enum {
  53         MTHCA_QP_STATE_RST  = 0,
  54         MTHCA_QP_STATE_INIT = 1,
  55         MTHCA_QP_STATE_RTR  = 2,
  56         MTHCA_QP_STATE_RTS  = 3,
  57         MTHCA_QP_STATE_SQE  = 4,
  58         MTHCA_QP_STATE_SQD  = 5,
  59         MTHCA_QP_STATE_ERR  = 6,
  60         MTHCA_QP_STATE_DRAINING = 7
  61 };
  62
  63 enum {
  64         MTHCA_QP_ST_RC  = 0x0,
  65         MTHCA_QP_ST_UC  = 0x1,
  66         MTHCA_QP_ST_RD  = 0x2,
  67         MTHCA_QP_ST_UD  = 0x3,
  68         MTHCA_QP_ST_MLX = 0x7
  69 };
  70
  71 enum {
  72         MTHCA_QP_PM_MIGRATED = 0x3,
  73         MTHCA_QP_PM_ARMED    = 0x0,
  74         MTHCA_QP_PM_REARM    = 0x1
  75 };
  76
  77 enum {
  78         /* qp_context flags */
  79         MTHCA_QP_BIT_DE  = 1 <<  8,
  80         /* params1 */
  81         MTHCA_QP_BIT_SRE = 1 << 15,
  82         MTHCA_QP_BIT_SWE = 1 << 14,
  83         MTHCA_QP_BIT_SAE = 1 << 13,
  84         MTHCA_QP_BIT_SIC = 1 <<  4,
  85         MTHCA_QP_BIT_SSC = 1 <<  3,
  86         /* params2 */
  87         MTHCA_QP_BIT_RRE = 1 << 15,
  88         MTHCA_QP_BIT_RWE = 1 << 14,
  89         MTHCA_QP_BIT_RAE = 1 << 13,
  90         MTHCA_QP_BIT_RIC = 1 <<  4,
  91         MTHCA_QP_BIT_RSC = 1 <<  3
  92 };
  93
  94 struct mthca_qp_path {
  95         u32 port_pkey;
  96         u8  rnr_retry;
  97         u8  g_mylmc;
  98         u16 rlid;
  99         u8  ackto;
 100         u8  mgid_index;
 101         u8  static_rate;
 102         u8  hop_limit;
 103         u32 sl_tclass_flowlabel;
 104         u8  rgid[16];
 105 } __attribute__((packed));
 106
 107 struct mthca_qp_context {
 108         u32 flags;
 109         u32 tavor_sched_queue;  /* Reserved on Arbel */
 110         u8  mtu_msgmax;
 111         u8  rq_size_stride;     /* Reserved on Tavor */
 112         u8  sq_size_stride;     /* Reserved on Tavor */
 113         u8  rlkey_arbel_sched_queue;    /* Reserved on Tavor */
 114         u32 usr_page;
 115         u32 local_qpn;
 116         u32 remote_qpn;
 117         u32 reserved1[2];
 118         struct mthca_qp_path pri_path;
 119         struct mthca_qp_path alt_path;
 120         u32 rdd;
 121         u32 pd;
 122         u32 wqe_base;
 123         u32 wqe_lkey;
 124         u32 params1;
 125         u32 reserved2;
 126         u32 next_send_psn;
 127         u32 cqn_snd;
 128         u32 snd_wqe_base_l;     /* Next send WQE on Tavor */
 129         u32 snd_db_index;       /* (debugging only entries) */
 130         u32 last_acked_psn;
 131         u32 ssn;
 132         u32 params2;
 133         u32 rnr_nextrecvpsn;
 134         u32 ra_buff_indx;
 135         u32 cqn_rcv;
 136         u32 rcv_wqe_base_l;     /* Next recv WQE on Tavor */
 137         u32 rcv_db_index;       /* (debugging only entries) */
 138         u32 qkey;
 139         u32 srqn;
 140         u32 rmsn;
 141         u16 rq_wqe_counter;     /* reserved on Tavor */
 142         u16 sq_wqe_counter;     /* reserved on Tavor */
 143         u32 reserved3[18];
 144 } __attribute__((packed));
 145
 146 struct mthca_qp_param {
 147         u32 opt_param_mask;
 148         u32 reserved1;
 149         struct mthca_qp_context context;
 150         u32 reserved2[62];
 151 } __attribute__((packed));
 152
 153 enum {
 154         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 155         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 156         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 157         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 158         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 159         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 160         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 161         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 162         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 163         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 164         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 165         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 166         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 167         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 168         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 169         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 170         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 171 };
 172
 173 enum {
 174         MTHCA_NEXT_DBD       = 1 << 7,
 175         MTHCA_NEXT_FENCE     = 1 << 6,
 176         MTHCA_NEXT_CQ_UPDATE = 1 << 3,
 177         MTHCA_NEXT_EVENT_GEN = 1 << 2,
 178         MTHCA_NEXT_SOLICIT   = 1 << 1,
 179
 180         MTHCA_MLX_VL15       = 1 << 17,
 181         MTHCA_MLX_SLR        = 1 << 16
 182 };
 183
 184 enum {
 185         MTHCA_INVAL_LKEY = 0x100
 186 };
 187
 188 struct mthca_next_seg {
 189         u32 nda_op;             /* [31:6] next WQE [4:0] next opcode */
 190         u32 ee_nds;             /* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
 191         u32 flags;              /* [3] CQ [2] Event [1] Solicit */
 192         u32 imm;                /* immediate data */
 193 };
 194
 195 struct mthca_tavor_ud_seg {
 196         u32 reserved1;
 197         u32 lkey;
 198         u64 av_addr;
 199         u32 reserved2[4];
 200         u32 dqpn;
 201         u32 qkey;
 202         u32 reserved3[2];
 203 };
 204
 205 struct mthca_arbel_ud_seg {
 206         u32 av[8];
 207         u32 dqpn;
 208         u32 qkey;
 209         u32 reserved[2];
 210 };
 211
 212 struct mthca_bind_seg {
 213         u32 flags;              /* [31] Atomic [30] rem write [29] rem read */
 214         u32 reserved;
 215         u32 new_rkey;
 216         u32 lkey;
 217         u64 addr;
 218         u64 length;
 219 };
 220
 221 struct mthca_raddr_seg {
 222         u64 raddr;
 223         u32 rkey;
 224         u32 reserved;
 225 };
 226
 227 struct mthca_atomic_seg {
 228         u64 swap_add;
 229         u64 compare;
 230 };
 231
 232 struct mthca_data_seg {
 233         u32 byte_count;
 234         u32 lkey;
 235         u64 addr;
 236 };
 237
 238 struct mthca_mlx_seg {
 239         u32 nda_op;
 240         u32 nds;
 241         u32 flags;              /* [17] VL15 [16] SLR [14:12] static rate
 242                                    [11:8] SL [3] C [2] E */
 243         u16 rlid;
 244         u16 vcrc;
 245 };
 246
 247 static const u8 mthca_opcode[] = {
 248         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 249         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 250         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 251         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 252         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 253         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 254         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 255 };
 256
 257 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 258 {
 259         return qp->qpn >= dev->qp_table.sqp_start &&
 260                 qp->qpn <= dev->qp_table.sqp_start + 3;
 261 }
 262
 263 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 264 {
 265         return qp->qpn >= dev->qp_table.sqp_start &&
 266                 qp->qpn <= dev->qp_table.sqp_start + 1;
 267 }
 268
 269 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 270 {
 271         if (qp->is_direct)
 272                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 273         else
 274                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 275                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 276 }
 277
 278 static void *get_send_wqe(struct mthca_qp *qp, int n)
 279 {
 280         if (qp->is_direct)
 281                 return qp->queue.direct.buf + qp->send_wqe_offset +
 282                         (n << qp->sq.wqe_shift);
 283         else
 284                 return qp->queue.page_list[(qp->send_wqe_offset +
 285                                             (n << qp->sq.wqe_shift)) >>
 286                                            PAGE_SHIFT].buf +
 287                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 288                          (PAGE_SIZE - 1));
 289 }
 290
 291 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 292                     enum ib_event_type event_type)
 293 {
 294         struct mthca_qp *qp;
 295         struct ib_event event;
 296
 297         spin_lock(&dev->qp_table.lock);
 298         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 299         if (qp)
 300                 atomic_inc(&qp->refcount);
 301         spin_unlock(&dev->qp_table.lock);
 302
 303         if (!qp) {
 304                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 305                 return;
 306         }
 307
 308         event.device      = &dev->ib_dev;
 309         event.event       = event_type;
 310         event.element.qp  = &qp->ibqp;
 311         if (qp->ibqp.event_handler)
 312                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 313
 314         if (atomic_dec_and_test(&qp->refcount))
 315                 wake_up(&qp->wait);
 316 }
 317
 318 static int to_mthca_state(enum ib_qp_state ib_state)
 319 {
 320         switch (ib_state) {
 321         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 322         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 323         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 324         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 325         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 326         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 327         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 328         default:                return -1;
 329         }
 330 }
 331
 332 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 333
 334 static int to_mthca_st(int transport)
 335 {
 336         switch (transport) {
 337         case RC:  return MTHCA_QP_ST_RC;
 338         case UC:  return MTHCA_QP_ST_UC;
 339         case UD:  return MTHCA_QP_ST_UD;
 340         case RD:  return MTHCA_QP_ST_RD;
 341         case MLX: return MTHCA_QP_ST_MLX;
 342         default:  return -1;
 343         }
 344 }
 345
 346 static const struct {
 347         int trans;
 348         u32 req_param[NUM_TRANS];
 349         u32 opt_param[NUM_TRANS];
 350 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 351         [IB_QPS_RESET] = {
 352                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 353                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 354                 [IB_QPS_INIT]  = {
 355                         .trans = MTHCA_TRANS_RST2INIT,
 356                         .req_param = {
 357                                 [UD]  = (IB_QP_PKEY_INDEX |
 358                                          IB_QP_PORT       |
 359                                          IB_QP_QKEY),
 360                                 [RC]  = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_PORT       |
 362                                          IB_QP_ACCESS_FLAGS),
 363                                 [MLX] = (IB_QP_PKEY_INDEX |
 364                                          IB_QP_QKEY),
 365                         },
 366                         /* bug-for-bug compatibility with VAPI: */
 367                         .opt_param = {
 368                                 [MLX] = IB_QP_PORT
 369                         }
 370                 },
 371         },
 372         [IB_QPS_INIT]  = {
 373                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 374                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 375                 [IB_QPS_INIT]  = {
 376                         .trans = MTHCA_TRANS_INIT2INIT,
 377                         .opt_param = {
 378                                 [UD]  = (IB_QP_PKEY_INDEX |
 379                                          IB_QP_PORT       |
 380                                          IB_QP_QKEY),
 381                                 [RC]  = (IB_QP_PKEY_INDEX |
 382                                          IB_QP_PORT       |
 383                                          IB_QP_ACCESS_FLAGS),
 384                                 [MLX] = (IB_QP_PKEY_INDEX |
 385                                          IB_QP_QKEY),
 386                         }
 387                 },
 388                 [IB_QPS_RTR]   = {
 389                         .trans = MTHCA_TRANS_INIT2RTR,
 390                         .req_param = {
 391                                 [RC]  = (IB_QP_AV                  |
 392                                          IB_QP_PATH_MTU            |
 393                                          IB_QP_DEST_QPN            |
 394                                          IB_QP_RQ_PSN              |
 395                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 396                                          IB_QP_MIN_RNR_TIMER),
 397                         },
 398                         .opt_param = {
 399                                 [UD]  = (IB_QP_PKEY_INDEX |
 400                                          IB_QP_QKEY),
 401                                 [RC]  = (IB_QP_ALT_PATH     |
 402                                          IB_QP_ACCESS_FLAGS |
 403                                          IB_QP_PKEY_INDEX),
 404                                 [MLX] = (IB_QP_PKEY_INDEX |
 405                                          IB_QP_QKEY),
 406                         }
 407                 }
 408         },
 409         [IB_QPS_RTR]   = {
 410                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 411                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 412                 [IB_QPS_RTS]   = {
 413                         .trans = MTHCA_TRANS_RTR2RTS,
 414                         .req_param = {
 415                                 [UD]  = IB_QP_SQ_PSN,
 416                                 [RC]  = (IB_QP_TIMEOUT           |
 417                                          IB_QP_RETRY_CNT         |
 418                                          IB_QP_RNR_RETRY         |
 419                                          IB_QP_SQ_PSN            |
 420                                          IB_QP_MAX_QP_RD_ATOMIC),
 421                                 [MLX] = IB_QP_SQ_PSN,
 422                         },
 423                         .opt_param = {
 424                                 [UD]  = (IB_QP_CUR_STATE             |
 425                                          IB_QP_QKEY),
 426                                 [RC]  = (IB_QP_CUR_STATE             |
 427                                          IB_QP_ALT_PATH              |
 428                                          IB_QP_ACCESS_FLAGS          |
 429                                          IB_QP_PKEY_INDEX            |
 430                                          IB_QP_MIN_RNR_TIMER         |
 431                                          IB_QP_PATH_MIG_STATE),
 432                                 [MLX] = (IB_QP_CUR_STATE             |
 433                                          IB_QP_QKEY),
 434                         }
 435                 }
 436         },
 437         [IB_QPS_RTS]   = {
 438                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 439                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 440                 [IB_QPS_RTS]   = {
 441                         .trans = MTHCA_TRANS_RTS2RTS,
 442                         .opt_param = {
 443                                 [UD]  = (IB_QP_CUR_STATE             |
 444                                          IB_QP_QKEY),
 445                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 446                                          IB_QP_ALT_PATH              |
 447                                          IB_QP_PATH_MIG_STATE        |
 448                                          IB_QP_MIN_RNR_TIMER),
 449                                 [MLX] = (IB_QP_CUR_STATE             |
 450                                          IB_QP_QKEY),
 451                         }
 452                 },
 453                 [IB_QPS_SQD]   = {
 454                         .trans = MTHCA_TRANS_RTS2SQD,
 455                 },
 456         },
 457         [IB_QPS_SQD]   = {
 458                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 459                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 460                 [IB_QPS_RTS]   = {
 461                         .trans = MTHCA_TRANS_SQD2RTS,
 462                         .opt_param = {
 463                                 [UD]  = (IB_QP_CUR_STATE             |
 464                                          IB_QP_QKEY),
 465                                 [RC]  = (IB_QP_CUR_STATE             |
 466                                          IB_QP_ALT_PATH              |
 467                                          IB_QP_ACCESS_FLAGS          |
 468                                          IB_QP_MIN_RNR_TIMER         |
 469                                          IB_QP_PATH_MIG_STATE),
 470                                 [MLX] = (IB_QP_CUR_STATE             |
 471                                          IB_QP_QKEY),
 472                         }
 473                 },
 474                 [IB_QPS_SQD]   = {
 475                         .trans = MTHCA_TRANS_SQD2SQD,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_PKEY_INDEX            |
 478                                          IB_QP_QKEY),
 479                                 [RC]  = (IB_QP_AV                    |
 480                                          IB_QP_TIMEOUT               |
 481                                          IB_QP_RETRY_CNT             |
 482                                          IB_QP_RNR_RETRY             |
 483                                          IB_QP_MAX_QP_RD_ATOMIC      |
 484                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 485                                          IB_QP_CUR_STATE             |
 486                                          IB_QP_ALT_PATH              |
 487                                          IB_QP_ACCESS_FLAGS          |
 488                                          IB_QP_PKEY_INDEX            |
 489                                          IB_QP_MIN_RNR_TIMER         |
 490                                          IB_QP_PATH_MIG_STATE),
 491                                 [MLX] = (IB_QP_PKEY_INDEX            |
 492                                          IB_QP_QKEY),
 493                         }
 494                 }
 495         },
 496         [IB_QPS_SQE]   = {
 497                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 498                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 499                 [IB_QPS_RTS]   = {
 500                         .trans = MTHCA_TRANS_SQERR2RTS,
 501                         .opt_param = {
 502                                 [UD]  = (IB_QP_CUR_STATE             |
 503                                          IB_QP_QKEY),
 504                                 [RC]  = (IB_QP_CUR_STATE             |
 505                                          IB_QP_MIN_RNR_TIMER),
 506                                 [MLX] = (IB_QP_CUR_STATE             |
 507                                          IB_QP_QKEY),
 508                         }
 509                 }
 510         },
 511         [IB_QPS_ERR] = {
 512                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 513                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 514         }
 515 };
 516
 517 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 518                         int attr_mask)
 519 {
 520         if (attr_mask & IB_QP_PKEY_INDEX)
 521                 sqp->pkey_index = attr->pkey_index;
 522         if (attr_mask & IB_QP_QKEY)
 523                 sqp->qkey = attr->qkey;
 524         if (attr_mask & IB_QP_SQ_PSN)
 525                 sqp->send_psn = attr->sq_psn;
 526 }
 527
 528 static void init_port(struct mthca_dev *dev, int port)
 529 {
 530         int err;
 531         u8 status;
 532         struct mthca_init_ib_param param;
 533
 534         memset(&param, 0, sizeof param);
 535
 536         param.enable_1x = 1;
 537         param.enable_4x = 1;
 538         param.vl_cap    = dev->limits.vl_cap;
 539         param.mtu_cap   = dev->limits.mtu_cap;
 540         param.gid_cap   = dev->limits.gid_table_len;
 541         param.pkey_cap  = dev->limits.pkey_table_len;
 542
 543         err = mthca_INIT_IB(dev, &param, port, &status);
 544         if (err)
 545                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 546         if (status)
 547                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 548 }
 549
 550 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 551 {
 552         struct mthca_dev *dev = to_mdev(ibqp->device);
 553         struct mthca_qp *qp = to_mqp(ibqp);
 554         enum ib_qp_state cur_state, new_state;
 555         void *mailbox = NULL;
 556         struct mthca_qp_param *qp_param;
 557         struct mthca_qp_context *qp_context;
 558         u32 req_param, opt_param;
 559         u8 status;
 560         int err;
 561
 562         if (attr_mask & IB_QP_CUR_STATE) {
 563                 if (attr->cur_qp_state != IB_QPS_RTR &&
 564                     attr->cur_qp_state != IB_QPS_RTS &&
 565                     attr->cur_qp_state != IB_QPS_SQD &&
 566                     attr->cur_qp_state != IB_QPS_SQE)
 567                         return -EINVAL;
 568                 else
 569                         cur_state = attr->cur_qp_state;
 570         } else {
 571                 spin_lock_irq(&qp->sq.lock);
 572                 spin_lock(&qp->rq.lock);
 573                 cur_state = qp->state;
 574                 spin_unlock(&qp->rq.lock);
 575                 spin_unlock_irq(&qp->sq.lock);
 576         }
 577
 578         if (attr_mask & IB_QP_STATE) {
 579                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 580                         return -EINVAL;
 581                 new_state = attr->qp_state;
 582         } else
 583                 new_state = cur_state;
 584
 585         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 586                 mthca_dbg(dev, "Illegal QP transition "
 587                           "%d->%d\n", cur_state, new_state);
 588                 return -EINVAL;
 589         }
 590
 591         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 592         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 593
 594         if ((req_param & attr_mask) != req_param) {
 595                 mthca_dbg(dev, "QP transition "
 596                           "%d->%d missing req attr 0x%08x\n",
 597                           cur_state, new_state,
 598                           req_param & ~attr_mask);
 599                 return -EINVAL;
 600         }
 601
 602         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 603                 mthca_dbg(dev, "QP transition (transport %d) "
 604                           "%d->%d has extra attr 0x%08x\n",
 605                           qp->transport,
 606                           cur_state, new_state,
 607                           attr_mask & ~(req_param | opt_param |
 608                                                  IB_QP_STATE));
 609                 return -EINVAL;
 610         }
 611
 612         mailbox = kmalloc(sizeof (*qp_param) + MTHCA_CMD_MAILBOX_EXTRA, GFP_KERNEL);
 613         if (!mailbox)
 614                 return -ENOMEM;
 615         qp_param = MAILBOX_ALIGN(mailbox);
 616         qp_context = &qp_param->context;
 617         memset(qp_param, 0, sizeof *qp_param);
 618
 619         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 620                                              (to_mthca_st(qp->transport) << 16));
 621         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 622         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 623                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 624         else {
 625                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 626                 switch (attr->path_mig_state) {
 627                 case IB_MIG_MIGRATED:
 628                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 629                         break;
 630                 case IB_MIG_REARM:
 631                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 632                         break;
 633                 case IB_MIG_ARMED:
 634                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 635                         break;
 636                 }
 637         }
 638
 639         /* leave tavor_sched_queue as 0 */
 640
 641         if (qp->transport == MLX || qp->transport == UD)
 642                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 643         else if (attr_mask & IB_QP_PATH_MTU)
 644                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 645
 646         if (mthca_is_memfree(dev)) {
 647                 qp_context->rq_size_stride =
 648                         ((ffs(qp->rq.max) - 1) << 3) | (qp->rq.wqe_shift - 4);
 649                 qp_context->sq_size_stride =
 650                         ((ffs(qp->sq.max) - 1) << 3) | (qp->sq.wqe_shift - 4);
 651         }
 652
 653         /* leave arbel_sched_queue as 0 */
 654
 655         qp_context->usr_page   = cpu_to_be32(dev->driver_uar.index);
 656         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 657         if (attr_mask & IB_QP_DEST_QPN) {
 658                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 659         }
 660
 661         if (qp->transport == MLX)
 662                 qp_context->pri_path.port_pkey |=
 663                         cpu_to_be32(to_msqp(qp)->port << 24);
 664         else {
 665                 if (attr_mask & IB_QP_PORT) {
 666                         qp_context->pri_path.port_pkey |=
 667                                 cpu_to_be32(attr->port_num << 24);
 668                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 669                 }
 670         }
 671
 672         if (attr_mask & IB_QP_PKEY_INDEX) {
 673                 qp_context->pri_path.port_pkey |=
 674                         cpu_to_be32(attr->pkey_index);
 675                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 676         }
 677
 678         if (attr_mask & IB_QP_RNR_RETRY) {
 679                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 680                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 681         }
 682
 683         if (attr_mask & IB_QP_AV) {
 684                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 685                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 686                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 687                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 688                         qp_context->pri_path.g_mylmc |= 1 << 7;
 689                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 690                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 691                         qp_context->pri_path.sl_tclass_flowlabel =
 692                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 693                                             (attr->ah_attr.grh.traffic_class << 20) |
 694                                             (attr->ah_attr.grh.flow_label));
 695                         memcpy(qp_context->pri_path.rgid,
 696                                attr->ah_attr.grh.dgid.raw, 16);
 697                 } else {
 698                         qp_context->pri_path.sl_tclass_flowlabel =
 699                                 cpu_to_be32(attr->ah_attr.sl << 28);
 700                 }
 701                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 702         }
 703
 704         if (attr_mask & IB_QP_TIMEOUT) {
 705                 qp_context->pri_path.ackto = attr->timeout;
 706                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 707         }
 708
 709         /* XXX alt_path */
 710
 711         /* leave rdd as 0 */
 712         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 713         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 714         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 715         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 716                                              (MTHCA_FLIGHT_LIMIT << 24) |
 717                                              MTHCA_QP_BIT_SRE           |
 718                                              MTHCA_QP_BIT_SWE           |
 719                                              MTHCA_QP_BIT_SAE);
 720         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 721                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 722         if (attr_mask & IB_QP_RETRY_CNT) {
 723                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 724                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 725         }
 726
 727         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 728                 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
 729                                                        ffs(attr->max_rd_atomic) - 1 : 0,
 730                                                        7) << 21);
 731                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 732         }
 733
 734         if (attr_mask & IB_QP_SQ_PSN)
 735                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 736         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 737
 738         if (mthca_is_memfree(dev)) {
 739                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 740                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 741         }
 742
 743         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 744                 /*
 745                  * Only enable RDMA/atomics if we have responder
 746                  * resources set to a non-zero value.
 747                  */
 748                 if (qp->resp_depth) {
 749                         qp_context->params2 |=
 750                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 751                                             MTHCA_QP_BIT_RWE : 0);
 752                         qp_context->params2 |=
 753                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 754                                             MTHCA_QP_BIT_RRE : 0);
 755                         qp_context->params2 |=
 756                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 757                                             MTHCA_QP_BIT_RAE : 0);
 758                 }
 759
 760                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 761                                                         MTHCA_QP_OPTPAR_RRE |
 762                                                         MTHCA_QP_OPTPAR_RAE);
 763
 764                 qp->atomic_rd_en = attr->qp_access_flags;
 765         }
 766
 767         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 768                 u8 rra_max;
 769
 770                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 771                         /*
 772                          * Lowering our responder resources to zero.
 773                          * Turn off RDMA/atomics as responder.
 774                          * (RWE/RRE/RAE in params2 already zero)
 775                          */
 776                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 777                                                                 MTHCA_QP_OPTPAR_RRE |
 778                                                                 MTHCA_QP_OPTPAR_RAE);
 779                 }
 780
 781                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 782                         /*
 783                          * Increasing our responder resources from
 784                          * zero.  Turn on RDMA/atomics as appropriate.
 785                          */
 786                         qp_context->params2 |=
 787                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 788                                             MTHCA_QP_BIT_RWE : 0);
 789                         qp_context->params2 |=
 790                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 791                                             MTHCA_QP_BIT_RRE : 0);
 792                         qp_context->params2 |=
 793                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 794                                             MTHCA_QP_BIT_RAE : 0);
 795
 796                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 797                                                                 MTHCA_QP_OPTPAR_RRE |
 798                                                                 MTHCA_QP_OPTPAR_RAE);
 799                 }
 800
 801                 for (rra_max = 0;
 802                      1 << rra_max < attr->max_dest_rd_atomic &&
 803                              rra_max < dev->qp_table.rdb_shift;
 804                      ++rra_max)
 805                         ; /* nothing */
 806
 807                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 808                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 809
 810                 qp->resp_depth = attr->max_dest_rd_atomic;
 811         }
 812
 813         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 814
 815         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 816                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 817                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 818         }
 819         if (attr_mask & IB_QP_RQ_PSN)
 820                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 821
 822         qp_context->ra_buff_indx =
 823                 cpu_to_be32(dev->qp_table.rdb_base +
 824                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 825                              dev->qp_table.rdb_shift));
 826
 827         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 828
 829         if (mthca_is_memfree(dev))
 830                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 831
 832         if (attr_mask & IB_QP_QKEY) {
 833                 qp_context->qkey = cpu_to_be32(attr->qkey);
 834                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 835         }
 836
 837         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 838                               qp->qpn, 0, qp_param, 0, &status);
 839         if (status) {
 840                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 841                            state_table[cur_state][new_state].trans, status);
 842                 err = -EINVAL;
 843         }
 844
 845         if (!err)
 846                 qp->state = new_state;
 847
 848         kfree(mailbox);
 849
 850         if (is_sqp(dev, qp))
 851                 store_attrs(to_msqp(qp), attr, attr_mask);
 852
 853         /*
 854          * If we are moving QP0 to RTR, bring the IB link up; if we
 855          * are moving QP0 to RESET or ERROR, bring the link back down.
 856          */
 857         if (is_qp0(dev, qp)) {
 858                 if (cur_state != IB_QPS_RTR &&
 859                     new_state == IB_QPS_RTR)
 860                         init_port(dev, to_msqp(qp)->port);
 861
 862                 if (cur_state != IB_QPS_RESET &&
 863                     cur_state != IB_QPS_ERR &&
 864                     (new_state == IB_QPS_RESET ||
 865                      new_state == IB_QPS_ERR))
 866                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 867         }
 868
 869         return err;
 870 }
 871
 872 /*
 873  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 874  * rq.max_gs and sq.max_gs must all be assigned.
 875  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 876  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 877  * queue)
 878  */
 879 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 880                                struct mthca_pd *pd,
 881                                struct mthca_qp *qp)
 882 {
 883         int size;
 884         int i;
 885         int npages, shift;
 886         dma_addr_t t;
 887         u64 *dma_list = NULL;
 888         int err = -ENOMEM;
 889
 890         size = sizeof (struct mthca_next_seg) +
 891                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 892
 893         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 894              qp->rq.wqe_shift++)
 895                 ; /* nothing */
 896
 897         size = sizeof (struct mthca_next_seg) +
 898                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 899         switch (qp->transport) {
 900         case MLX:
 901                 size += 2 * sizeof (struct mthca_data_seg);
 902                 break;
 903         case UD:
 904                 if (mthca_is_memfree(dev))
 905                         size += sizeof (struct mthca_arbel_ud_seg);
 906                 else
 907                         size += sizeof (struct mthca_tavor_ud_seg);
 908                 break;
 909         default:
 910                 /* bind seg is as big as atomic + raddr segs */
 911                 size += sizeof (struct mthca_bind_seg);
 912         }
 913
 914         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 915              qp->sq.wqe_shift++)
 916                 ; /* nothing */
 917
 918         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 919                                     1 << qp->sq.wqe_shift);
 920         size = PAGE_ALIGN(qp->send_wqe_offset +
 921                           (qp->sq.max << qp->sq.wqe_shift));
 922
 923         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 924                            GFP_KERNEL);
 925         if (!qp->wrid)
 926                 goto err_out;
 927
 928         if (size <= MTHCA_MAX_DIRECT_QP_SIZE) {
 929                 qp->is_direct = 1;
 930                 npages = 1;
 931                 shift = get_order(size) + PAGE_SHIFT;
 932
 933                 if (0)
 934                         mthca_dbg(dev, "Creating direct QP of size %d (shift %d)\n",
 935                                   size, shift);
 936
 937                 qp->queue.direct.buf = dma_alloc_coherent(&dev->pdev->dev, size,
 938                                                           &t, GFP_KERNEL);
 939                 if (!qp->queue.direct.buf)
 940                         goto err_out;
 941
 942                 pci_unmap_addr_set(&qp->queue.direct, mapping, t);
 943
 944                 memset(qp->queue.direct.buf, 0, size);
 945
 946                 while (t & ((1 << shift) - 1)) {
 947                         --shift;
 948                         npages *= 2;
 949                 }
 950
 951                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 952                 if (!dma_list)
 953                         goto err_out_free;
 954
 955                 for (i = 0; i < npages; ++i)
 956                         dma_list[i] = t + i * (1 << shift);
 957         } else {
 958                 qp->is_direct = 0;
 959                 npages = size / PAGE_SIZE;
 960                 shift = PAGE_SHIFT;
 961
 962                 if (0)
 963                         mthca_dbg(dev, "Creating indirect QP with %d pages\n", npages);
 964
 965                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 966                 if (!dma_list)
 967                         goto err_out;
 968
 969                 qp->queue.page_list = kmalloc(npages *
 970                                               sizeof *qp->queue.page_list,
 971                                               GFP_KERNEL);
 972                 if (!qp->queue.page_list)
 973                         goto err_out;
 974
 975                 for (i = 0; i < npages; ++i) {
 976                         qp->queue.page_list[i].buf =
 977                                 dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
 978                                                    &t, GFP_KERNEL);
 979                         if (!qp->queue.page_list[i].buf)
 980                                 goto err_out_free;
 981
 982                         memset(qp->queue.page_list[i].buf, 0, PAGE_SIZE);
 983
 984                         pci_unmap_addr_set(&qp->queue.page_list[i], mapping, t);
 985                         dma_list[i] = t;
 986                 }
 987         }
 988
 989         err = mthca_mr_alloc_phys(dev, pd->pd_num, dma_list, shift,
 990                                   npages, 0, size,
 991                                   MTHCA_MPT_FLAG_LOCAL_READ,
 992                                   &qp->mr);
 993         if (err)
 994                 goto err_out_free;
 995
 996         kfree(dma_list);
 997         return 0;
 998
 999  err_out_free:
1000         if (qp->is_direct) {
1001                 dma_free_coherent(&dev->pdev->dev, size, qp->queue.direct.buf,
1002                                   pci_unmap_addr(&qp->queue.direct, mapping));
1003         } else
1004                 for (i = 0; i < npages; ++i) {
1005                         if (qp->queue.page_list[i].buf)
1006                                 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1007                                                   qp->queue.page_list[i].buf,
1008                                                   pci_unmap_addr(&qp->queue.page_list[i],
1009                                                                  mapping));
1010
1011                 }
1012
1013  err_out:
1014         kfree(qp->wrid);
1015         kfree(dma_list);
1016         return err;
1017 }
1018
1019 static int mthca_alloc_memfree(struct mthca_dev *dev,
1020                                struct mthca_qp *qp)
1021 {
1022         int ret = 0;
1023
1024         if (mthca_is_memfree(dev)) {
1025                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1026                 if (ret)
1027                         return ret;
1028
1029                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1030                 if (ret)
1031                         goto err_qpc;
1032
1033                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1034                                       qp->qpn << dev->qp_table.rdb_shift);
1035                 if (ret)
1036                         goto err_eqpc;
1037
1038                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1039                                                  qp->qpn, &qp->rq.db);
1040                 if (qp->rq.db_index < 0) {
1041                         ret = -ENOMEM;
1042                         goto err_rdb;
1043                 }
1044
1045                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1046                                                  qp->qpn, &qp->sq.db);
1047                 if (qp->sq.db_index < 0) {
1048                         ret = -ENOMEM;
1049                         goto err_rq_db;
1050                 }
1051         }
1052
1053         return 0;
1054
1055 err_rq_db:
1056         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1057
1058 err_rdb:
1059         mthca_table_put(dev, dev->qp_table.rdb_table,
1060                         qp->qpn << dev->qp_table.rdb_shift);
1061
1062 err_eqpc:
1063         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1064
1065 err_qpc:
1066         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1067
1068         return ret;
1069 }
1070
1071 static void mthca_free_memfree(struct mthca_dev *dev,
1072                                struct mthca_qp *qp)
1073 {
1074         if (mthca_is_memfree(dev)) {
1075                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1076                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1077                 mthca_table_put(dev, dev->qp_table.rdb_table,
1078                                 qp->qpn << dev->qp_table.rdb_shift);
1079                 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1080                 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1081         }
1082 }
1083
1084 static void mthca_wq_init(struct mthca_wq* wq)
1085 {
1086         spin_lock_init(&wq->lock);
1087         wq->next_ind  = 0;
1088         wq->last_comp = wq->max - 1;
1089         wq->head      = 0;
1090         wq->tail      = 0;
1091         wq->last      = NULL;
1092 }
1093
1094 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1095                                  struct mthca_pd *pd,
1096                                  struct mthca_cq *send_cq,
1097                                  struct mthca_cq *recv_cq,
1098                                  enum ib_sig_type send_policy,
1099                                  struct mthca_qp *qp)
1100 {
1101         int ret;
1102         int i;
1103
1104         atomic_set(&qp->refcount, 1);
1105         qp->state        = IB_QPS_RESET;
1106         qp->atomic_rd_en = 0;
1107         qp->resp_depth   = 0;
1108         qp->sq_policy    = send_policy;
1109         mthca_wq_init(&qp->sq);
1110         mthca_wq_init(&qp->rq);
1111
1112         ret = mthca_alloc_memfree(dev, qp);
1113         if (ret)
1114                 return ret;
1115
1116         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1117         if (ret) {
1118                 mthca_free_memfree(dev, qp);
1119                 return ret;
1120         }
1121
1122         if (mthca_is_memfree(dev)) {
1123                 struct mthca_next_seg *next;
1124                 struct mthca_data_seg *scatter;
1125                 int size = (sizeof (struct mthca_next_seg) +
1126                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1127
1128                 for (i = 0; i < qp->rq.max; ++i) {
1129                         next = get_recv_wqe(qp, i);
1130                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1131                                                    qp->rq.wqe_shift);
1132                         next->ee_nds = cpu_to_be32(size);
1133
1134                         for (scatter = (void *) (next + 1);
1135                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1136                              ++scatter)
1137                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1138                 }
1139
1140                 for (i = 0; i < qp->sq.max; ++i) {
1141                         next = get_send_wqe(qp, i);
1142                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1143                                                     qp->sq.wqe_shift) +
1144                                                    qp->send_wqe_offset);
1145                 }
1146         }
1147
1148         return 0;
1149 }
1150
1151 static void mthca_align_qp_size(struct mthca_dev *dev, struct mthca_qp *qp)
1152 {
1153         int i;
1154
1155         if (!mthca_is_memfree(dev))
1156                 return;
1157
1158         for (i = 0; 1 << i < qp->rq.max; ++i)
1159                 ; /* nothing */
1160
1161         qp->rq.max = 1 << i;
1162
1163         for (i = 0; 1 << i < qp->sq.max; ++i)
1164                 ; /* nothing */
1165
1166         qp->sq.max = 1 << i;
1167 }
1168
1169 int mthca_alloc_qp(struct mthca_dev *dev,
1170                    struct mthca_pd *pd,
1171                    struct mthca_cq *send_cq,
1172                    struct mthca_cq *recv_cq,
1173                    enum ib_qp_type type,
1174                    enum ib_sig_type send_policy,
1175                    struct mthca_qp *qp)
1176 {
1177         int err;
1178
1179         mthca_align_qp_size(dev, qp);
1180
1181         switch (type) {
1182         case IB_QPT_RC: qp->transport = RC; break;
1183         case IB_QPT_UC: qp->transport = UC; break;
1184         case IB_QPT_UD: qp->transport = UD; break;
1185         default: return -EINVAL;
1186         }
1187
1188         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1189         if (qp->qpn == -1)
1190                 return -ENOMEM;
1191
1192         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1193                                     send_policy, qp);
1194         if (err) {
1195                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1196                 return err;
1197         }
1198
1199         spin_lock_irq(&dev->qp_table.lock);
1200         mthca_array_set(&dev->qp_table.qp,
1201                         qp->qpn & (dev->limits.num_qps - 1), qp);
1202         spin_unlock_irq(&dev->qp_table.lock);
1203
1204         return 0;
1205 }
1206
1207 int mthca_alloc_sqp(struct mthca_dev *dev,
1208                     struct mthca_pd *pd,
1209                     struct mthca_cq *send_cq,
1210                     struct mthca_cq *recv_cq,
1211                     enum ib_sig_type send_policy,
1212                     int qpn,
1213                     int port,
1214                     struct mthca_sqp *sqp)
1215 {
1216         int err = 0;
1217         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1218
1219         mthca_align_qp_size(dev, &sqp->qp);
1220
1221         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1222         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1223                                              &sqp->header_dma, GFP_KERNEL);
1224         if (!sqp->header_buf)
1225                 return -ENOMEM;
1226
1227         spin_lock_irq(&dev->qp_table.lock);
1228         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1229                 err = -EBUSY;
1230         else
1231                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1232         spin_unlock_irq(&dev->qp_table.lock);
1233
1234         if (err)
1235                 goto err_out;
1236
1237         sqp->port = port;
1238         sqp->qp.qpn       = mqpn;
1239         sqp->qp.transport = MLX;
1240
1241         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1242                                     send_policy, &sqp->qp);
1243         if (err)
1244                 goto err_out_free;
1245
1246         atomic_inc(&pd->sqp_count);
1247
1248         return 0;
1249
1250  err_out_free:
1251         /*
1252          * Lock CQs here, so that CQ polling code can do QP lookup
1253          * without taking a lock.
1254          */
1255         spin_lock_irq(&send_cq->lock);
1256         if (send_cq != recv_cq)
1257                 spin_lock(&recv_cq->lock);
1258
1259         spin_lock(&dev->qp_table.lock);
1260         mthca_array_clear(&dev->qp_table.qp, mqpn);
1261         spin_unlock(&dev->qp_table.lock);
1262
1263         if (send_cq != recv_cq)
1264                 spin_unlock(&recv_cq->lock);
1265         spin_unlock_irq(&send_cq->lock);
1266
1267  err_out:
1268         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1269                           sqp->header_buf, sqp->header_dma);
1270
1271         return err;
1272 }
1273
1274 void mthca_free_qp(struct mthca_dev *dev,
1275                    struct mthca_qp *qp)
1276 {
1277         u8 status;
1278         int size;
1279         int i;
1280         struct mthca_cq *send_cq;
1281         struct mthca_cq *recv_cq;
1282
1283         send_cq = to_mcq(qp->ibqp.send_cq);
1284         recv_cq = to_mcq(qp->ibqp.recv_cq);
1285
1286         /*
1287          * Lock CQs here, so that CQ polling code can do QP lookup
1288          * without taking a lock.
1289          */
1290         spin_lock_irq(&send_cq->lock);
1291         if (send_cq != recv_cq)
1292                 spin_lock(&recv_cq->lock);
1293
1294         spin_lock(&dev->qp_table.lock);
1295         mthca_array_clear(&dev->qp_table.qp,
1296                           qp->qpn & (dev->limits.num_qps - 1));
1297         spin_unlock(&dev->qp_table.lock);
1298
1299         if (send_cq != recv_cq)
1300                 spin_unlock(&recv_cq->lock);
1301         spin_unlock_irq(&send_cq->lock);
1302
1303         atomic_dec(&qp->refcount);
1304         wait_event(qp->wait, !atomic_read(&qp->refcount));
1305
1306         if (qp->state != IB_QPS_RESET)
1307                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1308
1309         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn);
1310         if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1311                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn);
1312
1313         mthca_free_mr(dev, &qp->mr);
1314
1315         size = PAGE_ALIGN(qp->send_wqe_offset +
1316                           (qp->sq.max << qp->sq.wqe_shift));
1317
1318         if (qp->is_direct) {
1319                 pci_free_consistent(dev->pdev, size,
1320                                     qp->queue.direct.buf,
1321                                     pci_unmap_addr(&qp->queue.direct, mapping));
1322         } else {
1323                 for (i = 0; i < size / PAGE_SIZE; ++i) {
1324                         pci_free_consistent(dev->pdev, PAGE_SIZE,
1325                                             qp->queue.page_list[i].buf,
1326                                             pci_unmap_addr(&qp->queue.page_list[i],
1327                                                            mapping));
1328                 }
1329         }
1330
1331         kfree(qp->wrid);
1332
1333         mthca_free_memfree(dev, qp);
1334
1335         if (is_sqp(dev, qp)) {
1336                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1337                 dma_free_coherent(&dev->pdev->dev,
1338                                   to_msqp(qp)->header_buf_size,
1339                                   to_msqp(qp)->header_buf,
1340                                   to_msqp(qp)->header_dma);
1341         } else
1342                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1343 }
1344
1345 /* Create UD header for an MLX send and build a data segment for it */
1346 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1347                             int ind, struct ib_send_wr *wr,
1348                             struct mthca_mlx_seg *mlx,
1349                             struct mthca_data_seg *data)
1350 {
1351         int header_size;
1352         int err;
1353
1354         ib_ud_header_init(256, /* assume a MAD */
1355                           sqp->ud_header.grh_present,
1356                           &sqp->ud_header);
1357
1358         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1359         if (err)
1360                 return err;
1361         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1362         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1363                                   (sqp->ud_header.lrh.destination_lid == 0xffff ?
1364                                    MTHCA_MLX_SLR : 0) |
1365                                   (sqp->ud_header.lrh.service_level << 8));
1366         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1367         mlx->vcrc = 0;
1368
1369         switch (wr->opcode) {
1370         case IB_WR_SEND:
1371                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1372                 sqp->ud_header.immediate_present = 0;
1373                 break;
1374         case IB_WR_SEND_WITH_IMM:
1375                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1376                 sqp->ud_header.immediate_present = 1;
1377                 sqp->ud_header.immediate_data = wr->imm_data;
1378                 break;
1379         default:
1380                 return -EINVAL;
1381         }
1382
1383         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1384         if (sqp->ud_header.lrh.destination_lid == 0xffff)
1385                 sqp->ud_header.lrh.source_lid = 0xffff;
1386         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1387         if (!sqp->qp.ibqp.qp_num)
1388                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1389                                    sqp->pkey_index,
1390                                    &sqp->ud_header.bth.pkey);
1391         else
1392                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1393                                    wr->wr.ud.pkey_index,
1394                                    &sqp->ud_header.bth.pkey);
1395         cpu_to_be16s(&sqp->ud_header.bth.pkey);
1396         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1397         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1398         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1399                                                sqp->qkey : wr->wr.ud.remote_qkey);
1400         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1401
1402         header_size = ib_ud_header_pack(&sqp->ud_header,
1403                                         sqp->header_buf +
1404                                         ind * MTHCA_UD_HEADER_SIZE);
1405
1406         data->byte_count = cpu_to_be32(header_size);
1407         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1408         data->addr       = cpu_to_be64(sqp->header_dma +
1409                                        ind * MTHCA_UD_HEADER_SIZE);
1410
1411         return 0;
1412 }
1413
1414 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1415                                     struct ib_cq *ib_cq)
1416 {
1417         unsigned cur;
1418         struct mthca_cq *cq;
1419
1420         cur = wq->head - wq->tail;
1421         if (likely(cur + nreq < wq->max))
1422                 return 0;
1423
1424         cq = to_mcq(ib_cq);
1425         spin_lock(&cq->lock);
1426         cur = wq->head - wq->tail;
1427         spin_unlock(&cq->lock);
1428
1429         return cur + nreq >= wq->max;
1430 }
1431
1432 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1433                           struct ib_send_wr **bad_wr)
1434 {
1435         struct mthca_dev *dev = to_mdev(ibqp->device);
1436         struct mthca_qp *qp = to_mqp(ibqp);
1437         void *wqe;
1438         void *prev_wqe;
1439         unsigned long flags;
1440         int err = 0;
1441         int nreq;
1442         int i;
1443         int size;
1444         int size0 = 0;
1445         u32 f0 = 0;
1446         int ind;
1447         u8 op0 = 0;
1448
1449         spin_lock_irqsave(&qp->sq.lock, flags);
1450
1451         /* XXX check that state is OK to post send */
1452
1453         ind = qp->sq.next_ind;
1454
1455         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1456                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1457                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1458                                         " %d max, %d nreq)\n", qp->qpn,
1459                                         qp->sq.head, qp->sq.tail,
1460                                         qp->sq.max, nreq);
1461                         err = -ENOMEM;
1462                         *bad_wr = wr;
1463                         goto out;
1464                 }
1465
1466                 wqe = get_send_wqe(qp, ind);
1467                 prev_wqe = qp->sq.last;
1468                 qp->sq.last = wqe;
1469
1470                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1471                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1472                 ((struct mthca_next_seg *) wqe)->flags =
1473                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1474                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1475                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1476                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1477                         cpu_to_be32(1);
1478                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1479                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1480                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1481
1482                 wqe += sizeof (struct mthca_next_seg);
1483                 size = sizeof (struct mthca_next_seg) / 16;
1484
1485                 switch (qp->transport) {
1486                 case RC:
1487                         switch (wr->opcode) {
1488                         case IB_WR_ATOMIC_CMP_AND_SWP:
1489                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1490                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1491                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1492                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1493                                         cpu_to_be32(wr->wr.atomic.rkey);
1494                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1495
1496                                 wqe += sizeof (struct mthca_raddr_seg);
1497
1498                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1499                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1500                                                 cpu_to_be64(wr->wr.atomic.swap);
1501                                         ((struct mthca_atomic_seg *) wqe)->compare =
1502                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1503                                 } else {
1504                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1505                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1506                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1507                                 }
1508
1509                                 wqe += sizeof (struct mthca_atomic_seg);
1510                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1511                                         sizeof (struct mthca_atomic_seg);
1512                                 break;
1513
1514                         case IB_WR_RDMA_WRITE:
1515                         case IB_WR_RDMA_WRITE_WITH_IMM:
1516                         case IB_WR_RDMA_READ:
1517                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1518                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1519                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1520                                         cpu_to_be32(wr->wr.rdma.rkey);
1521                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1522                                 wqe += sizeof (struct mthca_raddr_seg);
1523                                 size += sizeof (struct mthca_raddr_seg) / 16;
1524                                 break;
1525
1526                         default:
1527                                 /* No extra segments required for sends */
1528                                 break;
1529                         }
1530
1531                         break;
1532
1533                 case UD:
1534                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1535                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1536                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1537                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1538                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1539                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1540                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1541                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1542
1543                         wqe += sizeof (struct mthca_tavor_ud_seg);
1544                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1545                         break;
1546
1547                 case MLX:
1548                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1549                                                wqe - sizeof (struct mthca_next_seg),
1550                                                wqe);
1551                         if (err) {
1552                                 *bad_wr = wr;
1553                                 goto out;
1554                         }
1555                         wqe += sizeof (struct mthca_data_seg);
1556                         size += sizeof (struct mthca_data_seg) / 16;
1557                         break;
1558                 }
1559
1560                 if (wr->num_sge > qp->sq.max_gs) {
1561                         mthca_err(dev, "too many gathers\n");
1562                         err = -EINVAL;
1563                         *bad_wr = wr;
1564                         goto out;
1565                 }
1566
1567                 for (i = 0; i < wr->num_sge; ++i) {
1568                         ((struct mthca_data_seg *) wqe)->byte_count =
1569                                 cpu_to_be32(wr->sg_list[i].length);
1570                         ((struct mthca_data_seg *) wqe)->lkey =
1571                                 cpu_to_be32(wr->sg_list[i].lkey);
1572                         ((struct mthca_data_seg *) wqe)->addr =
1573                                 cpu_to_be64(wr->sg_list[i].addr);
1574                         wqe += sizeof (struct mthca_data_seg);
1575                         size += sizeof (struct mthca_data_seg) / 16;
1576                 }
1577
1578                 /* Add one more inline data segment for ICRC */
1579                 if (qp->transport == MLX) {
1580                         ((struct mthca_data_seg *) wqe)->byte_count =
1581                                 cpu_to_be32((1 << 31) | 4);
1582                         ((u32 *) wqe)[1] = 0;
1583                         wqe += sizeof (struct mthca_data_seg);
1584                         size += sizeof (struct mthca_data_seg) / 16;
1585                 }
1586
1587                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1588
1589                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1590                         mthca_err(dev, "opcode invalid\n");
1591                         err = -EINVAL;
1592                         *bad_wr = wr;
1593                         goto out;
1594                 }
1595
1596                 if (prev_wqe) {
1597                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1598                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1599                                              qp->send_wqe_offset) |
1600                                             mthca_opcode[wr->opcode]);
1601                         wmb();
1602                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1603                                 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1604                 }
1605
1606                 if (!size0) {
1607                         size0 = size;
1608                         op0   = mthca_opcode[wr->opcode];
1609                 }
1610
1611                 ++ind;
1612                 if (unlikely(ind >= qp->sq.max))
1613                         ind -= qp->sq.max;
1614         }
1615
1616 out:
1617         if (likely(nreq)) {
1618                 u32 doorbell[2];
1619
1620                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1621                                            qp->send_wqe_offset) | f0 | op0);
1622                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1623
1624                 wmb();
1625
1626                 mthca_write64(doorbell,
1627                               dev->kar + MTHCA_SEND_DOORBELL,
1628                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1629         }
1630
1631         qp->sq.next_ind = ind;
1632         qp->sq.head    += nreq;
1633
1634         spin_unlock_irqrestore(&qp->sq.lock, flags);
1635         return err;
1636 }
1637
1638 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1639                              struct ib_recv_wr **bad_wr)
1640 {
1641         struct mthca_dev *dev = to_mdev(ibqp->device);
1642         struct mthca_qp *qp = to_mqp(ibqp);
1643         unsigned long flags;
1644         int err = 0;
1645         int nreq;
1646         int i;
1647         int size;
1648         int size0 = 0;
1649         int ind;
1650         void *wqe;
1651         void *prev_wqe;
1652
1653         spin_lock_irqsave(&qp->rq.lock, flags);
1654
1655         /* XXX check that state is OK to post receive */
1656
1657         ind = qp->rq.next_ind;
1658
1659         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1660                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1661                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1662                                         " %d max, %d nreq)\n", qp->qpn,
1663                                         qp->rq.head, qp->rq.tail,
1664                                         qp->rq.max, nreq);
1665                         err = -ENOMEM;
1666                         *bad_wr = wr;
1667                         goto out;
1668                 }
1669
1670                 wqe = get_recv_wqe(qp, ind);
1671                 prev_wqe = qp->rq.last;
1672                 qp->rq.last = wqe;
1673
1674                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1675                 ((struct mthca_next_seg *) wqe)->ee_nds =
1676                         cpu_to_be32(MTHCA_NEXT_DBD);
1677                 ((struct mthca_next_seg *) wqe)->flags = 0;
1678
1679                 wqe += sizeof (struct mthca_next_seg);
1680                 size = sizeof (struct mthca_next_seg) / 16;
1681
1682                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1683                         err = -EINVAL;
1684                         *bad_wr = wr;
1685                         goto out;
1686                 }
1687
1688                 for (i = 0; i < wr->num_sge; ++i) {
1689                         ((struct mthca_data_seg *) wqe)->byte_count =
1690                                 cpu_to_be32(wr->sg_list[i].length);
1691                         ((struct mthca_data_seg *) wqe)->lkey =
1692                                 cpu_to_be32(wr->sg_list[i].lkey);
1693                         ((struct mthca_data_seg *) wqe)->addr =
1694                                 cpu_to_be64(wr->sg_list[i].addr);
1695                         wqe += sizeof (struct mthca_data_seg);
1696                         size += sizeof (struct mthca_data_seg) / 16;
1697                 }
1698
1699                 qp->wrid[ind] = wr->wr_id;
1700
1701                 if (likely(prev_wqe)) {
1702                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1703                                 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1704                         wmb();
1705                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1706                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1707                 }
1708
1709                 if (!size0)
1710                         size0 = size;
1711
1712                 ++ind;
1713                 if (unlikely(ind >= qp->rq.max))
1714                         ind -= qp->rq.max;
1715         }
1716
1717 out:
1718         if (likely(nreq)) {
1719                 u32 doorbell[2];
1720
1721                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1722                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1723
1724                 wmb();
1725
1726                 mthca_write64(doorbell,
1727                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1728                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1729         }
1730
1731         qp->rq.next_ind = ind;
1732         qp->rq.head    += nreq;
1733
1734         spin_unlock_irqrestore(&qp->rq.lock, flags);
1735         return err;
1736 }
1737
1738 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1739                           struct ib_send_wr **bad_wr)
1740 {
1741         struct mthca_dev *dev = to_mdev(ibqp->device);
1742         struct mthca_qp *qp = to_mqp(ibqp);
1743         void *wqe;
1744         void *prev_wqe;
1745         unsigned long flags;
1746         int err = 0;
1747         int nreq;
1748         int i;
1749         int size;
1750         int size0 = 0;
1751         u32 f0 = 0;
1752         int ind;
1753         u8 op0 = 0;
1754
1755         spin_lock_irqsave(&qp->sq.lock, flags);
1756
1757         /* XXX check that state is OK to post send */
1758
1759         ind = qp->sq.head & (qp->sq.max - 1);
1760
1761         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1762                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1763                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1764                                         " %d max, %d nreq)\n", qp->qpn,
1765                                         qp->sq.head, qp->sq.tail,
1766                                         qp->sq.max, nreq);
1767                         err = -ENOMEM;
1768                         *bad_wr = wr;
1769                         goto out;
1770                 }
1771
1772                 wqe = get_send_wqe(qp, ind);
1773                 prev_wqe = qp->sq.last;
1774                 qp->sq.last = wqe;
1775
1776                 ((struct mthca_next_seg *) wqe)->flags =
1777                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1778                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1779                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1780                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1781                         cpu_to_be32(1);
1782                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1783                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1784                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1785
1786                 wqe += sizeof (struct mthca_next_seg);
1787                 size = sizeof (struct mthca_next_seg) / 16;
1788
1789                 switch (qp->transport) {
1790                 case RC:
1791                         switch (wr->opcode) {
1792                         case IB_WR_ATOMIC_CMP_AND_SWP:
1793                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1794                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1795                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1796                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1797                                         cpu_to_be32(wr->wr.atomic.rkey);
1798                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1799
1800                                 wqe += sizeof (struct mthca_raddr_seg);
1801
1802                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1803                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1804                                                 cpu_to_be64(wr->wr.atomic.swap);
1805                                         ((struct mthca_atomic_seg *) wqe)->compare =
1806                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1807                                 } else {
1808                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1809                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1810                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1811                                 }
1812
1813                                 wqe += sizeof (struct mthca_atomic_seg);
1814                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1815                                         sizeof (struct mthca_atomic_seg);
1816                                 break;
1817
1818                         case IB_WR_RDMA_WRITE:
1819                         case IB_WR_RDMA_WRITE_WITH_IMM:
1820                         case IB_WR_RDMA_READ:
1821                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1822                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1823                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1824                                         cpu_to_be32(wr->wr.rdma.rkey);
1825                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1826                                 wqe += sizeof (struct mthca_raddr_seg);
1827                                 size += sizeof (struct mthca_raddr_seg) / 16;
1828                                 break;
1829
1830                         default:
1831                                 /* No extra segments required for sends */
1832                                 break;
1833                         }
1834
1835                         break;
1836
1837                 case UD:
1838                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1839                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1840                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1841                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1842                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1843                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1844
1845                         wqe += sizeof (struct mthca_arbel_ud_seg);
1846                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1847                         break;
1848
1849                 case MLX:
1850                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1851                                                wqe - sizeof (struct mthca_next_seg),
1852                                                wqe);
1853                         if (err) {
1854                                 *bad_wr = wr;
1855                                 goto out;
1856                         }
1857                         wqe += sizeof (struct mthca_data_seg);
1858                         size += sizeof (struct mthca_data_seg) / 16;
1859                         break;
1860                 }
1861
1862                 if (wr->num_sge > qp->sq.max_gs) {
1863                         mthca_err(dev, "too many gathers\n");
1864                         err = -EINVAL;
1865                         *bad_wr = wr;
1866                         goto out;
1867                 }
1868
1869                 for (i = 0; i < wr->num_sge; ++i) {
1870                         ((struct mthca_data_seg *) wqe)->byte_count =
1871                                 cpu_to_be32(wr->sg_list[i].length);
1872                         ((struct mthca_data_seg *) wqe)->lkey =
1873                                 cpu_to_be32(wr->sg_list[i].lkey);
1874                         ((struct mthca_data_seg *) wqe)->addr =
1875                                 cpu_to_be64(wr->sg_list[i].addr);
1876                         wqe += sizeof (struct mthca_data_seg);
1877                         size += sizeof (struct mthca_data_seg) / 16;
1878                 }
1879
1880                 /* Add one more inline data segment for ICRC */
1881                 if (qp->transport == MLX) {
1882                         ((struct mthca_data_seg *) wqe)->byte_count =
1883                                 cpu_to_be32((1 << 31) | 4);
1884                         ((u32 *) wqe)[1] = 0;
1885                         wqe += sizeof (struct mthca_data_seg);
1886                         size += sizeof (struct mthca_data_seg) / 16;
1887                 }
1888
1889                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1890
1891                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1892                         mthca_err(dev, "opcode invalid\n");
1893                         err = -EINVAL;
1894                         *bad_wr = wr;
1895                         goto out;
1896                 }
1897
1898                 if (likely(prev_wqe)) {
1899                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1900                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1901                                              qp->send_wqe_offset) |
1902                                             mthca_opcode[wr->opcode]);
1903                         wmb();
1904                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1905                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1906                 }
1907
1908                 if (!size0) {
1909                         size0 = size;
1910                         op0   = mthca_opcode[wr->opcode];
1911                 }
1912
1913                 ++ind;
1914                 if (unlikely(ind >= qp->sq.max))
1915                         ind -= qp->sq.max;
1916         }
1917
1918 out:
1919         if (likely(nreq)) {
1920                 u32 doorbell[2];
1921
1922                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1923                                           ((qp->sq.head & 0xffff) << 8) |
1924                                           f0 | op0);
1925                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1926
1927                 qp->sq.head += nreq;
1928
1929                 /*
1930                  * Make sure that descriptors are written before
1931                  * doorbell record.
1932                  */
1933                 wmb();
1934                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1935
1936                 /*
1937                  * Make sure doorbell record is written before we
1938                  * write MMIO send doorbell.
1939                  */
1940                 wmb();
1941                 mthca_write64(doorbell,
1942                               dev->kar + MTHCA_SEND_DOORBELL,
1943                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1944         }
1945
1946         spin_unlock_irqrestore(&qp->sq.lock, flags);
1947         return err;
1948 }
1949
1950 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1951                              struct ib_recv_wr **bad_wr)
1952 {
1953         struct mthca_dev *dev = to_mdev(ibqp->device);
1954         struct mthca_qp *qp = to_mqp(ibqp);
1955         unsigned long flags;
1956         int err = 0;
1957         int nreq;
1958         int ind;
1959         int i;
1960         void *wqe;
1961
1962         spin_lock_irqsave(&qp->rq.lock, flags);
1963
1964         /* XXX check that state is OK to post receive */
1965
1966         ind = qp->rq.head & (qp->rq.max - 1);
1967
1968         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1969                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1970                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1971                                         " %d max, %d nreq)\n", qp->qpn,
1972                                         qp->rq.head, qp->rq.tail,
1973                                         qp->rq.max, nreq);
1974                         err = -ENOMEM;
1975                         *bad_wr = wr;
1976                         goto out;
1977                 }
1978
1979                 wqe = get_recv_wqe(qp, ind);
1980
1981                 ((struct mthca_next_seg *) wqe)->flags = 0;
1982
1983                 wqe += sizeof (struct mthca_next_seg);
1984
1985                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1986                         err = -EINVAL;
1987                         *bad_wr = wr;
1988                         goto out;
1989                 }
1990
1991                 for (i = 0; i < wr->num_sge; ++i) {
1992                         ((struct mthca_data_seg *) wqe)->byte_count =
1993                                 cpu_to_be32(wr->sg_list[i].length);
1994                         ((struct mthca_data_seg *) wqe)->lkey =
1995                                 cpu_to_be32(wr->sg_list[i].lkey);
1996                         ((struct mthca_data_seg *) wqe)->addr =
1997                                 cpu_to_be64(wr->sg_list[i].addr);
1998                         wqe += sizeof (struct mthca_data_seg);
1999                 }
2000
2001                 if (i < qp->rq.max_gs) {
2002                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2003                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2004                         ((struct mthca_data_seg *) wqe)->addr = 0;
2005                 }
2006
2007                 qp->wrid[ind] = wr->wr_id;
2008
2009                 ++ind;
2010                 if (unlikely(ind >= qp->rq.max))
2011                         ind -= qp->rq.max;
2012         }
2013 out:
2014         if (likely(nreq)) {
2015                 qp->rq.head += nreq;
2016
2017                 /*
2018                  * Make sure that descriptors are written before
2019                  * doorbell record.
2020                  */
2021                 wmb();
2022                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2023         }
2024
2025         spin_unlock_irqrestore(&qp->rq.lock, flags);
2026         return err;
2027 }
2028
2029 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2030                        int index, int *dbd, u32 *new_wqe)
2031 {
2032         struct mthca_next_seg *next;
2033
2034         if (is_send)
2035                 next = get_send_wqe(qp, index);
2036         else
2037                 next = get_recv_wqe(qp, index);
2038
2039         if (mthca_is_memfree(dev))
2040                 *dbd = 1;
2041         else
2042                 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2043         if (next->ee_nds & cpu_to_be32(0x3f))
2044                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2045                         (next->ee_nds & cpu_to_be32(0x3f));
2046         else
2047                 *new_wqe = 0;
2048
2049         return 0;
2050 }
2051
2052 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2053 {
2054         int err;
2055         u8 status;
2056         int i;
2057
2058         spin_lock_init(&dev->qp_table.lock);
2059
2060         /*
2061          * We reserve 2 extra QPs per port for the special QPs.  The
2062          * special QP for port 1 has to be even, so round up.
2063          */
2064         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2065         err = mthca_alloc_init(&dev->qp_table.alloc,
2066                                dev->limits.num_qps,
2067                                (1 << 24) - 1,
2068                                dev->qp_table.sqp_start +
2069                                MTHCA_MAX_PORTS * 2);
2070         if (err)
2071                 return err;
2072
2073         err = mthca_array_init(&dev->qp_table.qp,
2074                                dev->limits.num_qps);
2075         if (err) {
2076                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2077                 return err;
2078         }
2079
2080         for (i = 0; i < 2; ++i) {
2081                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2082                                             dev->qp_table.sqp_start + i * 2,
2083                                             &status);
2084                 if (err)
2085                         goto err_out;
2086                 if (status) {
2087                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2088                                    "status %02x, aborting.\n",
2089                                    status);
2090                         err = -EINVAL;
2091                         goto err_out;
2092                 }
2093         }
2094         return 0;
2095
2096  err_out:
2097         for (i = 0; i < 2; ++i)
2098                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2099
2100         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2101         mthca_alloc_cleanup(&dev->qp_table.alloc);
2102
2103         return err;
2104 }
2105
2106 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2107 {
2108         int i;
2109         u8 status;
2110
2111         for (i = 0; i < 2; ++i)
2112                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2113
2114         mthca_alloc_cleanup(&dev->qp_table.alloc);
2115 }