drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PKEY_INDEX            |
 387                                          IB_QP_PATH_MIG_STATE),
 388                                 [RC]  = (IB_QP_CUR_STATE             |
 389                                          IB_QP_ALT_PATH              |
 390                                          IB_QP_ACCESS_FLAGS          |
 391                                          IB_QP_PKEY_INDEX            |
 392                                          IB_QP_MIN_RNR_TIMER         |
 393                                          IB_QP_PATH_MIG_STATE),
 394                                 [MLX] = (IB_QP_CUR_STATE             |
 395                                          IB_QP_QKEY),
 396                         }
 397                 }
 398         },
 399         [IB_QPS_RTS]   = {
 400                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 401                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 402                 [IB_QPS_RTS]   = {
 403                         .trans = MTHCA_TRANS_RTS2RTS,
 404                         .opt_param = {
 405                                 [UD]  = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 408                                          IB_QP_ALT_PATH              |
 409                                          IB_QP_PATH_MIG_STATE),
 410                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_PATH_MIG_STATE        |
 413                                          IB_QP_MIN_RNR_TIMER),
 414                                 [MLX] = (IB_QP_CUR_STATE             |
 415                                          IB_QP_QKEY),
 416                         }
 417                 },
 418                 [IB_QPS_SQD]   = {
 419                         .trans = MTHCA_TRANS_RTS2SQD,
 420                 },
 421         },
 422         [IB_QPS_SQD]   = {
 423                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 424                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 425                 [IB_QPS_RTS]   = {
 426                         .trans = MTHCA_TRANS_SQD2RTS,
 427                         .opt_param = {
 428                                 [UD]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                                 [UC]  = (IB_QP_CUR_STATE             |
 431                                          IB_QP_ALT_PATH              |
 432                                          IB_QP_ACCESS_FLAGS          |
 433                                          IB_QP_PATH_MIG_STATE),
 434                                 [RC]  = (IB_QP_CUR_STATE             |
 435                                          IB_QP_ALT_PATH              |
 436                                          IB_QP_ACCESS_FLAGS          |
 437                                          IB_QP_MIN_RNR_TIMER         |
 438                                          IB_QP_PATH_MIG_STATE),
 439                                 [MLX] = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                         }
 442                 },
 443                 [IB_QPS_SQD]   = {
 444                         .trans = MTHCA_TRANS_SQD2SQD,
 445                         .opt_param = {
 446                                 [UD]  = (IB_QP_PKEY_INDEX            |
 447                                          IB_QP_QKEY),
 448                                 [UC]  = (IB_QP_AV                    |
 449                                          IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_PKEY_INDEX            |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [RC]  = (IB_QP_AV                    |
 455                                          IB_QP_TIMEOUT               |
 456                                          IB_QP_RETRY_CNT             |
 457                                          IB_QP_RNR_RETRY             |
 458                                          IB_QP_MAX_QP_RD_ATOMIC      |
 459                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 460                                          IB_QP_CUR_STATE             |
 461                                          IB_QP_ALT_PATH              |
 462                                          IB_QP_ACCESS_FLAGS          |
 463                                          IB_QP_PKEY_INDEX            |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_PKEY_INDEX            |
 467                                          IB_QP_QKEY),
 468                         }
 469                 }
 470         },
 471         [IB_QPS_SQE]   = {
 472                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 473                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 474                 [IB_QPS_RTS]   = {
 475                         .trans = MTHCA_TRANS_SQERR2RTS,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_QKEY),
 479                                 [UC]  = IB_QP_CUR_STATE,
 480                                 [RC]  = (IB_QP_CUR_STATE             |
 481                                          IB_QP_MIN_RNR_TIMER),
 482                                 [MLX] = (IB_QP_CUR_STATE             |
 483                                          IB_QP_QKEY),
 484                         }
 485                 }
 486         },
 487         [IB_QPS_ERR] = {
 488                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 489                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 490         }
 491 };
 492
 493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 494                         int attr_mask)
 495 {
 496         if (attr_mask & IB_QP_PKEY_INDEX)
 497                 sqp->pkey_index = attr->pkey_index;
 498         if (attr_mask & IB_QP_QKEY)
 499                 sqp->qkey = attr->qkey;
 500         if (attr_mask & IB_QP_SQ_PSN)
 501                 sqp->send_psn = attr->sq_psn;
 502 }
 503
 504 static void init_port(struct mthca_dev *dev, int port)
 505 {
 506         int err;
 507         u8 status;
 508         struct mthca_init_ib_param param;
 509
 510         memset(&param, 0, sizeof param);
 511
 512         param.port_width = dev->limits.port_width_cap;
 513         param.vl_cap     = dev->limits.vl_cap;
 514         param.mtu_cap    = dev->limits.mtu_cap;
 515         param.gid_cap    = dev->limits.gid_table_len;
 516         param.pkey_cap   = dev->limits.pkey_table_len;
 517
 518         err = mthca_INIT_IB(dev, &param, port, &status);
 519         if (err)
 520                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 521         if (status)
 522                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 523 }
 524
 525 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 526 {
 527         struct mthca_dev *dev = to_mdev(ibqp->device);
 528         struct mthca_qp *qp = to_mqp(ibqp);
 529         enum ib_qp_state cur_state, new_state;
 530         struct mthca_mailbox *mailbox;
 531         struct mthca_qp_param *qp_param;
 532         struct mthca_qp_context *qp_context;
 533         u32 req_param, opt_param;
 534         u8 status;
 535         int err;
 536
 537         if (attr_mask & IB_QP_CUR_STATE) {
 538                 if (attr->cur_qp_state != IB_QPS_RTR &&
 539                     attr->cur_qp_state != IB_QPS_RTS &&
 540                     attr->cur_qp_state != IB_QPS_SQD &&
 541                     attr->cur_qp_state != IB_QPS_SQE)
 542                         return -EINVAL;
 543                 else
 544                         cur_state = attr->cur_qp_state;
 545         } else {
 546                 spin_lock_irq(&qp->sq.lock);
 547                 spin_lock(&qp->rq.lock);
 548                 cur_state = qp->state;
 549                 spin_unlock(&qp->rq.lock);
 550                 spin_unlock_irq(&qp->sq.lock);
 551         }
 552
 553         if (attr_mask & IB_QP_STATE) {
 554                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 555                         return -EINVAL;
 556                 new_state = attr->qp_state;
 557         } else
 558                 new_state = cur_state;
 559
 560         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 561                 mthca_dbg(dev, "Illegal QP transition "
 562                           "%d->%d\n", cur_state, new_state);
 563                 return -EINVAL;
 564         }
 565
 566         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 567         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 568
 569         if ((req_param & attr_mask) != req_param) {
 570                 mthca_dbg(dev, "QP transition "
 571                           "%d->%d missing req attr 0x%08x\n",
 572                           cur_state, new_state,
 573                           req_param & ~attr_mask);
 574                 return -EINVAL;
 575         }
 576
 577         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 578                 mthca_dbg(dev, "QP transition (transport %d) "
 579                           "%d->%d has extra attr 0x%08x\n",
 580                           qp->transport,
 581                           cur_state, new_state,
 582                           attr_mask & ~(req_param | opt_param |
 583                                                  IB_QP_STATE));
 584                 return -EINVAL;
 585         }
 586
 587         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 588         if (IS_ERR(mailbox))
 589                 return PTR_ERR(mailbox);
 590         qp_param = mailbox->buf;
 591         qp_context = &qp_param->context;
 592         memset(qp_param, 0, sizeof *qp_param);
 593
 594         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 595                                              (to_mthca_st(qp->transport) << 16));
 596         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 597         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 598                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 599         else {
 600                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 601                 switch (attr->path_mig_state) {
 602                 case IB_MIG_MIGRATED:
 603                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 604                         break;
 605                 case IB_MIG_REARM:
 606                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 607                         break;
 608                 case IB_MIG_ARMED:
 609                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 610                         break;
 611                 }
 612         }
 613
 614         /* leave tavor_sched_queue as 0 */
 615
 616         if (qp->transport == MLX || qp->transport == UD)
 617                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 618         else if (attr_mask & IB_QP_PATH_MTU)
 619                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 620
 621         if (mthca_is_memfree(dev)) {
 622                 if (qp->rq.max)
 623                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 624                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 625
 626                 if (qp->sq.max)
 627                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 628                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 629         }
 630
 631         /* leave arbel_sched_queue as 0 */
 632
 633         if (qp->ibqp.uobject)
 634                 qp_context->usr_page =
 635                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 636         else
 637                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 638         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 639         if (attr_mask & IB_QP_DEST_QPN) {
 640                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 641         }
 642
 643         if (qp->transport == MLX)
 644                 qp_context->pri_path.port_pkey |=
 645                         cpu_to_be32(to_msqp(qp)->port << 24);
 646         else {
 647                 if (attr_mask & IB_QP_PORT) {
 648                         qp_context->pri_path.port_pkey |=
 649                                 cpu_to_be32(attr->port_num << 24);
 650                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 651                 }
 652         }
 653
 654         if (attr_mask & IB_QP_PKEY_INDEX) {
 655                 qp_context->pri_path.port_pkey |=
 656                         cpu_to_be32(attr->pkey_index);
 657                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 658         }
 659
 660         if (attr_mask & IB_QP_RNR_RETRY) {
 661                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 662                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 663         }
 664
 665         if (attr_mask & IB_QP_AV) {
 666                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 667                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 668                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 669                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 670                         qp_context->pri_path.g_mylmc |= 1 << 7;
 671                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 672                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 673                         qp_context->pri_path.sl_tclass_flowlabel =
 674                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 675                                             (attr->ah_attr.grh.traffic_class << 20) |
 676                                             (attr->ah_attr.grh.flow_label));
 677                         memcpy(qp_context->pri_path.rgid,
 678                                attr->ah_attr.grh.dgid.raw, 16);
 679                 } else {
 680                         qp_context->pri_path.sl_tclass_flowlabel =
 681                                 cpu_to_be32(attr->ah_attr.sl << 28);
 682                 }
 683                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 684         }
 685
 686         if (attr_mask & IB_QP_TIMEOUT) {
 687                 qp_context->pri_path.ackto = attr->timeout << 3;
 688                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 689         }
 690
 691         /* XXX alt_path */
 692
 693         /* leave rdd as 0 */
 694         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 695         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 696         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 697         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 698                                              (MTHCA_FLIGHT_LIMIT << 24) |
 699                                              MTHCA_QP_BIT_SRE           |
 700                                              MTHCA_QP_BIT_SWE           |
 701                                              MTHCA_QP_BIT_SAE);
 702         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 703                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 704         if (attr_mask & IB_QP_RETRY_CNT) {
 705                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 706                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 707         }
 708
 709         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 710                 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
 711                                                        ffs(attr->max_rd_atomic) - 1 : 0,
 712                                                        7) << 21);
 713                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 714         }
 715
 716         if (attr_mask & IB_QP_SQ_PSN)
 717                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 718         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 719
 720         if (mthca_is_memfree(dev)) {
 721                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 722                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 723         }
 724
 725         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 726                 /*
 727                  * Only enable RDMA/atomics if we have responder
 728                  * resources set to a non-zero value.
 729                  */
 730                 if (qp->resp_depth) {
 731                         qp_context->params2 |=
 732                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 733                                             MTHCA_QP_BIT_RWE : 0);
 734                         qp_context->params2 |=
 735                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 736                                             MTHCA_QP_BIT_RRE : 0);
 737                         qp_context->params2 |=
 738                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 739                                             MTHCA_QP_BIT_RAE : 0);
 740                 }
 741
 742                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 743                                                         MTHCA_QP_OPTPAR_RRE |
 744                                                         MTHCA_QP_OPTPAR_RAE);
 745
 746                 qp->atomic_rd_en = attr->qp_access_flags;
 747         }
 748
 749         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 750                 u8 rra_max;
 751
 752                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 753                         /*
 754                          * Lowering our responder resources to zero.
 755                          * Turn off RDMA/atomics as responder.
 756                          * (RWE/RRE/RAE in params2 already zero)
 757                          */
 758                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 759                                                                 MTHCA_QP_OPTPAR_RRE |
 760                                                                 MTHCA_QP_OPTPAR_RAE);
 761                 }
 762
 763                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 764                         /*
 765                          * Increasing our responder resources from
 766                          * zero.  Turn on RDMA/atomics as appropriate.
 767                          */
 768                         qp_context->params2 |=
 769                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 770                                             MTHCA_QP_BIT_RWE : 0);
 771                         qp_context->params2 |=
 772                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 773                                             MTHCA_QP_BIT_RRE : 0);
 774                         qp_context->params2 |=
 775                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 776                                             MTHCA_QP_BIT_RAE : 0);
 777
 778                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 779                                                                 MTHCA_QP_OPTPAR_RRE |
 780                                                                 MTHCA_QP_OPTPAR_RAE);
 781                 }
 782
 783                 for (rra_max = 0;
 784                      1 << rra_max < attr->max_dest_rd_atomic &&
 785                              rra_max < dev->qp_table.rdb_shift;
 786                      ++rra_max)
 787                         ; /* nothing */
 788
 789                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 790                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 791
 792                 qp->resp_depth = attr->max_dest_rd_atomic;
 793         }
 794
 795         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 796
 797         if (ibqp->srq)
 798                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 799
 800         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 801                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 802                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 803         }
 804         if (attr_mask & IB_QP_RQ_PSN)
 805                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 806
 807         qp_context->ra_buff_indx =
 808                 cpu_to_be32(dev->qp_table.rdb_base +
 809                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 810                              dev->qp_table.rdb_shift));
 811
 812         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 813
 814         if (mthca_is_memfree(dev))
 815                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 816
 817         if (attr_mask & IB_QP_QKEY) {
 818                 qp_context->qkey = cpu_to_be32(attr->qkey);
 819                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 820         }
 821
 822         if (ibqp->srq)
 823                 qp_context->srqn = cpu_to_be32(1 << 24 |
 824                                                to_msrq(ibqp->srq)->srqn);
 825
 826         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 827                               qp->qpn, 0, mailbox, 0, &status);
 828         if (status) {
 829                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 830                            state_table[cur_state][new_state].trans, status);
 831                 err = -EINVAL;
 832         }
 833
 834         if (!err)
 835                 qp->state = new_state;
 836
 837         mthca_free_mailbox(dev, mailbox);
 838
 839         if (is_sqp(dev, qp))
 840                 store_attrs(to_msqp(qp), attr, attr_mask);
 841
 842         /*
 843          * If we moved QP0 to RTR, bring the IB link up; if we moved
 844          * QP0 to RESET or ERROR, bring the link back down.
 845          */
 846         if (is_qp0(dev, qp)) {
 847                 if (cur_state != IB_QPS_RTR &&
 848                     new_state == IB_QPS_RTR)
 849                         init_port(dev, to_msqp(qp)->port);
 850
 851                 if (cur_state != IB_QPS_RESET &&
 852                     cur_state != IB_QPS_ERR &&
 853                     (new_state == IB_QPS_RESET ||
 854                      new_state == IB_QPS_ERR))
 855                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 856         }
 857
 858         /*
 859          * If we moved a kernel QP to RESET, clean up all old CQ
 860          * entries and reinitialize the QP.
 861          */
 862         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 863                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 864                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 865                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 866                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 867                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 868
 869                 mthca_wq_init(&qp->sq);
 870                 mthca_wq_init(&qp->rq);
 871
 872                 if (mthca_is_memfree(dev)) {
 873                         *qp->sq.db = 0;
 874                         *qp->rq.db = 0;
 875                 }
 876         }
 877
 878         return err;
 879 }
 880
 881 /*
 882  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 883  * rq.max_gs and sq.max_gs must all be assigned.
 884  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 885  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 886  * queue)
 887  */
 888 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 889                                struct mthca_pd *pd,
 890                                struct mthca_qp *qp)
 891 {
 892         int size;
 893         int err = -ENOMEM;
 894
 895         size = sizeof (struct mthca_next_seg) +
 896                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 897
 898         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 899              qp->rq.wqe_shift++)
 900                 ; /* nothing */
 901
 902         size = sizeof (struct mthca_next_seg) +
 903                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 904         switch (qp->transport) {
 905         case MLX:
 906                 size += 2 * sizeof (struct mthca_data_seg);
 907                 break;
 908         case UD:
 909                 if (mthca_is_memfree(dev))
 910                         size += sizeof (struct mthca_arbel_ud_seg);
 911                 else
 912                         size += sizeof (struct mthca_tavor_ud_seg);
 913                 break;
 914         default:
 915                 /* bind seg is as big as atomic + raddr segs */
 916                 size += sizeof (struct mthca_bind_seg);
 917         }
 918
 919         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 920              qp->sq.wqe_shift++)
 921                 ; /* nothing */
 922
 923         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 924                                     1 << qp->sq.wqe_shift);
 925
 926         /*
 927          * If this is a userspace QP, we don't actually have to
 928          * allocate anything.  All we need is to calculate the WQE
 929          * sizes and the send_wqe_offset, so we're done now.
 930          */
 931         if (pd->ibpd.uobject)
 932                 return 0;
 933
 934         size = PAGE_ALIGN(qp->send_wqe_offset +
 935                           (qp->sq.max << qp->sq.wqe_shift));
 936
 937         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 938                            GFP_KERNEL);
 939         if (!qp->wrid)
 940                 goto err_out;
 941
 942         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
 943                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
 944         if (err)
 945                 goto err_out;
 946
 947         return 0;
 948
 949 err_out:
 950         kfree(qp->wrid);
 951         return err;
 952 }
 953
 954 static void mthca_free_wqe_buf(struct mthca_dev *dev,
 955                                struct mthca_qp *qp)
 956 {
 957         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
 958                                        (qp->sq.max << qp->sq.wqe_shift)),
 959                        &qp->queue, qp->is_direct, &qp->mr);
 960         kfree(qp->wrid);
 961 }
 962
 963 static int mthca_map_memfree(struct mthca_dev *dev,
 964                              struct mthca_qp *qp)
 965 {
 966         int ret;
 967
 968         if (mthca_is_memfree(dev)) {
 969                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
 970                 if (ret)
 971                         return ret;
 972
 973                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
 974                 if (ret)
 975                         goto err_qpc;
 976
 977                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
 978                                       qp->qpn << dev->qp_table.rdb_shift);
 979                 if (ret)
 980                         goto err_eqpc;
 981
 982         }
 983
 984         return 0;
 985
 986 err_eqpc:
 987         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
 988
 989 err_qpc:
 990         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
 991
 992         return ret;
 993 }
 994
 995 static void mthca_unmap_memfree(struct mthca_dev *dev,
 996                                 struct mthca_qp *qp)
 997 {
 998         mthca_table_put(dev, dev->qp_table.rdb_table,
 999                         qp->qpn << dev->qp_table.rdb_shift);
1000         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1001         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1002 }
1003
1004 static int mthca_alloc_memfree(struct mthca_dev *dev,
1005                                struct mthca_qp *qp)
1006 {
1007         int ret = 0;
1008
1009         if (mthca_is_memfree(dev)) {
1010                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1011                                                  qp->qpn, &qp->rq.db);
1012                 if (qp->rq.db_index < 0)
1013                         return ret;
1014
1015                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1016                                                  qp->qpn, &qp->sq.db);
1017                 if (qp->sq.db_index < 0)
1018                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1019         }
1020
1021         return ret;
1022 }
1023
1024 static void mthca_free_memfree(struct mthca_dev *dev,
1025                                struct mthca_qp *qp)
1026 {
1027         if (mthca_is_memfree(dev)) {
1028                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1029                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1030         }
1031 }
1032
1033 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1034                                  struct mthca_pd *pd,
1035                                  struct mthca_cq *send_cq,
1036                                  struct mthca_cq *recv_cq,
1037                                  enum ib_sig_type send_policy,
1038                                  struct mthca_qp *qp)
1039 {
1040         int ret;
1041         int i;
1042
1043         atomic_set(&qp->refcount, 1);
1044         init_waitqueue_head(&qp->wait);
1045         qp->state        = IB_QPS_RESET;
1046         qp->atomic_rd_en = 0;
1047         qp->resp_depth   = 0;
1048         qp->sq_policy    = send_policy;
1049         mthca_wq_init(&qp->sq);
1050         mthca_wq_init(&qp->rq);
1051
1052         ret = mthca_map_memfree(dev, qp);
1053         if (ret)
1054                 return ret;
1055
1056         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1057         if (ret) {
1058                 mthca_unmap_memfree(dev, qp);
1059                 return ret;
1060         }
1061
1062         /*
1063          * If this is a userspace QP, we're done now.  The doorbells
1064          * will be allocated and buffers will be initialized in
1065          * userspace.
1066          */
1067         if (pd->ibpd.uobject)
1068                 return 0;
1069
1070         ret = mthca_alloc_memfree(dev, qp);
1071         if (ret) {
1072                 mthca_free_wqe_buf(dev, qp);
1073                 mthca_unmap_memfree(dev, qp);
1074                 return ret;
1075         }
1076
1077         if (mthca_is_memfree(dev)) {
1078                 struct mthca_next_seg *next;
1079                 struct mthca_data_seg *scatter;
1080                 int size = (sizeof (struct mthca_next_seg) +
1081                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1082
1083                 for (i = 0; i < qp->rq.max; ++i) {
1084                         next = get_recv_wqe(qp, i);
1085                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1086                                                    qp->rq.wqe_shift);
1087                         next->ee_nds = cpu_to_be32(size);
1088
1089                         for (scatter = (void *) (next + 1);
1090                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1091                              ++scatter)
1092                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1093                 }
1094
1095                 for (i = 0; i < qp->sq.max; ++i) {
1096                         next = get_send_wqe(qp, i);
1097                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1098                                                     qp->sq.wqe_shift) +
1099                                                    qp->send_wqe_offset);
1100                 }
1101         }
1102
1103         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1104         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1105
1106         return 0;
1107 }
1108
1109 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1110                              struct mthca_qp *qp)
1111 {
1112         /* Sanity check QP size before proceeding */
1113         if (cap->max_send_wr  > dev->limits.max_wqes ||
1114             cap->max_recv_wr  > dev->limits.max_wqes ||
1115             cap->max_send_sge > dev->limits.max_sg   ||
1116             cap->max_recv_sge > dev->limits.max_sg)
1117                 return -EINVAL;
1118
1119         if (mthca_is_memfree(dev)) {
1120                 qp->rq.max = cap->max_recv_wr ?
1121                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1122                 qp->sq.max = cap->max_send_wr ?
1123                         roundup_pow_of_two(cap->max_send_wr) : 0;
1124         } else {
1125                 qp->rq.max = cap->max_recv_wr;
1126                 qp->sq.max = cap->max_send_wr;
1127         }
1128
1129         qp->rq.max_gs = cap->max_recv_sge;
1130         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1131                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1132                                     MTHCA_INLINE_CHUNK_SIZE) /
1133                               sizeof (struct mthca_data_seg));
1134
1135         /*
1136          * For MLX transport we need 2 extra S/G entries:
1137          * one for the header and one for the checksum at the end
1138          */
1139         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1140             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1141                 return -EINVAL;
1142
1143         return 0;
1144 }
1145
1146 int mthca_alloc_qp(struct mthca_dev *dev,
1147                    struct mthca_pd *pd,
1148                    struct mthca_cq *send_cq,
1149                    struct mthca_cq *recv_cq,
1150                    enum ib_qp_type type,
1151                    enum ib_sig_type send_policy,
1152                    struct ib_qp_cap *cap,
1153                    struct mthca_qp *qp)
1154 {
1155         int err;
1156
1157         err = mthca_set_qp_size(dev, cap, qp);
1158         if (err)
1159                 return err;
1160
1161         switch (type) {
1162         case IB_QPT_RC: qp->transport = RC; break;
1163         case IB_QPT_UC: qp->transport = UC; break;
1164         case IB_QPT_UD: qp->transport = UD; break;
1165         default: return -EINVAL;
1166         }
1167
1168         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1169         if (qp->qpn == -1)
1170                 return -ENOMEM;
1171
1172         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1173                                     send_policy, qp);
1174         if (err) {
1175                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1176                 return err;
1177         }
1178
1179         spin_lock_irq(&dev->qp_table.lock);
1180         mthca_array_set(&dev->qp_table.qp,
1181                         qp->qpn & (dev->limits.num_qps - 1), qp);
1182         spin_unlock_irq(&dev->qp_table.lock);
1183
1184         return 0;
1185 }
1186
1187 int mthca_alloc_sqp(struct mthca_dev *dev,
1188                     struct mthca_pd *pd,
1189                     struct mthca_cq *send_cq,
1190                     struct mthca_cq *recv_cq,
1191                     enum ib_sig_type send_policy,
1192                     struct ib_qp_cap *cap,
1193                     int qpn,
1194                     int port,
1195                     struct mthca_sqp *sqp)
1196 {
1197         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1198         int err;
1199
1200         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1201         if (err)
1202                 return err;
1203
1204         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1205         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1206                                              &sqp->header_dma, GFP_KERNEL);
1207         if (!sqp->header_buf)
1208                 return -ENOMEM;
1209
1210         spin_lock_irq(&dev->qp_table.lock);
1211         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1212                 err = -EBUSY;
1213         else
1214                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1215         spin_unlock_irq(&dev->qp_table.lock);
1216
1217         if (err)
1218                 goto err_out;
1219
1220         sqp->port = port;
1221         sqp->qp.qpn       = mqpn;
1222         sqp->qp.transport = MLX;
1223
1224         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1225                                     send_policy, &sqp->qp);
1226         if (err)
1227                 goto err_out_free;
1228
1229         atomic_inc(&pd->sqp_count);
1230
1231         return 0;
1232
1233  err_out_free:
1234         /*
1235          * Lock CQs here, so that CQ polling code can do QP lookup
1236          * without taking a lock.
1237          */
1238         spin_lock_irq(&send_cq->lock);
1239         if (send_cq != recv_cq)
1240                 spin_lock(&recv_cq->lock);
1241
1242         spin_lock(&dev->qp_table.lock);
1243         mthca_array_clear(&dev->qp_table.qp, mqpn);
1244         spin_unlock(&dev->qp_table.lock);
1245
1246         if (send_cq != recv_cq)
1247                 spin_unlock(&recv_cq->lock);
1248         spin_unlock_irq(&send_cq->lock);
1249
1250  err_out:
1251         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1252                           sqp->header_buf, sqp->header_dma);
1253
1254         return err;
1255 }
1256
1257 void mthca_free_qp(struct mthca_dev *dev,
1258                    struct mthca_qp *qp)
1259 {
1260         u8 status;
1261         struct mthca_cq *send_cq;
1262         struct mthca_cq *recv_cq;
1263
1264         send_cq = to_mcq(qp->ibqp.send_cq);
1265         recv_cq = to_mcq(qp->ibqp.recv_cq);
1266
1267         /*
1268          * Lock CQs here, so that CQ polling code can do QP lookup
1269          * without taking a lock.
1270          */
1271         spin_lock_irq(&send_cq->lock);
1272         if (send_cq != recv_cq)
1273                 spin_lock(&recv_cq->lock);
1274
1275         spin_lock(&dev->qp_table.lock);
1276         mthca_array_clear(&dev->qp_table.qp,
1277                           qp->qpn & (dev->limits.num_qps - 1));
1278         spin_unlock(&dev->qp_table.lock);
1279
1280         if (send_cq != recv_cq)
1281                 spin_unlock(&recv_cq->lock);
1282         spin_unlock_irq(&send_cq->lock);
1283
1284         atomic_dec(&qp->refcount);
1285         wait_event(qp->wait, !atomic_read(&qp->refcount));
1286
1287         if (qp->state != IB_QPS_RESET)
1288                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1289
1290         /*
1291          * If this is a userspace QP, the buffers, MR, CQs and so on
1292          * will be cleaned up in userspace, so all we have to do is
1293          * unref the mem-free tables and free the QPN in our table.
1294          */
1295         if (!qp->ibqp.uobject) {
1296                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1297                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1298                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1299                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1300                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1301
1302                 mthca_free_memfree(dev, qp);
1303                 mthca_free_wqe_buf(dev, qp);
1304         }
1305
1306         mthca_unmap_memfree(dev, qp);
1307
1308         if (is_sqp(dev, qp)) {
1309                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1310                 dma_free_coherent(&dev->pdev->dev,
1311                                   to_msqp(qp)->header_buf_size,
1312                                   to_msqp(qp)->header_buf,
1313                                   to_msqp(qp)->header_dma);
1314         } else
1315                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1316 }
1317
1318 /* Create UD header for an MLX send and build a data segment for it */
1319 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1320                             int ind, struct ib_send_wr *wr,
1321                             struct mthca_mlx_seg *mlx,
1322                             struct mthca_data_seg *data)
1323 {
1324         int header_size;
1325         int err;
1326         u16 pkey;
1327
1328         ib_ud_header_init(256, /* assume a MAD */
1329                           sqp->ud_header.grh_present,
1330                           &sqp->ud_header);
1331
1332         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1333         if (err)
1334                 return err;
1335         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1336         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1337                                   (sqp->ud_header.lrh.destination_lid ==
1338                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1339                                   (sqp->ud_header.lrh.service_level << 8));
1340         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1341         mlx->vcrc = 0;
1342
1343         switch (wr->opcode) {
1344         case IB_WR_SEND:
1345                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1346                 sqp->ud_header.immediate_present = 0;
1347                 break;
1348         case IB_WR_SEND_WITH_IMM:
1349                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1350                 sqp->ud_header.immediate_present = 1;
1351                 sqp->ud_header.immediate_data = wr->imm_data;
1352                 break;
1353         default:
1354                 return -EINVAL;
1355         }
1356
1357         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1358         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1359                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1360         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1361         if (!sqp->qp.ibqp.qp_num)
1362                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1363                                    sqp->pkey_index, &pkey);
1364         else
1365                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1366                                    wr->wr.ud.pkey_index, &pkey);
1367         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1368         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1369         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1370         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1371                                                sqp->qkey : wr->wr.ud.remote_qkey);
1372         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1373
1374         header_size = ib_ud_header_pack(&sqp->ud_header,
1375                                         sqp->header_buf +
1376                                         ind * MTHCA_UD_HEADER_SIZE);
1377
1378         data->byte_count = cpu_to_be32(header_size);
1379         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1380         data->addr       = cpu_to_be64(sqp->header_dma +
1381                                        ind * MTHCA_UD_HEADER_SIZE);
1382
1383         return 0;
1384 }
1385
1386 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1387                                     struct ib_cq *ib_cq)
1388 {
1389         unsigned cur;
1390         struct mthca_cq *cq;
1391
1392         cur = wq->head - wq->tail;
1393         if (likely(cur + nreq < wq->max))
1394                 return 0;
1395
1396         cq = to_mcq(ib_cq);
1397         spin_lock(&cq->lock);
1398         cur = wq->head - wq->tail;
1399         spin_unlock(&cq->lock);
1400
1401         return cur + nreq >= wq->max;
1402 }
1403
1404 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1405                           struct ib_send_wr **bad_wr)
1406 {
1407         struct mthca_dev *dev = to_mdev(ibqp->device);
1408         struct mthca_qp *qp = to_mqp(ibqp);
1409         void *wqe;
1410         void *prev_wqe;
1411         unsigned long flags;
1412         int err = 0;
1413         int nreq;
1414         int i;
1415         int size;
1416         int size0 = 0;
1417         u32 f0 = 0;
1418         int ind;
1419         u8 op0 = 0;
1420
1421         spin_lock_irqsave(&qp->sq.lock, flags);
1422
1423         /* XXX check that state is OK to post send */
1424
1425         ind = qp->sq.next_ind;
1426
1427         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1428                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1429                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1430                                         " %d max, %d nreq)\n", qp->qpn,
1431                                         qp->sq.head, qp->sq.tail,
1432                                         qp->sq.max, nreq);
1433                         err = -ENOMEM;
1434                         *bad_wr = wr;
1435                         goto out;
1436                 }
1437
1438                 wqe = get_send_wqe(qp, ind);
1439                 prev_wqe = qp->sq.last;
1440                 qp->sq.last = wqe;
1441
1442                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1443                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1444                 ((struct mthca_next_seg *) wqe)->flags =
1445                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1446                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1447                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1448                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1449                         cpu_to_be32(1);
1450                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1451                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1452                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1453
1454                 wqe += sizeof (struct mthca_next_seg);
1455                 size = sizeof (struct mthca_next_seg) / 16;
1456
1457                 switch (qp->transport) {
1458                 case RC:
1459                         switch (wr->opcode) {
1460                         case IB_WR_ATOMIC_CMP_AND_SWP:
1461                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1462                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1463                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1464                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1465                                         cpu_to_be32(wr->wr.atomic.rkey);
1466                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1467
1468                                 wqe += sizeof (struct mthca_raddr_seg);
1469
1470                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1471                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1472                                                 cpu_to_be64(wr->wr.atomic.swap);
1473                                         ((struct mthca_atomic_seg *) wqe)->compare =
1474                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1475                                 } else {
1476                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1477                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1478                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1479                                 }
1480
1481                                 wqe += sizeof (struct mthca_atomic_seg);
1482                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1483                                         sizeof (struct mthca_atomic_seg);
1484                                 break;
1485
1486                         case IB_WR_RDMA_WRITE:
1487                         case IB_WR_RDMA_WRITE_WITH_IMM:
1488                         case IB_WR_RDMA_READ:
1489                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1490                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1491                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1492                                         cpu_to_be32(wr->wr.rdma.rkey);
1493                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1494                                 wqe += sizeof (struct mthca_raddr_seg);
1495                                 size += sizeof (struct mthca_raddr_seg) / 16;
1496                                 break;
1497
1498                         default:
1499                                 /* No extra segments required for sends */
1500                                 break;
1501                         }
1502
1503                         break;
1504
1505                 case UC:
1506                         switch (wr->opcode) {
1507                         case IB_WR_RDMA_WRITE:
1508                         case IB_WR_RDMA_WRITE_WITH_IMM:
1509                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1510                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1511                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1512                                         cpu_to_be32(wr->wr.rdma.rkey);
1513                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1514                                 wqe += sizeof (struct mthca_raddr_seg);
1515                                 size += sizeof (struct mthca_raddr_seg) / 16;
1516                                 break;
1517
1518                         default:
1519                                 /* No extra segments required for sends */
1520                                 break;
1521                         }
1522
1523                         break;
1524
1525                 case UD:
1526                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1527                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1528                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1529                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1530                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1531                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1532                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1533                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1534
1535                         wqe += sizeof (struct mthca_tavor_ud_seg);
1536                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1537                         break;
1538
1539                 case MLX:
1540                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1541                                                wqe - sizeof (struct mthca_next_seg),
1542                                                wqe);
1543                         if (err) {
1544                                 *bad_wr = wr;
1545                                 goto out;
1546                         }
1547                         wqe += sizeof (struct mthca_data_seg);
1548                         size += sizeof (struct mthca_data_seg) / 16;
1549                         break;
1550                 }
1551
1552                 if (wr->num_sge > qp->sq.max_gs) {
1553                         mthca_err(dev, "too many gathers\n");
1554                         err = -EINVAL;
1555                         *bad_wr = wr;
1556                         goto out;
1557                 }
1558
1559                 for (i = 0; i < wr->num_sge; ++i) {
1560                         ((struct mthca_data_seg *) wqe)->byte_count =
1561                                 cpu_to_be32(wr->sg_list[i].length);
1562                         ((struct mthca_data_seg *) wqe)->lkey =
1563                                 cpu_to_be32(wr->sg_list[i].lkey);
1564                         ((struct mthca_data_seg *) wqe)->addr =
1565                                 cpu_to_be64(wr->sg_list[i].addr);
1566                         wqe += sizeof (struct mthca_data_seg);
1567                         size += sizeof (struct mthca_data_seg) / 16;
1568                 }
1569
1570                 /* Add one more inline data segment for ICRC */
1571                 if (qp->transport == MLX) {
1572                         ((struct mthca_data_seg *) wqe)->byte_count =
1573                                 cpu_to_be32((1 << 31) | 4);
1574                         ((u32 *) wqe)[1] = 0;
1575                         wqe += sizeof (struct mthca_data_seg);
1576                         size += sizeof (struct mthca_data_seg) / 16;
1577                 }
1578
1579                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1580
1581                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1582                         mthca_err(dev, "opcode invalid\n");
1583                         err = -EINVAL;
1584                         *bad_wr = wr;
1585                         goto out;
1586                 }
1587
1588                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1589                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1590                                      qp->send_wqe_offset) |
1591                                     mthca_opcode[wr->opcode]);
1592                 wmb();
1593                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1594                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1595
1596                 if (!size0) {
1597                         size0 = size;
1598                         op0   = mthca_opcode[wr->opcode];
1599                 }
1600
1601                 ++ind;
1602                 if (unlikely(ind >= qp->sq.max))
1603                         ind -= qp->sq.max;
1604         }
1605
1606 out:
1607         if (likely(nreq)) {
1608                 __be32 doorbell[2];
1609
1610                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1611                                            qp->send_wqe_offset) | f0 | op0);
1612                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1613
1614                 wmb();
1615
1616                 mthca_write64(doorbell,
1617                               dev->kar + MTHCA_SEND_DOORBELL,
1618                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1619         }
1620
1621         qp->sq.next_ind = ind;
1622         qp->sq.head    += nreq;
1623
1624         spin_unlock_irqrestore(&qp->sq.lock, flags);
1625         return err;
1626 }
1627
1628 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1629                              struct ib_recv_wr **bad_wr)
1630 {
1631         struct mthca_dev *dev = to_mdev(ibqp->device);
1632         struct mthca_qp *qp = to_mqp(ibqp);
1633         unsigned long flags;
1634         int err = 0;
1635         int nreq;
1636         int i;
1637         int size;
1638         int size0 = 0;
1639         int ind;
1640         void *wqe;
1641         void *prev_wqe;
1642
1643         spin_lock_irqsave(&qp->rq.lock, flags);
1644
1645         /* XXX check that state is OK to post receive */
1646
1647         ind = qp->rq.next_ind;
1648
1649         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1650                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1651                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1652                                         " %d max, %d nreq)\n", qp->qpn,
1653                                         qp->rq.head, qp->rq.tail,
1654                                         qp->rq.max, nreq);
1655                         err = -ENOMEM;
1656                         *bad_wr = wr;
1657                         goto out;
1658                 }
1659
1660                 wqe = get_recv_wqe(qp, ind);
1661                 prev_wqe = qp->rq.last;
1662                 qp->rq.last = wqe;
1663
1664                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1665                 ((struct mthca_next_seg *) wqe)->ee_nds =
1666                         cpu_to_be32(MTHCA_NEXT_DBD);
1667                 ((struct mthca_next_seg *) wqe)->flags = 0;
1668
1669                 wqe += sizeof (struct mthca_next_seg);
1670                 size = sizeof (struct mthca_next_seg) / 16;
1671
1672                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1673                         err = -EINVAL;
1674                         *bad_wr = wr;
1675                         goto out;
1676                 }
1677
1678                 for (i = 0; i < wr->num_sge; ++i) {
1679                         ((struct mthca_data_seg *) wqe)->byte_count =
1680                                 cpu_to_be32(wr->sg_list[i].length);
1681                         ((struct mthca_data_seg *) wqe)->lkey =
1682                                 cpu_to_be32(wr->sg_list[i].lkey);
1683                         ((struct mthca_data_seg *) wqe)->addr =
1684                                 cpu_to_be64(wr->sg_list[i].addr);
1685                         wqe += sizeof (struct mthca_data_seg);
1686                         size += sizeof (struct mthca_data_seg) / 16;
1687                 }
1688
1689                 qp->wrid[ind] = wr->wr_id;
1690
1691                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1692                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1693                 wmb();
1694                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1695                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1696
1697                 if (!size0)
1698                         size0 = size;
1699
1700                 ++ind;
1701                 if (unlikely(ind >= qp->rq.max))
1702                         ind -= qp->rq.max;
1703         }
1704
1705 out:
1706         if (likely(nreq)) {
1707                 __be32 doorbell[2];
1708
1709                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1710                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1711
1712                 wmb();
1713
1714                 mthca_write64(doorbell,
1715                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1716                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1717         }
1718
1719         qp->rq.next_ind = ind;
1720         qp->rq.head    += nreq;
1721
1722         spin_unlock_irqrestore(&qp->rq.lock, flags);
1723         return err;
1724 }
1725
1726 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1727                           struct ib_send_wr **bad_wr)
1728 {
1729         struct mthca_dev *dev = to_mdev(ibqp->device);
1730         struct mthca_qp *qp = to_mqp(ibqp);
1731         void *wqe;
1732         void *prev_wqe;
1733         unsigned long flags;
1734         int err = 0;
1735         int nreq;
1736         int i;
1737         int size;
1738         int size0 = 0;
1739         u32 f0 = 0;
1740         int ind;
1741         u8 op0 = 0;
1742
1743         spin_lock_irqsave(&qp->sq.lock, flags);
1744
1745         /* XXX check that state is OK to post send */
1746
1747         ind = qp->sq.head & (qp->sq.max - 1);
1748
1749         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1750                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1751                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1752                                         " %d max, %d nreq)\n", qp->qpn,
1753                                         qp->sq.head, qp->sq.tail,
1754                                         qp->sq.max, nreq);
1755                         err = -ENOMEM;
1756                         *bad_wr = wr;
1757                         goto out;
1758                 }
1759
1760                 wqe = get_send_wqe(qp, ind);
1761                 prev_wqe = qp->sq.last;
1762                 qp->sq.last = wqe;
1763
1764                 ((struct mthca_next_seg *) wqe)->flags =
1765                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1766                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1767                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1768                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1769                         cpu_to_be32(1);
1770                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1771                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1772                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1773
1774                 wqe += sizeof (struct mthca_next_seg);
1775                 size = sizeof (struct mthca_next_seg) / 16;
1776
1777                 switch (qp->transport) {
1778                 case RC:
1779                         switch (wr->opcode) {
1780                         case IB_WR_ATOMIC_CMP_AND_SWP:
1781                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1782                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1783                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1784                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1785                                         cpu_to_be32(wr->wr.atomic.rkey);
1786                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1787
1788                                 wqe += sizeof (struct mthca_raddr_seg);
1789
1790                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1791                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1792                                                 cpu_to_be64(wr->wr.atomic.swap);
1793                                         ((struct mthca_atomic_seg *) wqe)->compare =
1794                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1795                                 } else {
1796                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1797                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1798                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1799                                 }
1800
1801                                 wqe += sizeof (struct mthca_atomic_seg);
1802                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1803                                         sizeof (struct mthca_atomic_seg);
1804                                 break;
1805
1806                         case IB_WR_RDMA_READ:
1807                         case IB_WR_RDMA_WRITE:
1808                         case IB_WR_RDMA_WRITE_WITH_IMM:
1809                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1810                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1811                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1812                                         cpu_to_be32(wr->wr.rdma.rkey);
1813                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1814                                 wqe += sizeof (struct mthca_raddr_seg);
1815                                 size += sizeof (struct mthca_raddr_seg) / 16;
1816                                 break;
1817
1818                         default:
1819                                 /* No extra segments required for sends */
1820                                 break;
1821                         }
1822
1823                         break;
1824
1825                 case UC:
1826                         switch (wr->opcode) {
1827                         case IB_WR_RDMA_WRITE:
1828                         case IB_WR_RDMA_WRITE_WITH_IMM:
1829                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1830                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1831                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1832                                         cpu_to_be32(wr->wr.rdma.rkey);
1833                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1834                                 wqe += sizeof (struct mthca_raddr_seg);
1835                                 size += sizeof (struct mthca_raddr_seg) / 16;
1836                                 break;
1837
1838                         default:
1839                                 /* No extra segments required for sends */
1840                                 break;
1841                         }
1842
1843                         break;
1844
1845                 case UD:
1846                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1847                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1848                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1849                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1850                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1851                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1852
1853                         wqe += sizeof (struct mthca_arbel_ud_seg);
1854                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1855                         break;
1856
1857                 case MLX:
1858                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1859                                                wqe - sizeof (struct mthca_next_seg),
1860                                                wqe);
1861                         if (err) {
1862                                 *bad_wr = wr;
1863                                 goto out;
1864                         }
1865                         wqe += sizeof (struct mthca_data_seg);
1866                         size += sizeof (struct mthca_data_seg) / 16;
1867                         break;
1868                 }
1869
1870                 if (wr->num_sge > qp->sq.max_gs) {
1871                         mthca_err(dev, "too many gathers\n");
1872                         err = -EINVAL;
1873                         *bad_wr = wr;
1874                         goto out;
1875                 }
1876
1877                 for (i = 0; i < wr->num_sge; ++i) {
1878                         ((struct mthca_data_seg *) wqe)->byte_count =
1879                                 cpu_to_be32(wr->sg_list[i].length);
1880                         ((struct mthca_data_seg *) wqe)->lkey =
1881                                 cpu_to_be32(wr->sg_list[i].lkey);
1882                         ((struct mthca_data_seg *) wqe)->addr =
1883                                 cpu_to_be64(wr->sg_list[i].addr);
1884                         wqe += sizeof (struct mthca_data_seg);
1885                         size += sizeof (struct mthca_data_seg) / 16;
1886                 }
1887
1888                 /* Add one more inline data segment for ICRC */
1889                 if (qp->transport == MLX) {
1890                         ((struct mthca_data_seg *) wqe)->byte_count =
1891                                 cpu_to_be32((1 << 31) | 4);
1892                         ((u32 *) wqe)[1] = 0;
1893                         wqe += sizeof (struct mthca_data_seg);
1894                         size += sizeof (struct mthca_data_seg) / 16;
1895                 }
1896
1897                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1898
1899                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1900                         mthca_err(dev, "opcode invalid\n");
1901                         err = -EINVAL;
1902                         *bad_wr = wr;
1903                         goto out;
1904                 }
1905
1906                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1907                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1908                                      qp->send_wqe_offset) |
1909                                     mthca_opcode[wr->opcode]);
1910                 wmb();
1911                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1912                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1913
1914                 if (!size0) {
1915                         size0 = size;
1916                         op0   = mthca_opcode[wr->opcode];
1917                 }
1918
1919                 ++ind;
1920                 if (unlikely(ind >= qp->sq.max))
1921                         ind -= qp->sq.max;
1922         }
1923
1924 out:
1925         if (likely(nreq)) {
1926                 __be32 doorbell[2];
1927
1928                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1929                                           ((qp->sq.head & 0xffff) << 8) |
1930                                           f0 | op0);
1931                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1932
1933                 qp->sq.head += nreq;
1934
1935                 /*
1936                  * Make sure that descriptors are written before
1937                  * doorbell record.
1938                  */
1939                 wmb();
1940                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1941
1942                 /*
1943                  * Make sure doorbell record is written before we
1944                  * write MMIO send doorbell.
1945                  */
1946                 wmb();
1947                 mthca_write64(doorbell,
1948                               dev->kar + MTHCA_SEND_DOORBELL,
1949                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1950         }
1951
1952         spin_unlock_irqrestore(&qp->sq.lock, flags);
1953         return err;
1954 }
1955
1956 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1957                              struct ib_recv_wr **bad_wr)
1958 {
1959         struct mthca_dev *dev = to_mdev(ibqp->device);
1960         struct mthca_qp *qp = to_mqp(ibqp);
1961         unsigned long flags;
1962         int err = 0;
1963         int nreq;
1964         int ind;
1965         int i;
1966         void *wqe;
1967
1968         spin_lock_irqsave(&qp->rq.lock, flags);
1969
1970         /* XXX check that state is OK to post receive */
1971
1972         ind = qp->rq.head & (qp->rq.max - 1);
1973
1974         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1975                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1976                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1977                                         " %d max, %d nreq)\n", qp->qpn,
1978                                         qp->rq.head, qp->rq.tail,
1979                                         qp->rq.max, nreq);
1980                         err = -ENOMEM;
1981                         *bad_wr = wr;
1982                         goto out;
1983                 }
1984
1985                 wqe = get_recv_wqe(qp, ind);
1986
1987                 ((struct mthca_next_seg *) wqe)->flags = 0;
1988
1989                 wqe += sizeof (struct mthca_next_seg);
1990
1991                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1992                         err = -EINVAL;
1993                         *bad_wr = wr;
1994                         goto out;
1995                 }
1996
1997                 for (i = 0; i < wr->num_sge; ++i) {
1998                         ((struct mthca_data_seg *) wqe)->byte_count =
1999                                 cpu_to_be32(wr->sg_list[i].length);
2000                         ((struct mthca_data_seg *) wqe)->lkey =
2001                                 cpu_to_be32(wr->sg_list[i].lkey);
2002                         ((struct mthca_data_seg *) wqe)->addr =
2003                                 cpu_to_be64(wr->sg_list[i].addr);
2004                         wqe += sizeof (struct mthca_data_seg);
2005                 }
2006
2007                 if (i < qp->rq.max_gs) {
2008                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2009                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2010                         ((struct mthca_data_seg *) wqe)->addr = 0;
2011                 }
2012
2013                 qp->wrid[ind] = wr->wr_id;
2014
2015                 ++ind;
2016                 if (unlikely(ind >= qp->rq.max))
2017                         ind -= qp->rq.max;
2018         }
2019 out:
2020         if (likely(nreq)) {
2021                 qp->rq.head += nreq;
2022
2023                 /*
2024                  * Make sure that descriptors are written before
2025                  * doorbell record.
2026                  */
2027                 wmb();
2028                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2029         }
2030
2031         spin_unlock_irqrestore(&qp->rq.lock, flags);
2032         return err;
2033 }
2034
2035 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2036                        int index, int *dbd, __be32 *new_wqe)
2037 {
2038         struct mthca_next_seg *next;
2039
2040         /*
2041          * For SRQs, all WQEs generate a CQE, so we're always at the
2042          * end of the doorbell chain.
2043          */
2044         if (qp->ibqp.srq) {
2045                 *new_wqe = 0;
2046                 return 0;
2047         }
2048
2049         if (is_send)
2050                 next = get_send_wqe(qp, index);
2051         else
2052                 next = get_recv_wqe(qp, index);
2053
2054         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2055         if (next->ee_nds & cpu_to_be32(0x3f))
2056                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2057                         (next->ee_nds & cpu_to_be32(0x3f));
2058         else
2059                 *new_wqe = 0;
2060
2061         return 0;
2062 }
2063
2064 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2065 {
2066         int err;
2067         u8 status;
2068         int i;
2069
2070         spin_lock_init(&dev->qp_table.lock);
2071
2072         /*
2073          * We reserve 2 extra QPs per port for the special QPs.  The
2074          * special QP for port 1 has to be even, so round up.
2075          */
2076         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2077         err = mthca_alloc_init(&dev->qp_table.alloc,
2078                                dev->limits.num_qps,
2079                                (1 << 24) - 1,
2080                                dev->qp_table.sqp_start +
2081                                MTHCA_MAX_PORTS * 2);
2082         if (err)
2083                 return err;
2084
2085         err = mthca_array_init(&dev->qp_table.qp,
2086                                dev->limits.num_qps);
2087         if (err) {
2088                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2089                 return err;
2090         }
2091
2092         for (i = 0; i < 2; ++i) {
2093                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2094                                             dev->qp_table.sqp_start + i * 2,
2095                                             &status);
2096                 if (err)
2097                         goto err_out;
2098                 if (status) {
2099                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2100                                    "status %02x, aborting.\n",
2101                                    status);
2102                         err = -EINVAL;
2103                         goto err_out;
2104                 }
2105         }
2106         return 0;
2107
2108  err_out:
2109         for (i = 0; i < 2; ++i)
2110                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2111
2112         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2113         mthca_alloc_cleanup(&dev->qp_table.alloc);
2114
2115         return err;
2116 }
2117
2118 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2119 {
2120         int i;
2121         u8 status;
2122
2123         for (i = 0; i < 2; ++i)
2124                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2125
2126         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2127         mthca_alloc_cleanup(&dev->qp_table.alloc);
2128 }