2 * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
39 #include <linux/tcp.h>
40 #include <linux/if_vlan.h>
41 #include <linux/inet_lro.h>
42 #include <linux/slab.h>
46 static unsigned int nes_lro_max_aggr = NES_LRO_MAX_AGGR;
47 module_param(nes_lro_max_aggr, uint, 0444);
48 MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation");
50 static int wide_ppm_offset;
51 module_param(wide_ppm_offset, int, 0644);
52 MODULE_PARM_DESC(wide_ppm_offset, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
54 static u32 crit_err_count;
55 u32 int_mod_timer_init;
56 u32 int_mod_cq_depth_256;
57 u32 int_mod_cq_depth_128;
58 u32 int_mod_cq_depth_32;
59 u32 int_mod_cq_depth_24;
60 u32 int_mod_cq_depth_16;
61 u32 int_mod_cq_depth_4;
62 u32 int_mod_cq_depth_1;
63 static const u8 nes_max_critical_error_count = 100;
66 static void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq);
67 static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count);
68 static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
69 struct nes_adapter *nesadapter, u8 OneG_Mode);
70 static void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
71 static void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq);
72 static void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq);
73 static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
74 struct nes_hw_aeqe *aeqe);
75 static void process_critical_error(struct nes_device *nesdev);
76 static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number);
77 static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode);
78 static void nes_terminate_timeout(unsigned long context);
79 static void nes_terminate_start_timer(struct nes_qp *nesqp);
81 #ifdef CONFIG_INFINIBAND_NES_DEBUG
82 static unsigned char *nes_iwarp_state_str[] = {
93 static unsigned char *nes_tcp_state_str[] = {
113 static inline void print_ip(struct nes_cm_node *cm_node)
115 unsigned char *rem_addr;
117 rem_addr = (unsigned char *)&cm_node->rem_addr;
118 printk(KERN_ERR PFX "Remote IP addr: %pI4\n", rem_addr);
123 * nes_nic_init_timer_defaults
125 void nes_nic_init_timer_defaults(struct nes_device *nesdev, u8 jumbomode)
128 struct nes_adapter *nesadapter = nesdev->nesadapter;
129 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
131 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
133 shared_timer->timer_in_use_min = NES_NIC_FAST_TIMER_LOW;
134 shared_timer->timer_in_use_max = NES_NIC_FAST_TIMER_HIGH;
136 shared_timer->threshold_low = DEFAULT_JUMBO_NES_QL_LOW;
137 shared_timer->threshold_target = DEFAULT_JUMBO_NES_QL_TARGET;
138 shared_timer->threshold_high = DEFAULT_JUMBO_NES_QL_HIGH;
140 shared_timer->threshold_low = DEFAULT_NES_QL_LOW;
141 shared_timer->threshold_target = DEFAULT_NES_QL_TARGET;
142 shared_timer->threshold_high = DEFAULT_NES_QL_HIGH;
145 /* todo use netdev->mtu to set thresholds */
146 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
153 static void nes_nic_init_timer(struct nes_device *nesdev)
156 struct nes_adapter *nesadapter = nesdev->nesadapter;
157 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
159 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
161 if (shared_timer->timer_in_use_old == 0) {
162 nesdev->deepcq_count = 0;
163 shared_timer->timer_direction_upward = 0;
164 shared_timer->timer_direction_downward = 0;
165 shared_timer->timer_in_use = NES_NIC_FAST_TIMER;
166 shared_timer->timer_in_use_old = 0;
169 if (shared_timer->timer_in_use != shared_timer->timer_in_use_old) {
170 shared_timer->timer_in_use_old = shared_timer->timer_in_use;
171 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL,
172 0x80000000 | ((u32)(shared_timer->timer_in_use*8)));
174 /* todo use netdev->mtu to set thresholds */
175 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
182 static void nes_nic_tune_timer(struct nes_device *nesdev)
185 struct nes_adapter *nesadapter = nesdev->nesadapter;
186 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
187 u16 cq_count = nesdev->currcq_count;
189 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
191 if (shared_timer->cq_count_old <= cq_count)
192 shared_timer->cq_direction_downward = 0;
194 shared_timer->cq_direction_downward++;
195 shared_timer->cq_count_old = cq_count;
196 if (shared_timer->cq_direction_downward > NES_NIC_CQ_DOWNWARD_TREND) {
197 if (cq_count <= shared_timer->threshold_low &&
198 shared_timer->threshold_low > 4) {
199 shared_timer->threshold_low = shared_timer->threshold_low/2;
200 shared_timer->cq_direction_downward=0;
201 nesdev->currcq_count = 0;
202 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
208 nesdev->deepcq_count += cq_count;
209 if (cq_count <= shared_timer->threshold_low) { /* increase timer gently */
210 shared_timer->timer_direction_upward++;
211 shared_timer->timer_direction_downward = 0;
212 } else if (cq_count <= shared_timer->threshold_target) { /* balanced */
213 shared_timer->timer_direction_upward = 0;
214 shared_timer->timer_direction_downward = 0;
215 } else if (cq_count <= shared_timer->threshold_high) { /* decrease timer gently */
216 shared_timer->timer_direction_downward++;
217 shared_timer->timer_direction_upward = 0;
218 } else if (cq_count <= (shared_timer->threshold_high) * 2) {
219 shared_timer->timer_in_use -= 2;
220 shared_timer->timer_direction_upward = 0;
221 shared_timer->timer_direction_downward++;
223 shared_timer->timer_in_use -= 4;
224 shared_timer->timer_direction_upward = 0;
225 shared_timer->timer_direction_downward++;
228 if (shared_timer->timer_direction_upward > 3 ) { /* using history */
229 shared_timer->timer_in_use += 3;
230 shared_timer->timer_direction_upward = 0;
231 shared_timer->timer_direction_downward = 0;
233 if (shared_timer->timer_direction_downward > 5) { /* using history */
234 shared_timer->timer_in_use -= 4 ;
235 shared_timer->timer_direction_downward = 0;
236 shared_timer->timer_direction_upward = 0;
240 /* boundary checking */
241 if (shared_timer->timer_in_use > shared_timer->threshold_high)
242 shared_timer->timer_in_use = shared_timer->threshold_high;
243 else if (shared_timer->timer_in_use < shared_timer->threshold_low)
244 shared_timer->timer_in_use = shared_timer->threshold_low;
246 nesdev->currcq_count = 0;
248 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
253 * nes_init_adapter - initialize adapter
255 struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
256 struct nes_adapter *nesadapter = NULL;
257 unsigned long num_pds;
276 /* search the list of existing adapters */
277 list_for_each_entry(nesadapter, &nes_adapter_list, list) {
278 nes_debug(NES_DBG_INIT, "Searching Adapter list for PCI devfn = 0x%X,"
279 " adapter PCI slot/bus = %u/%u, pci devices PCI slot/bus = %u/%u, .\n",
280 nesdev->pcidev->devfn,
281 PCI_SLOT(nesadapter->devfn),
282 nesadapter->bus_number,
283 PCI_SLOT(nesdev->pcidev->devfn),
284 nesdev->pcidev->bus->number );
285 if ((PCI_SLOT(nesadapter->devfn) == PCI_SLOT(nesdev->pcidev->devfn)) &&
286 (nesadapter->bus_number == nesdev->pcidev->bus->number)) {
287 nesadapter->ref_count++;
292 /* no adapter found */
293 num_pds = pci_resource_len(nesdev->pcidev, BAR_1) >> PAGE_SHIFT;
294 if ((hw_rev != NE020_REV) && (hw_rev != NE020_REV1)) {
295 nes_debug(NES_DBG_INIT, "NE020 driver detected unknown hardware revision 0x%x\n",
300 nes_debug(NES_DBG_INIT, "Determine Soft Reset, QP_control=0x%x, CPU0=0x%x, CPU1=0x%x, CPU2=0x%x\n",
301 nes_read_indexed(nesdev, NES_IDX_QP_CONTROL + PCI_FUNC(nesdev->pcidev->devfn) * 8),
302 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS),
303 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 4),
304 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 8));
306 nes_debug(NES_DBG_INIT, "Reset and init NE020\n");
309 if ((port_count = nes_reset_adapter_ne020(nesdev, &OneG_Mode)) == 0)
312 max_qp = nes_read_indexed(nesdev, NES_IDX_QP_CTX_SIZE);
313 nes_debug(NES_DBG_INIT, "QP_CTX_SIZE=%u\n", max_qp);
315 u32temp = nes_read_indexed(nesdev, NES_IDX_QUAD_HASH_TABLE_SIZE);
316 if (max_qp > ((u32)1 << (u32temp & 0x001f))) {
317 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to hash table size = 0x%08X\n",
319 max_qp = (u32)1 << (u32temp & 0x001f);
322 hte_index_mask = ((u32)1 << ((u32temp & 0x001f)+1))-1;
323 nes_debug(NES_DBG_INIT, "Max QP = %u, hte_index_mask = 0x%08X.\n",
324 max_qp, hte_index_mask);
326 u32temp = nes_read_indexed(nesdev, NES_IDX_IRRQ_COUNT);
328 max_irrq = 1 << (u32temp & 0x001f);
330 if (max_qp > max_irrq) {
332 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to Available Q1s.\n",
336 /* there should be no reason to allocate more pds than qps */
337 if (num_pds > max_qp)
340 u32temp = nes_read_indexed(nesdev, NES_IDX_MRT_SIZE);
341 max_mr = (u32)8192 << (u32temp & 0x7);
343 u32temp = nes_read_indexed(nesdev, NES_IDX_PBL_REGION_SIZE);
344 max_256pbl = (u32)1 << (u32temp & 0x0000001f);
345 max_4kpbl = (u32)1 << ((u32temp >> 16) & 0x0000001f);
346 max_cq = nes_read_indexed(nesdev, NES_IDX_CQ_CTX_SIZE);
348 u32temp = nes_read_indexed(nesdev, NES_IDX_ARP_CACHE_SIZE);
349 arp_table_size = 1 << u32temp;
351 adapter_size = (sizeof(struct nes_adapter) +
352 (sizeof(unsigned long)-1)) & (~(sizeof(unsigned long)-1));
353 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
354 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
355 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
356 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
357 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
358 adapter_size += sizeof(struct nes_qp **) * max_qp;
360 /* allocate a new adapter struct */
361 nesadapter = kzalloc(adapter_size, GFP_KERNEL);
362 if (nesadapter == NULL) {
366 nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
367 nesadapter, (u32)sizeof(struct nes_adapter), adapter_size);
369 if (nes_read_eeprom_values(nesdev, nesadapter)) {
370 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
375 nesadapter->vendor_id = (((u32) nesadapter->mac_addr_high) << 8) |
376 (nesadapter->mac_addr_low >> 24);
378 pci_bus_read_config_word(nesdev->pcidev->bus, nesdev->pcidev->devfn,
379 PCI_DEVICE_ID, &device_id);
380 nesadapter->vendor_part_id = device_id;
382 if (nes_init_serdes(nesdev, hw_rev, port_count, nesadapter,
387 nes_init_csr_ne020(nesdev, hw_rev, port_count);
389 memset(nesadapter->pft_mcast_map, 255,
390 sizeof nesadapter->pft_mcast_map);
392 /* populate the new nesadapter */
393 nesadapter->devfn = nesdev->pcidev->devfn;
394 nesadapter->bus_number = nesdev->pcidev->bus->number;
395 nesadapter->ref_count = 1;
396 nesadapter->timer_int_req = 0xffff0000;
397 nesadapter->OneG_Mode = OneG_Mode;
398 nesadapter->doorbell_start = nesdev->doorbell_region;
400 /* nesadapter->tick_delta = clk_divisor; */
401 nesadapter->hw_rev = hw_rev;
402 nesadapter->port_count = port_count;
404 nesadapter->max_qp = max_qp;
405 nesadapter->hte_index_mask = hte_index_mask;
406 nesadapter->max_irrq = max_irrq;
407 nesadapter->max_mr = max_mr;
408 nesadapter->max_256pbl = max_256pbl - 1;
409 nesadapter->max_4kpbl = max_4kpbl - 1;
410 nesadapter->max_cq = max_cq;
411 nesadapter->free_256pbl = max_256pbl - 1;
412 nesadapter->free_4kpbl = max_4kpbl - 1;
413 nesadapter->max_pd = num_pds;
414 nesadapter->arp_table_size = arp_table_size;
416 nesadapter->et_pkt_rate_low = NES_TIMER_ENABLE_LIMIT;
417 if (nes_drv_opt & NES_DRV_OPT_DISABLE_INT_MOD) {
418 nesadapter->et_use_adaptive_rx_coalesce = 0;
419 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT;
420 nesadapter->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
422 nesadapter->et_use_adaptive_rx_coalesce = 1;
423 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT_DYNAMIC;
424 nesadapter->et_rx_coalesce_usecs_irq = 0;
425 printk(PFX "%s: Using Adaptive Interrupt Moderation\n", __func__);
427 /* Setup and enable the periodic timer */
428 if (nesadapter->et_rx_coalesce_usecs_irq)
429 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x80000000 |
430 ((u32)(nesadapter->et_rx_coalesce_usecs_irq * 8)));
432 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x00000000);
434 nesadapter->base_pd = 1;
436 nesadapter->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
437 IB_DEVICE_MEM_WINDOW |
438 IB_DEVICE_MEM_MGT_EXTENSIONS;
440 nesadapter->allocated_qps = (unsigned long *)&(((unsigned char *)nesadapter)
441 [(sizeof(struct nes_adapter)+(sizeof(unsigned long)-1))&(~(sizeof(unsigned long)-1))]);
442 nesadapter->allocated_cqs = &nesadapter->allocated_qps[BITS_TO_LONGS(max_qp)];
443 nesadapter->allocated_mrs = &nesadapter->allocated_cqs[BITS_TO_LONGS(max_cq)];
444 nesadapter->allocated_pds = &nesadapter->allocated_mrs[BITS_TO_LONGS(max_mr)];
445 nesadapter->allocated_arps = &nesadapter->allocated_pds[BITS_TO_LONGS(num_pds)];
446 nesadapter->qp_table = (struct nes_qp **)(&nesadapter->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
449 /* mark the usual suspect QPs, MR and CQs as in use */
450 for (u32temp = 0; u32temp < NES_FIRST_QPN; u32temp++) {
451 set_bit(u32temp, nesadapter->allocated_qps);
452 set_bit(u32temp, nesadapter->allocated_cqs);
454 set_bit(0, nesadapter->allocated_mrs);
456 for (u32temp = 0; u32temp < 20; u32temp++)
457 set_bit(u32temp, nesadapter->allocated_pds);
458 u32temp = nes_read_indexed(nesdev, NES_IDX_QP_MAX_CFG_SIZES);
460 max_rq_wrs = ((u32temp >> 8) & 3);
461 switch (max_rq_wrs) {
476 max_sq_wrs = (u32temp & 3);
477 switch (max_sq_wrs) {
491 nesadapter->max_qp_wr = min(max_rq_wrs, max_sq_wrs);
492 nesadapter->max_irrq_wr = (u32temp >> 16) & 3;
494 nesadapter->max_sge = 4;
495 nesadapter->max_cqe = 32766;
497 if (nes_read_eeprom_values(nesdev, nesadapter)) {
498 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
503 u32temp = nes_read_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG);
504 nes_write_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG,
505 (u32temp & 0xff000000) | (nesadapter->tcp_timer_core_clk_divisor & 0x00ffffff));
507 /* setup port configuration */
508 if (nesadapter->port_count == 1) {
509 nesadapter->log_port = 0x00000000;
510 if (nes_drv_opt & NES_DRV_OPT_DUAL_LOGICAL_PORT)
511 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000002);
513 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
515 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
516 nesadapter->log_port = 0x000000D8;
518 if (nesadapter->port_count == 2)
519 nesadapter->log_port = 0x00000044;
521 nesadapter->log_port = 0x000000e4;
523 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
526 nes_write_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT,
527 nesadapter->log_port);
528 nes_debug(NES_DBG_INIT, "Probe time, LOG2PHY=%u\n",
529 nes_read_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT));
531 spin_lock_init(&nesadapter->resource_lock);
532 spin_lock_init(&nesadapter->phy_lock);
533 spin_lock_init(&nesadapter->pbl_lock);
534 spin_lock_init(&nesadapter->periodic_timer_lock);
536 INIT_LIST_HEAD(&nesadapter->nesvnic_list[0]);
537 INIT_LIST_HEAD(&nesadapter->nesvnic_list[1]);
538 INIT_LIST_HEAD(&nesadapter->nesvnic_list[2]);
539 INIT_LIST_HEAD(&nesadapter->nesvnic_list[3]);
541 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
542 u32 pcs_control_status0, pcs_control_status1;
550 pcs_control_status0 = nes_read_indexed(nesdev,
551 NES_IDX_PHY_PCS_CONTROL_STATUS0);
552 pcs_control_status1 = nes_read_indexed(nesdev,
553 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
555 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
556 pcs_control_status0 = nes_read_indexed(nesdev,
557 NES_IDX_PHY_PCS_CONTROL_STATUS0);
558 pcs_control_status1 = nes_read_indexed(nesdev,
559 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
560 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
561 || (0x0F000100 == (pcs_control_status1 & 0x0F000100)))
566 spin_lock_irqsave(&nesadapter->phy_lock, flags);
567 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
569 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
570 reset_value |= 0x0000003d;
571 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
573 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
574 & 0x00000040) != 0x00000040) && (j++ < 5000));
575 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
577 pcs_control_status0 = nes_read_indexed(nesdev,
578 NES_IDX_PHY_PCS_CONTROL_STATUS0);
579 pcs_control_status1 = nes_read_indexed(nesdev,
580 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
582 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
583 pcs_control_status0 = nes_read_indexed(nesdev,
584 NES_IDX_PHY_PCS_CONTROL_STATUS0);
585 pcs_control_status1 = nes_read_indexed(nesdev,
586 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
587 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
588 || (0x0F000100 == (pcs_control_status1 & 0x0F000100))) {
589 if (++ext_cnt > int_cnt) {
590 spin_lock_irqsave(&nesadapter->phy_lock, flags);
591 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1,
594 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
595 reset_value |= 0x0000003d;
596 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
598 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
599 & 0x00000040) != 0x00000040) && (j++ < 5000));
600 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
609 if (nesadapter->hw_rev == NE020_REV) {
610 init_timer(&nesadapter->mh_timer);
611 nesadapter->mh_timer.function = nes_mh_fix;
612 nesadapter->mh_timer.expires = jiffies + (HZ/5); /* 1 second */
613 nesadapter->mh_timer.data = (unsigned long)nesdev;
614 add_timer(&nesadapter->mh_timer);
616 nes_write32(nesdev->regs+NES_INTF_INT_STAT, 0x0f000000);
619 init_timer(&nesadapter->lc_timer);
620 nesadapter->lc_timer.function = nes_clc;
621 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
622 nesadapter->lc_timer.data = (unsigned long)nesdev;
623 add_timer(&nesadapter->lc_timer);
625 list_add_tail(&nesadapter->list, &nes_adapter_list);
627 for (func_index = 0; func_index < 8; func_index++) {
628 pci_bus_read_config_word(nesdev->pcidev->bus,
629 PCI_DEVFN(PCI_SLOT(nesdev->pcidev->devfn),
630 func_index), 0, &vendor_id);
631 if (vendor_id == 0xffff)
634 nes_debug(NES_DBG_INIT, "%s %d functions found for %s.\n", __func__,
635 func_index, pci_name(nesdev->pcidev));
636 nesadapter->adapter_fcn_count = func_index;
643 * nes_reset_adapter_ne020
645 static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode)
651 u32temp = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
652 port_count = ((u32temp & 0x00000300) >> 8) + 1;
653 /* TODO: assuming that both SERDES are set the same for now */
654 *OneG_Mode = (u32temp & 0x00003c00) ? 0 : 1;
655 nes_debug(NES_DBG_INIT, "Initial Software Reset = 0x%08X, port_count=%u\n",
656 u32temp, port_count);
658 nes_debug(NES_DBG_INIT, "Running in 1G mode.\n");
659 u32temp &= 0xff00ffc0;
660 switch (port_count) {
662 u32temp |= 0x00ee0000;
665 u32temp |= 0x00cc0000;
668 u32temp |= 0x00000000;
675 /* check and do full reset if needed */
676 if (nes_read_indexed(nesdev, NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8))) {
677 nes_debug(NES_DBG_INIT, "Issuing Full Soft reset = 0x%08X\n", u32temp | 0xd);
678 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
681 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
684 nes_debug(NES_DBG_INIT, "Did not see full soft reset done.\n");
689 while ((nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS) != 0x80) && i++ < 10000)
692 printk(KERN_ERR PFX "Internal CPU not ready, status = %02X\n",
693 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS));
699 switch (port_count) {
701 u32temp |= 0x00ee0010;
704 u32temp |= 0x00cc0030;
707 u32temp |= 0x00000030;
711 nes_debug(NES_DBG_INIT, "Issuing Port Soft reset = 0x%08X\n", u32temp | 0xd);
712 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
715 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
718 nes_debug(NES_DBG_INIT, "Did not see port soft reset done.\n");
724 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
725 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
728 nes_debug(NES_DBG_INIT, "Serdes 0 not ready, status=%x\n", u32temp);
733 if (port_count > 1) {
735 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
736 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
739 nes_debug(NES_DBG_INIT, "Serdes 1 not ready, status=%x\n", u32temp);
751 static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
752 struct nes_adapter *nesadapter, u8 OneG_Mode)
758 if (hw_rev != NE020_REV) {
760 switch (nesadapter->phy_type[0]) {
761 case NES_PHY_TYPE_CX4:
763 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA);
765 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
767 case NES_PHY_TYPE_KR:
768 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
769 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
771 case NES_PHY_TYPE_PUMA_1G:
772 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
773 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
775 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds);
778 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
783 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
789 if (!(OneG_Mode && (nesadapter->phy_type[1] != NES_PHY_TYPE_PUMA_1G)))
790 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
792 switch (nesadapter->phy_type[1]) {
793 case NES_PHY_TYPE_ARGUS:
794 case NES_PHY_TYPE_SFP_D:
795 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
796 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
798 case NES_PHY_TYPE_CX4:
800 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
802 case NES_PHY_TYPE_KR:
803 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
805 case NES_PHY_TYPE_PUMA_1G:
806 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
808 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
811 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
812 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
814 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
818 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
820 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
821 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
824 nes_debug(NES_DBG_PHY, "Init: serdes 0 not ready, status=%x\n", u32temp);
827 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
828 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
829 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
830 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
831 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
832 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
834 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
836 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
838 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
839 if (port_count > 1) {
841 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x00000048);
843 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
844 & 0x0000000f)) != 0x0000000f) && (i++ < 5000))
847 printk("%s: Init: serdes 1 not ready, status=%x\n", __func__, u32temp);
850 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x000bdef7);
851 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE1, 0x9ce73000);
852 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE1, 0x0ff00000);
853 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET1, 0x00000000);
854 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS1, 0x00000000);
855 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1, 0x00000000);
856 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL1, 0xf0002222);
857 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000ff);
866 * Initialize registers for ne020 hardware
868 static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
872 nes_debug(NES_DBG_INIT, "port_count=%d\n", port_count);
874 nes_write_indexed(nesdev, 0x000001E4, 0x00000007);
875 /* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
876 nes_write_indexed(nesdev, 0x000001E8, 0x00020874);
877 nes_write_indexed(nesdev, 0x000001D8, 0x00048002);
878 /* nes_write_indexed(nesdev, 0x000001D8, 0x0004B002); */
879 nes_write_indexed(nesdev, 0x000001FC, 0x00050005);
880 nes_write_indexed(nesdev, 0x00000600, 0x55555555);
881 nes_write_indexed(nesdev, 0x00000604, 0x55555555);
883 /* TODO: move these MAC register settings to NIC bringup */
884 nes_write_indexed(nesdev, 0x00002000, 0x00000001);
885 nes_write_indexed(nesdev, 0x00002004, 0x00000001);
886 nes_write_indexed(nesdev, 0x00002008, 0x0000FFFF);
887 nes_write_indexed(nesdev, 0x0000200C, 0x00000001);
888 nes_write_indexed(nesdev, 0x00002010, 0x000003c1);
889 nes_write_indexed(nesdev, 0x0000201C, 0x75345678);
890 if (port_count > 1) {
891 nes_write_indexed(nesdev, 0x00002200, 0x00000001);
892 nes_write_indexed(nesdev, 0x00002204, 0x00000001);
893 nes_write_indexed(nesdev, 0x00002208, 0x0000FFFF);
894 nes_write_indexed(nesdev, 0x0000220C, 0x00000001);
895 nes_write_indexed(nesdev, 0x00002210, 0x000003c1);
896 nes_write_indexed(nesdev, 0x0000221C, 0x75345678);
897 nes_write_indexed(nesdev, 0x00000908, 0x20000001);
899 if (port_count > 2) {
900 nes_write_indexed(nesdev, 0x00002400, 0x00000001);
901 nes_write_indexed(nesdev, 0x00002404, 0x00000001);
902 nes_write_indexed(nesdev, 0x00002408, 0x0000FFFF);
903 nes_write_indexed(nesdev, 0x0000240C, 0x00000001);
904 nes_write_indexed(nesdev, 0x00002410, 0x000003c1);
905 nes_write_indexed(nesdev, 0x0000241C, 0x75345678);
906 nes_write_indexed(nesdev, 0x00000910, 0x20000001);
908 nes_write_indexed(nesdev, 0x00002600, 0x00000001);
909 nes_write_indexed(nesdev, 0x00002604, 0x00000001);
910 nes_write_indexed(nesdev, 0x00002608, 0x0000FFFF);
911 nes_write_indexed(nesdev, 0x0000260C, 0x00000001);
912 nes_write_indexed(nesdev, 0x00002610, 0x000003c1);
913 nes_write_indexed(nesdev, 0x0000261C, 0x75345678);
914 nes_write_indexed(nesdev, 0x00000918, 0x20000001);
917 nes_write_indexed(nesdev, 0x00005000, 0x00018000);
918 /* nes_write_indexed(nesdev, 0x00005000, 0x00010000); */
919 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG1, (wqm_quanta << 1) |
921 nes_write_indexed(nesdev, 0x00005008, 0x1F1F1F1F);
922 nes_write_indexed(nesdev, 0x00005010, 0x1F1F1F1F);
923 nes_write_indexed(nesdev, 0x00005018, 0x1F1F1F1F);
924 nes_write_indexed(nesdev, 0x00005020, 0x1F1F1F1F);
925 nes_write_indexed(nesdev, 0x00006090, 0xFFFFFFFF);
927 /* TODO: move this to code, get from EEPROM */
928 nes_write_indexed(nesdev, 0x00000900, 0x20000001);
929 nes_write_indexed(nesdev, 0x000060C0, 0x0000028e);
930 nes_write_indexed(nesdev, 0x000060C8, 0x00000020);
932 nes_write_indexed(nesdev, 0x000001EC, 0x7b2625a0);
933 /* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
935 if (hw_rev != NE020_REV) {
936 u32temp = nes_read_indexed(nesdev, 0x000008e8);
937 u32temp |= 0x80000000;
938 nes_write_indexed(nesdev, 0x000008e8, u32temp);
939 u32temp = nes_read_indexed(nesdev, 0x000021f8);
940 u32temp &= 0x7fffffff;
941 u32temp |= 0x7fff0010;
942 nes_write_indexed(nesdev, 0x000021f8, u32temp);
943 if (port_count > 1) {
944 u32temp = nes_read_indexed(nesdev, 0x000023f8);
945 u32temp &= 0x7fffffff;
946 u32temp |= 0x7fff0010;
947 nes_write_indexed(nesdev, 0x000023f8, u32temp);
954 * nes_destroy_adapter - destroy the adapter structure
956 void nes_destroy_adapter(struct nes_adapter *nesadapter)
958 struct nes_adapter *tmp_adapter;
960 list_for_each_entry(tmp_adapter, &nes_adapter_list, list) {
961 nes_debug(NES_DBG_SHUTDOWN, "Nes Adapter list entry = 0x%p.\n",
965 nesadapter->ref_count--;
966 if (!nesadapter->ref_count) {
967 if (nesadapter->hw_rev == NE020_REV) {
968 del_timer(&nesadapter->mh_timer);
970 del_timer(&nesadapter->lc_timer);
972 list_del(&nesadapter->list);
981 int nes_init_cqp(struct nes_device *nesdev)
983 struct nes_adapter *nesadapter = nesdev->nesadapter;
984 struct nes_hw_cqp_qp_context *cqp_qp_context;
985 struct nes_hw_cqp_wqe *cqp_wqe;
986 struct nes_hw_ceq *ceq;
987 struct nes_hw_ceq *nic_ceq;
988 struct nes_hw_aeq *aeq;
996 /* allocate CQP memory */
997 /* Need to add max_cq to the aeq size once cq overflow checking is added back */
998 /* SQ is 512 byte aligned, others are 256 byte aligned */
999 nesdev->cqp_mem_size = 512 +
1000 (sizeof(struct nes_hw_cqp_wqe) * NES_CQP_SQ_SIZE) +
1001 (sizeof(struct nes_hw_cqe) * NES_CCQ_SIZE) +
1002 max(((u32)sizeof(struct nes_hw_ceqe) * NES_CCEQ_SIZE), (u32)256) +
1003 max(((u32)sizeof(struct nes_hw_ceqe) * NES_NIC_CEQ_SIZE), (u32)256) +
1004 (sizeof(struct nes_hw_aeqe) * nesadapter->max_qp) +
1005 sizeof(struct nes_hw_cqp_qp_context);
1007 nesdev->cqp_vbase = pci_alloc_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1008 &nesdev->cqp_pbase);
1009 if (!nesdev->cqp_vbase) {
1010 nes_debug(NES_DBG_INIT, "Unable to allocate memory for host descriptor rings\n");
1013 memset(nesdev->cqp_vbase, 0, nesdev->cqp_mem_size);
1015 /* Allocate a twice the number of CQP requests as the SQ size */
1016 nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) *
1017 2 * NES_CQP_SQ_SIZE, GFP_KERNEL);
1018 if (nesdev->nes_cqp_requests == NULL) {
1019 nes_debug(NES_DBG_INIT, "Unable to allocate memory CQP request entries.\n");
1020 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1021 nesdev->cqp.sq_pbase);
1025 nes_debug(NES_DBG_INIT, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
1026 nesdev->cqp_vbase, (unsigned long)nesdev->cqp_pbase, nesdev->cqp_mem_size);
1028 spin_lock_init(&nesdev->cqp.lock);
1029 init_waitqueue_head(&nesdev->cqp.waitq);
1031 /* Setup Various Structures */
1032 vmem = (void *)(((unsigned long)nesdev->cqp_vbase + (512 - 1)) &
1033 ~(unsigned long)(512 - 1));
1034 pmem = (dma_addr_t)(((unsigned long long)nesdev->cqp_pbase + (512 - 1)) &
1035 ~(unsigned long long)(512 - 1));
1037 nesdev->cqp.sq_vbase = vmem;
1038 nesdev->cqp.sq_pbase = pmem;
1039 nesdev->cqp.sq_size = NES_CQP_SQ_SIZE;
1040 nesdev->cqp.sq_head = 0;
1041 nesdev->cqp.sq_tail = 0;
1042 nesdev->cqp.qp_id = PCI_FUNC(nesdev->pcidev->devfn);
1044 vmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
1045 pmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
1047 nesdev->ccq.cq_vbase = vmem;
1048 nesdev->ccq.cq_pbase = pmem;
1049 nesdev->ccq.cq_size = NES_CCQ_SIZE;
1050 nesdev->ccq.cq_head = 0;
1051 nesdev->ccq.ce_handler = nes_cqp_ce_handler;
1052 nesdev->ccq.cq_number = PCI_FUNC(nesdev->pcidev->devfn);
1054 vmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
1055 pmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
1057 nesdev->ceq_index = PCI_FUNC(nesdev->pcidev->devfn);
1058 ceq = &nesadapter->ceq[nesdev->ceq_index];
1059 ceq->ceq_vbase = vmem;
1060 ceq->ceq_pbase = pmem;
1061 ceq->ceq_size = NES_CCEQ_SIZE;
1064 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
1065 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
1067 nesdev->nic_ceq_index = PCI_FUNC(nesdev->pcidev->devfn) + 8;
1068 nic_ceq = &nesadapter->ceq[nesdev->nic_ceq_index];
1069 nic_ceq->ceq_vbase = vmem;
1070 nic_ceq->ceq_pbase = pmem;
1071 nic_ceq->ceq_size = NES_NIC_CEQ_SIZE;
1072 nic_ceq->ceq_head = 0;
1074 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
1075 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
1077 aeq = &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)];
1078 aeq->aeq_vbase = vmem;
1079 aeq->aeq_pbase = pmem;
1080 aeq->aeq_size = nesadapter->max_qp;
1083 /* Setup QP Context */
1084 vmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
1085 pmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
1087 cqp_qp_context = vmem;
1088 cqp_qp_context->context_words[0] =
1089 cpu_to_le32((PCI_FUNC(nesdev->pcidev->devfn) << 12) + (2 << 10));
1090 cqp_qp_context->context_words[1] = 0;
1091 cqp_qp_context->context_words[2] = cpu_to_le32((u32)nesdev->cqp.sq_pbase);
1092 cqp_qp_context->context_words[3] = cpu_to_le32(((u64)nesdev->cqp.sq_pbase) >> 32);
1095 /* Write the address to Create CQP */
1096 if ((sizeof(dma_addr_t) > 4)) {
1097 nes_write_indexed(nesdev,
1098 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
1101 nes_write_indexed(nesdev,
1102 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8), 0);
1104 nes_write_indexed(nesdev,
1105 NES_IDX_CREATE_CQP_LOW + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
1108 INIT_LIST_HEAD(&nesdev->cqp_avail_reqs);
1109 INIT_LIST_HEAD(&nesdev->cqp_pending_reqs);
1111 for (count = 0; count < 2*NES_CQP_SQ_SIZE; count++) {
1112 init_waitqueue_head(&nesdev->nes_cqp_requests[count].waitq);
1113 list_add_tail(&nesdev->nes_cqp_requests[count].list, &nesdev->cqp_avail_reqs);
1116 /* Write Create CCQ WQE */
1117 cqp_head = nesdev->cqp.sq_head++;
1118 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1119 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1120 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1121 (NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1122 NES_CQP_CQ_CHK_OVERFLOW | ((u32)nesdev->ccq.cq_size << 16)));
1123 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1124 (nesdev->ccq.cq_number |
1125 ((u32)nesdev->ceq_index << 16)));
1126 u64temp = (u64)nesdev->ccq.cq_pbase;
1127 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1128 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1129 u64temp = (unsigned long)&nesdev->ccq;
1130 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] =
1131 cpu_to_le32((u32)(u64temp >> 1));
1132 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1133 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1134 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1136 /* Write Create CEQ WQE */
1137 cqp_head = nesdev->cqp.sq_head++;
1138 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1139 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1140 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1141 (NES_CQP_CREATE_CEQ + ((u32)nesdev->ceq_index << 8)));
1142 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, ceq->ceq_size);
1143 u64temp = (u64)ceq->ceq_pbase;
1144 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1146 /* Write Create AEQ WQE */
1147 cqp_head = nesdev->cqp.sq_head++;
1148 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1149 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1150 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1151 (NES_CQP_CREATE_AEQ + ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8)));
1152 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX, aeq->aeq_size);
1153 u64temp = (u64)aeq->aeq_pbase;
1154 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1156 /* Write Create NIC CEQ WQE */
1157 cqp_head = nesdev->cqp.sq_head++;
1158 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1159 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1160 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1161 (NES_CQP_CREATE_CEQ + ((u32)nesdev->nic_ceq_index << 8)));
1162 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, nic_ceq->ceq_size);
1163 u64temp = (u64)nic_ceq->ceq_pbase;
1164 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1166 /* Poll until CCQP done */
1169 if (count++ > 1000) {
1170 printk(KERN_ERR PFX "Error creating CQP\n");
1171 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1172 nesdev->cqp_vbase, nesdev->cqp_pbase);
1176 } while (!(nes_read_indexed(nesdev,
1177 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn) * 8)) & (1 << 8)));
1179 nes_debug(NES_DBG_INIT, "CQP Status = 0x%08X\n", nes_read_indexed(nesdev,
1180 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1182 u32temp = 0x04800000;
1183 nes_write32(nesdev->regs+NES_WQE_ALLOC, u32temp | nesdev->cqp.qp_id);
1185 /* wait for the CCQ, CEQ, and AEQ to get created */
1188 if (count++ > 1000) {
1189 printk(KERN_ERR PFX "Error creating CCQ, CEQ, and AEQ\n");
1190 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1191 nesdev->cqp_vbase, nesdev->cqp_pbase);
1195 } while (((nes_read_indexed(nesdev,
1196 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != (15<<8)));
1198 /* dump the QP status value */
1199 nes_debug(NES_DBG_INIT, "QP Status = 0x%08X\n", nes_read_indexed(nesdev,
1200 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1202 nesdev->cqp.sq_tail++;
1211 int nes_destroy_cqp(struct nes_device *nesdev)
1213 struct nes_hw_cqp_wqe *cqp_wqe;
1216 unsigned long flags;
1222 } while (!(nesdev->cqp.sq_head == nesdev->cqp.sq_tail));
1225 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_RESET |
1226 nesdev->ccq.cq_number);
1228 /* Disable device interrupts */
1229 nes_write32(nesdev->regs+NES_INT_MASK, 0x7fffffff);
1231 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1233 /* Destroy the AEQ */
1234 cqp_head = nesdev->cqp.sq_head++;
1235 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1236 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1237 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_AEQ |
1238 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8));
1239 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
1241 /* Destroy the NIC CEQ */
1242 cqp_head = nesdev->cqp.sq_head++;
1243 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1244 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1245 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1246 ((u32)nesdev->nic_ceq_index << 8));
1248 /* Destroy the CEQ */
1249 cqp_head = nesdev->cqp.sq_head++;
1250 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1251 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1252 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1253 (nesdev->ceq_index << 8));
1255 /* Destroy the CCQ */
1256 cqp_head = nesdev->cqp.sq_head++;
1257 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1258 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1259 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ);
1260 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->ccq.cq_number |
1261 ((u32)nesdev->ceq_index << 16));
1264 cqp_head = nesdev->cqp.sq_head++;
1265 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1266 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1267 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_QP |
1268 NES_CQP_QP_TYPE_CQP);
1269 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->cqp.qp_id);
1272 /* Ring doorbell (5 WQEs) */
1273 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x05800000 | nesdev->cqp.qp_id);
1275 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1277 /* wait for the CCQ, CEQ, and AEQ to get destroyed */
1280 if (count++ > 1000) {
1281 printk(KERN_ERR PFX "Function%d: Error destroying CCQ, CEQ, and AEQ\n",
1282 PCI_FUNC(nesdev->pcidev->devfn));
1286 } while (((nes_read_indexed(nesdev,
1287 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15 << 8)) != 0));
1289 /* dump the QP status value */
1290 nes_debug(NES_DBG_SHUTDOWN, "Function%d: QP Status = 0x%08X\n",
1291 PCI_FUNC(nesdev->pcidev->devfn),
1292 nes_read_indexed(nesdev,
1293 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1295 kfree(nesdev->nes_cqp_requests);
1297 /* Free the control structures */
1298 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1299 nesdev->cqp.sq_pbase);
1308 static int nes_init_1g_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index)
1314 nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
1315 nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
1318 nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
1322 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1323 if (counter++ > 100) {
1327 } while (phy_data & 0x8000);
1329 /* Setting no phy loopback */
1332 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
1333 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1334 nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
1335 nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
1337 /* Setting the interrupt mask */
1338 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1339 nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
1340 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1342 /* turning on flow control */
1343 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1344 nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
1345 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1347 /* Clear Half duplex */
1348 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1349 nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
1350 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1352 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1353 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
1362 static int nes_init_2025_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index)
1364 u32 temp_phy_data = 0;
1365 u32 temp_phy_data2 = 0;
1368 u32 mac_index = nesdev->mac_index;
1370 unsigned int first_attempt = 1;
1372 /* Check firmware heartbeat */
1373 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1374 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1376 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1377 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1379 if (temp_phy_data != temp_phy_data2) {
1380 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1381 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1382 if ((temp_phy_data & 0xff) > 0x20)
1384 printk(PFX "Reinitialize external PHY\n");
1387 /* no heartbeat, configure the PHY */
1388 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
1389 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
1390 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1391 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1394 case NES_PHY_TYPE_ARGUS:
1395 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1396 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1397 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1398 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1399 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1400 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1401 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1404 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1405 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1406 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1409 case NES_PHY_TYPE_SFP_D:
1410 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1411 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1412 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004);
1413 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038);
1414 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1415 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1416 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1419 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1420 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1421 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1424 case NES_PHY_TYPE_KR:
1425 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1426 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1427 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1428 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0010);
1429 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1430 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0080);
1431 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1434 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x000B);
1435 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x0003);
1436 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0004);
1438 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0022, 0x406D);
1439 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0023, 0x0020);
1443 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
1445 /* Bring PHY out of reset */
1446 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
1448 /* Check for heartbeat */
1451 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1452 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1454 if (counter++ > 150) {
1455 printk(PFX "No PHY heartbeat\n");
1459 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1460 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1461 } while ((temp_phy_data2 == temp_phy_data));
1463 /* wait for tracking */
1466 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1467 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1468 if (counter++ > 300) {
1469 if (((temp_phy_data & 0xff) == 0x0) && first_attempt) {
1472 /* reset AMCC PHY and try again */
1473 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0);
1474 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040);
1482 } while ((temp_phy_data & 0xff) < 0x30);
1484 /* setup signal integrity */
1485 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
1486 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
1487 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
1488 if (phy_type == NES_PHY_TYPE_KR) {
1489 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x000C);
1491 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
1492 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
1496 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200);
1498 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds);
1500 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds);
1503 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
1504 && (counter++ < 5000))
1514 int nes_init_phy(struct nes_device *nesdev)
1516 struct nes_adapter *nesadapter = nesdev->nesadapter;
1517 u32 mac_index = nesdev->mac_index;
1519 unsigned long flags;
1520 u8 phy_type = nesadapter->phy_type[mac_index];
1521 u8 phy_index = nesadapter->phy_index[mac_index];
1524 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1525 if (phy_type == NES_PHY_TYPE_1G) {
1526 /* setup 1G MDIO operation */
1527 tx_config &= 0xFFFFFFE3;
1530 /* setup 10G MDIO operation */
1531 tx_config &= 0xFFFFFFE3;
1534 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1536 spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags);
1539 case NES_PHY_TYPE_1G:
1540 ret = nes_init_1g_phy(nesdev, phy_type, phy_index);
1542 case NES_PHY_TYPE_ARGUS:
1543 case NES_PHY_TYPE_SFP_D:
1544 case NES_PHY_TYPE_KR:
1545 ret = nes_init_2025_phy(nesdev, phy_type, phy_index);
1549 spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
1556 * nes_replenish_nic_rq
1558 static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
1560 unsigned long flags;
1561 dma_addr_t bus_address;
1562 struct sk_buff *skb;
1563 struct nes_hw_nic_rq_wqe *nic_rqe;
1564 struct nes_hw_nic *nesnic;
1565 struct nes_device *nesdev;
1566 struct nes_rskb_cb *cb;
1567 u32 rx_wqes_posted = 0;
1569 nesnic = &nesvnic->nic;
1570 nesdev = nesvnic->nesdev;
1571 spin_lock_irqsave(&nesnic->rq_lock, flags);
1572 if (nesnic->replenishing_rq !=0) {
1573 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1574 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1575 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1576 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1577 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1578 add_timer(&nesvnic->rq_wqes_timer);
1580 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1583 nesnic->replenishing_rq = 1;
1584 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1586 skb = dev_alloc_skb(nesvnic->max_frame_size);
1588 skb->dev = nesvnic->netdev;
1590 bus_address = pci_map_single(nesdev->pcidev,
1591 skb->data, nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1592 cb = (struct nes_rskb_cb *)&skb->cb[0];
1593 cb->busaddr = bus_address;
1594 cb->maplen = nesvnic->max_frame_size;
1596 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_head];
1597 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] =
1598 cpu_to_le32(nesvnic->max_frame_size);
1599 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1600 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] =
1601 cpu_to_le32((u32)bus_address);
1602 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] =
1603 cpu_to_le32((u32)((u64)bus_address >> 32));
1604 nesnic->rx_skb[nesnic->rq_head] = skb;
1606 nesnic->rq_head &= nesnic->rq_size - 1;
1607 atomic_dec(&nesvnic->rx_skbs_needed);
1609 if (++rx_wqes_posted == 255) {
1610 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1614 spin_lock_irqsave(&nesnic->rq_lock, flags);
1615 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1616 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1617 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1618 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1619 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1620 add_timer(&nesvnic->rq_wqes_timer);
1622 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1625 } while (atomic_read(&nesvnic->rx_skbs_needed));
1628 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1629 nesnic->replenishing_rq = 0;
1634 * nes_rq_wqes_timeout
1636 static void nes_rq_wqes_timeout(unsigned long parm)
1638 struct nes_vnic *nesvnic = (struct nes_vnic *)parm;
1639 printk("%s: Timer fired.\n", __func__);
1640 atomic_set(&nesvnic->rx_skb_timer_running, 0);
1641 if (atomic_read(&nesvnic->rx_skbs_needed))
1642 nes_replenish_nic_rq(nesvnic);
1646 static int nes_lro_get_skb_hdr(struct sk_buff *skb, void **iphdr,
1647 void **tcph, u64 *hdr_flags, void *priv)
1649 unsigned int ip_len;
1651 skb_reset_network_header(skb);
1653 if (iph->protocol != IPPROTO_TCP)
1655 ip_len = ip_hdrlen(skb);
1656 skb_set_transport_header(skb, ip_len);
1657 *tcph = tcp_hdr(skb);
1659 *hdr_flags = LRO_IPV4 | LRO_TCP;
1668 int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
1670 struct nes_hw_cqp_wqe *cqp_wqe;
1671 struct nes_hw_nic_sq_wqe *nic_sqe;
1672 struct nes_hw_nic_qp_context *nic_context;
1673 struct sk_buff *skb;
1674 struct nes_hw_nic_rq_wqe *nic_rqe;
1675 struct nes_vnic *nesvnic = netdev_priv(netdev);
1676 unsigned long flags;
1684 struct nes_rskb_cb *cb;
1687 /* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
1688 nesvnic->nic_mem_size = 256 +
1689 (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag)) +
1690 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe)) +
1691 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe)) +
1692 (NES_NIC_WQ_SIZE * 2 * sizeof(struct nes_hw_nic_cqe)) +
1693 sizeof(struct nes_hw_nic_qp_context);
1695 nesvnic->nic_vbase = pci_alloc_consistent(nesdev->pcidev, nesvnic->nic_mem_size,
1696 &nesvnic->nic_pbase);
1697 if (!nesvnic->nic_vbase) {
1698 nes_debug(NES_DBG_INIT, "Unable to allocate memory for NIC host descriptor rings\n");
1701 memset(nesvnic->nic_vbase, 0, nesvnic->nic_mem_size);
1702 nes_debug(NES_DBG_INIT, "Allocated NIC QP structures at %p (phys = %016lX), size = %u.\n",
1703 nesvnic->nic_vbase, (unsigned long)nesvnic->nic_pbase, nesvnic->nic_mem_size);
1705 vmem = (void *)(((unsigned long)nesvnic->nic_vbase + (256 - 1)) &
1706 ~(unsigned long)(256 - 1));
1707 pmem = (dma_addr_t)(((unsigned long long)nesvnic->nic_pbase + (256 - 1)) &
1708 ~(unsigned long long)(256 - 1));
1710 /* Setup the first Fragment buffers */
1711 nesvnic->nic.first_frag_vbase = vmem;
1713 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1714 nesvnic->nic.frag_paddr[counter] = pmem;
1715 pmem += sizeof(struct nes_first_frag);
1719 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag));
1721 nesvnic->nic.sq_vbase = (void *)vmem;
1722 nesvnic->nic.sq_pbase = pmem;
1723 nesvnic->nic.sq_head = 0;
1724 nesvnic->nic.sq_tail = 0;
1725 nesvnic->nic.sq_size = NES_NIC_WQ_SIZE;
1726 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1727 nic_sqe = &nesvnic->nic.sq_vbase[counter];
1728 nic_sqe->wqe_words[NES_NIC_SQ_WQE_MISC_IDX] =
1729 cpu_to_le32(NES_NIC_SQ_WQE_DISABLE_CHKSUM |
1730 NES_NIC_SQ_WQE_COMPLETION);
1731 nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX] =
1732 cpu_to_le32((u32)NES_FIRST_FRAG_SIZE << 16);
1733 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX] =
1734 cpu_to_le32((u32)nesvnic->nic.frag_paddr[counter]);
1735 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX] =
1736 cpu_to_le32((u32)((u64)nesvnic->nic.frag_paddr[counter] >> 32));
1739 nesvnic->get_cqp_request = nes_get_cqp_request;
1740 nesvnic->post_cqp_request = nes_post_cqp_request;
1741 nesvnic->mcrq_mcast_filter = NULL;
1743 spin_lock_init(&nesvnic->nic.rq_lock);
1746 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1747 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1750 nesvnic->nic.rq_vbase = vmem;
1751 nesvnic->nic.rq_pbase = pmem;
1752 nesvnic->nic.rq_head = 0;
1753 nesvnic->nic.rq_tail = 0;
1754 nesvnic->nic.rq_size = NES_NIC_WQ_SIZE;
1757 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1758 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1760 if (nesdev->nesadapter->netdev_count > 2)
1761 nesvnic->mcrq_qp_id = nesvnic->nic_index + 32;
1763 nesvnic->mcrq_qp_id = nesvnic->nic.qp_id + 4;
1765 nesvnic->nic_cq.cq_vbase = vmem;
1766 nesvnic->nic_cq.cq_pbase = pmem;
1767 nesvnic->nic_cq.cq_head = 0;
1768 nesvnic->nic_cq.cq_size = NES_NIC_WQ_SIZE * 2;
1770 nesvnic->nic_cq.ce_handler = nes_nic_napi_ce_handler;
1772 /* Send CreateCQ request to CQP */
1773 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1774 cqp_head = nesdev->cqp.sq_head;
1776 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1777 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1779 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
1780 NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1781 ((u32)nesvnic->nic_cq.cq_size << 16));
1782 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(
1783 nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16));
1784 u64temp = (u64)nesvnic->nic_cq.cq_pbase;
1785 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1786 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1787 u64temp = (unsigned long)&nesvnic->nic_cq;
1788 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp >> 1));
1789 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1790 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1791 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1792 if (++cqp_head >= nesdev->cqp.sq_size)
1794 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1795 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1797 /* Send CreateQP request to CQP */
1798 nic_context = (void *)(&nesvnic->nic_cq.cq_vbase[nesvnic->nic_cq.cq_size]);
1799 nic_context->context_words[NES_NIC_CTX_MISC_IDX] =
1800 cpu_to_le32((u32)NES_NIC_CTX_SIZE |
1801 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 12));
1802 nes_debug(NES_DBG_INIT, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
1803 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE),
1804 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE));
1805 if (nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE) != 0) {
1806 nic_context->context_words[NES_NIC_CTX_MISC_IDX] |= cpu_to_le32(NES_NIC_BACK_STORE);
1809 u64temp = (u64)nesvnic->nic.sq_pbase;
1810 nic_context->context_words[NES_NIC_CTX_SQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
1811 nic_context->context_words[NES_NIC_CTX_SQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1812 u64temp = (u64)nesvnic->nic.rq_pbase;
1813 nic_context->context_words[NES_NIC_CTX_RQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
1814 nic_context->context_words[NES_NIC_CTX_RQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1816 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_QP |
1817 NES_CQP_QP_TYPE_NIC);
1818 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic.qp_id);
1819 u64temp = (u64)nesvnic->nic_cq.cq_pbase +
1820 (nesvnic->nic_cq.cq_size * sizeof(struct nes_hw_nic_cqe));
1821 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
1823 if (++cqp_head >= nesdev->cqp.sq_size)
1825 nesdev->cqp.sq_head = cqp_head;
1829 /* Ring doorbell (2 WQEs) */
1830 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
1832 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1833 nes_debug(NES_DBG_INIT, "Waiting for create NIC QP%u to complete.\n",
1834 nesvnic->nic.qp_id);
1836 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
1838 nes_debug(NES_DBG_INIT, "Create NIC QP%u completed, wait_event_timeout ret = %u.\n",
1839 nesvnic->nic.qp_id, ret);
1841 nes_debug(NES_DBG_INIT, "NIC QP%u create timeout expired\n", nesvnic->nic.qp_id);
1842 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
1843 nesvnic->nic_pbase);
1847 /* Populate the RQ */
1848 for (counter = 0; counter < (NES_NIC_WQ_SIZE - 1); counter++) {
1849 skb = dev_alloc_skb(nesvnic->max_frame_size);
1851 nes_debug(NES_DBG_INIT, "%s: out of memory for receive skb\n", netdev->name);
1853 nes_destroy_nic_qp(nesvnic);
1859 pmem = pci_map_single(nesdev->pcidev, skb->data,
1860 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1861 cb = (struct nes_rskb_cb *)&skb->cb[0];
1863 cb->maplen = nesvnic->max_frame_size;
1865 nic_rqe = &nesvnic->nic.rq_vbase[counter];
1866 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] = cpu_to_le32(nesvnic->max_frame_size);
1867 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1868 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] = cpu_to_le32((u32)pmem);
1869 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] = cpu_to_le32((u32)((u64)pmem >> 32));
1870 nesvnic->nic.rx_skb[counter] = skb;
1873 wqe_count = NES_NIC_WQ_SIZE - 1;
1874 nesvnic->nic.rq_head = wqe_count;
1877 counter = min(wqe_count, ((u32)255));
1878 wqe_count -= counter;
1879 nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter << 24) | nesvnic->nic.qp_id);
1880 } while (wqe_count);
1881 init_timer(&nesvnic->rq_wqes_timer);
1882 nesvnic->rq_wqes_timer.function = nes_rq_wqes_timeout;
1883 nesvnic->rq_wqes_timer.data = (unsigned long)nesvnic;
1884 nes_debug(NES_DBG_INIT, "NAPI support Enabled\n");
1885 if (nesdev->nesadapter->et_use_adaptive_rx_coalesce)
1887 nes_nic_init_timer(nesdev);
1888 if (netdev->mtu > 1500)
1890 nes_nic_init_timer_defaults(nesdev, jumbomode);
1892 if ((nesdev->nesadapter->allow_unaligned_fpdus) &&
1893 (nes_init_mgt_qp(nesdev, netdev, nesvnic))) {
1894 nes_debug(NES_DBG_INIT, "%s: Out of memory for pau nic\n", netdev->name);
1895 nes_destroy_nic_qp(nesvnic);
1899 nesvnic->lro_mgr.max_aggr = nes_lro_max_aggr;
1900 nesvnic->lro_mgr.max_desc = NES_MAX_LRO_DESCRIPTORS;
1901 nesvnic->lro_mgr.lro_arr = nesvnic->lro_desc;
1902 nesvnic->lro_mgr.get_skb_header = nes_lro_get_skb_hdr;
1903 nesvnic->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1904 nesvnic->lro_mgr.dev = netdev;
1905 nesvnic->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1906 nesvnic->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1912 * nes_destroy_nic_qp
1914 void nes_destroy_nic_qp(struct nes_vnic *nesvnic)
1917 dma_addr_t bus_address;
1918 struct nes_device *nesdev = nesvnic->nesdev;
1919 struct nes_hw_cqp_wqe *cqp_wqe;
1920 struct nes_hw_nic_sq_wqe *nic_sqe;
1921 __le16 *wqe_fragment_length;
1922 u16 wqe_fragment_index;
1925 unsigned long flags;
1926 struct sk_buff *rx_skb;
1927 struct nes_rskb_cb *cb;
1930 if (nesdev->nesadapter->allow_unaligned_fpdus)
1931 nes_destroy_mgt(nesvnic);
1933 /* clear wqe stall before destroying NIC QP */
1934 wqm_cfg0 = nes_read_indexed(nesdev, NES_IDX_WQM_CONFIG0);
1935 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0 & 0xFFFF7FFF);
1937 /* Free remaining NIC receive buffers */
1938 while (nesvnic->nic.rq_head != nesvnic->nic.rq_tail) {
1939 rx_skb = nesvnic->nic.rx_skb[nesvnic->nic.rq_tail];
1940 cb = (struct nes_rskb_cb *)&rx_skb->cb[0];
1941 pci_unmap_single(nesdev->pcidev, cb->busaddr, cb->maplen,
1942 PCI_DMA_FROMDEVICE);
1944 dev_kfree_skb(nesvnic->nic.rx_skb[nesvnic->nic.rq_tail++]);
1945 nesvnic->nic.rq_tail &= (nesvnic->nic.rq_size - 1);
1948 /* Free remaining NIC transmit buffers */
1949 while (nesvnic->nic.sq_head != nesvnic->nic.sq_tail) {
1950 nic_sqe = &nesvnic->nic.sq_vbase[nesvnic->nic.sq_tail];
1951 wqe_fragment_index = 1;
1952 wqe_fragment_length = (__le16 *)
1953 &nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
1954 /* bump past the vlan tag */
1955 wqe_fragment_length++;
1956 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
1957 u64temp = (u64)le32_to_cpu(
1958 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX+
1959 wqe_fragment_index*2]);
1960 u64temp += ((u64)le32_to_cpu(
1961 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
1962 + wqe_fragment_index*2]))<<32;
1963 bus_address = (dma_addr_t)u64temp;
1964 if (test_and_clear_bit(nesvnic->nic.sq_tail,
1965 nesvnic->nic.first_frag_overflow)) {
1966 pci_unmap_single(nesdev->pcidev,
1968 le16_to_cpu(wqe_fragment_length[
1969 wqe_fragment_index++]),
1972 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
1973 if (wqe_fragment_length[wqe_fragment_index]) {
1974 u64temp = le32_to_cpu(
1976 NES_NIC_SQ_WQE_FRAG0_LOW_IDX+
1977 wqe_fragment_index*2]);
1978 u64temp += ((u64)le32_to_cpu(
1980 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX+
1981 wqe_fragment_index*2]))<<32;
1982 bus_address = (dma_addr_t)u64temp;
1983 pci_unmap_page(nesdev->pcidev,
1986 wqe_fragment_length[
1987 wqe_fragment_index]),
1993 if (nesvnic->nic.tx_skb[nesvnic->nic.sq_tail])
1995 nesvnic->nic.tx_skb[nesvnic->nic.sq_tail]);
1997 nesvnic->nic.sq_tail = (nesvnic->nic.sq_tail + 1)
1998 & (nesvnic->nic.sq_size - 1);
2001 spin_lock_irqsave(&nesdev->cqp.lock, flags);
2003 /* Destroy NIC QP */
2004 cqp_head = nesdev->cqp.sq_head;
2005 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
2006 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
2008 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
2009 (NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC));
2010 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
2011 nesvnic->nic.qp_id);
2013 if (++cqp_head >= nesdev->cqp.sq_size)
2016 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
2018 /* Destroy NIC CQ */
2019 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
2020 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
2021 (NES_CQP_DESTROY_CQ | ((u32)nesvnic->nic_cq.cq_size << 16)));
2022 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
2023 (nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16)));
2025 if (++cqp_head >= nesdev->cqp.sq_size)
2028 nesdev->cqp.sq_head = cqp_head;
2031 /* Ring doorbell (2 WQEs) */
2032 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
2034 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2035 nes_debug(NES_DBG_SHUTDOWN, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
2036 " cqp.sq_tail=%u, cqp.sq_size=%u\n",
2037 cqp_head, nesdev->cqp.sq_head,
2038 nesdev->cqp.sq_tail, nesdev->cqp.sq_size);
2040 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
2043 nes_debug(NES_DBG_SHUTDOWN, "Destroy NIC QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
2044 " cqp.sq_head=%u, cqp.sq_tail=%u\n",
2045 ret, cqp_head, nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
2047 nes_debug(NES_DBG_SHUTDOWN, "NIC QP%u destroy timeout expired\n",
2048 nesvnic->nic.qp_id);
2051 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
2052 nesvnic->nic_pbase);
2054 /* restore old wqm_cfg0 value */
2055 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0);
2061 int nes_napi_isr(struct nes_device *nesdev)
2063 struct nes_adapter *nesadapter = nesdev->nesadapter;
2066 if (nesdev->napi_isr_ran) {
2067 /* interrupt status has already been read in ISR */
2068 int_stat = nesdev->int_stat;
2070 int_stat = nes_read32(nesdev->regs + NES_INT_STAT);
2071 nesdev->int_stat = int_stat;
2072 nesdev->napi_isr_ran = 1;
2075 int_stat &= nesdev->int_req;
2076 /* iff NIC, process here, else wait for DPC */
2077 if ((int_stat) && ((int_stat & 0x0000ff00) == int_stat)) {
2078 nesdev->napi_isr_ran = 0;
2079 nes_write32(nesdev->regs + NES_INT_STAT,
2081 ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0 | NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3)));
2083 /* Process the CEQs */
2084 nes_process_ceq(nesdev, &nesdev->nesadapter->ceq[nesdev->nic_ceq_index]);
2086 if (unlikely((((nesadapter->et_rx_coalesce_usecs_irq) &&
2087 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
2088 ((nesadapter->et_use_adaptive_rx_coalesce) &&
2089 (nesdev->deepcq_count > nesadapter->et_pkt_rate_low))))) {
2090 if ((nesdev->int_req & NES_INT_TIMER) == 0) {
2091 /* Enable Periodic timer interrupts */
2092 nesdev->int_req |= NES_INT_TIMER;
2093 /* ack any pending periodic timer interrupts so we don't get an immediate interrupt */
2094 /* TODO: need to also ack other unused periodic timer values, get from nesadapter */
2095 nes_write32(nesdev->regs+NES_TIMER_STAT,
2096 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2097 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
2098 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
2101 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2103 nes_nic_init_timer(nesdev);
2105 /* Enable interrupts, except CEQs */
2106 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2108 /* Enable interrupts, make sure timer is off */
2109 nesdev->int_req &= ~NES_INT_TIMER;
2110 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2111 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2113 nesdev->deepcq_count = 0;
2120 static void process_critical_error(struct nes_device *nesdev)
2123 u32 nes_idx_debug_error_masks0 = 0;
2124 u16 error_module = 0;
2126 debug_error = nes_read_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS);
2127 printk(KERN_ERR PFX "Critical Error reported by device!!! 0x%02X\n",
2129 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS,
2130 0x01010000 | (debug_error & 0x0000ffff));
2131 if (crit_err_count++ > 10)
2132 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS1, 1 << 0x17);
2133 error_module = (u16) (debug_error & 0x1F00) >> 8;
2134 if (++nesdev->nesadapter->crit_error_count[error_module-1] >=
2135 nes_max_critical_error_count) {
2136 printk(KERN_ERR PFX "Masking off critical error for module "
2137 "0x%02X\n", (u16)error_module);
2138 nes_idx_debug_error_masks0 = nes_read_indexed(nesdev,
2139 NES_IDX_DEBUG_ERROR_MASKS0);
2140 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS0,
2141 nes_idx_debug_error_masks0 | (1 << error_module));
2147 void nes_dpc(unsigned long param)
2149 struct nes_device *nesdev = (struct nes_device *)param;
2150 struct nes_adapter *nesadapter = nesdev->nesadapter;
2152 u32 loop_counter = 0;
2158 u32 processed_intf_int = 0;
2159 u16 processed_timer_int = 0;
2160 u16 completion_ints = 0;
2163 /* nes_debug(NES_DBG_ISR, "\n"); */
2167 if (nesdev->napi_isr_ran) {
2168 nesdev->napi_isr_ran = 0;
2169 int_stat = nesdev->int_stat;
2171 int_stat = nes_read32(nesdev->regs+NES_INT_STAT);
2172 if (processed_intf_int != 0)
2173 int_stat &= nesdev->int_req & ~NES_INT_INTF;
2175 int_stat &= nesdev->int_req;
2176 if (processed_timer_int == 0) {
2177 processed_timer_int = 1;
2178 if (int_stat & NES_INT_TIMER) {
2179 timer_stat = nes_read32(nesdev->regs + NES_TIMER_STAT);
2180 if ((timer_stat & nesdev->timer_int_req) == 0) {
2181 int_stat &= ~NES_INT_TIMER;
2185 int_stat &= ~NES_INT_TIMER;
2189 if (int_stat & ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0|
2190 NES_INT_MAC1|NES_INT_MAC2 | NES_INT_MAC3)) {
2191 /* Ack the interrupts */
2192 nes_write32(nesdev->regs+NES_INT_STAT,
2193 (int_stat & ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0|
2194 NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3)));
2197 temp_int_stat = int_stat;
2198 for (counter = 0, int_status_bit = 1; counter < 16; counter++) {
2199 if (int_stat & int_status_bit) {
2200 nes_process_ceq(nesdev, &nesadapter->ceq[counter]);
2201 temp_int_stat &= ~int_status_bit;
2202 completion_ints = 1;
2204 if (!(temp_int_stat & 0x0000ffff))
2206 int_status_bit <<= 1;
2209 /* Process the AEQ for this pci function */
2210 int_status_bit = 1 << (16 + PCI_FUNC(nesdev->pcidev->devfn));
2211 if (int_stat & int_status_bit) {
2212 nes_process_aeq(nesdev, &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)]);
2215 /* Process the MAC interrupt for this pci function */
2216 int_status_bit = 1 << (24 + nesdev->mac_index);
2217 if (int_stat & int_status_bit) {
2218 nes_process_mac_intr(nesdev, nesdev->mac_index);
2221 if (int_stat & NES_INT_TIMER) {
2222 if (timer_stat & nesdev->timer_int_req) {
2223 nes_write32(nesdev->regs + NES_TIMER_STAT,
2224 (timer_stat & nesdev->timer_int_req) |
2225 ~(nesdev->nesadapter->timer_int_req));
2230 if (int_stat & NES_INT_INTF) {
2231 processed_intf_int = 1;
2232 intf_int_stat = nes_read32(nesdev->regs+NES_INTF_INT_STAT);
2233 intf_int_stat &= nesdev->intf_int_req;
2234 if (NES_INTF_INT_CRITERR & intf_int_stat) {
2235 process_critical_error(nesdev);
2237 if (NES_INTF_INT_PCIERR & intf_int_stat) {
2238 printk(KERN_ERR PFX "PCI Error reported by device!!!\n");
2241 if (NES_INTF_INT_AEQ_OFLOW & intf_int_stat) {
2242 printk(KERN_ERR PFX "AEQ Overflow reported by device!!!\n");
2245 nes_write32(nesdev->regs+NES_INTF_INT_STAT, intf_int_stat);
2248 if (int_stat & NES_INT_TSW) {
2251 /* Don't use the interface interrupt bit stay in loop */
2252 int_stat &= ~NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0 |
2253 NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3;
2254 } while ((int_stat != 0) && (loop_counter++ < MAX_DPC_ITERATIONS));
2256 if (timer_ints == 1) {
2257 if ((nesadapter->et_rx_coalesce_usecs_irq) || (nesadapter->et_use_adaptive_rx_coalesce)) {
2258 if (completion_ints == 0) {
2259 nesdev->timer_only_int_count++;
2260 if (nesdev->timer_only_int_count>=nesadapter->timer_int_limit) {
2261 nesdev->timer_only_int_count = 0;
2262 nesdev->int_req &= ~NES_INT_TIMER;
2263 nes_write32(nesdev->regs + NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2264 nes_write32(nesdev->regs + NES_INT_MASK, ~nesdev->int_req);
2266 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2269 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2271 nes_nic_init_timer(nesdev);
2273 nesdev->timer_only_int_count = 0;
2274 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2277 nesdev->timer_only_int_count = 0;
2278 nesdev->int_req &= ~NES_INT_TIMER;
2279 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2280 nes_write32(nesdev->regs+NES_TIMER_STAT,
2281 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2282 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2285 if ( (completion_ints == 1) &&
2286 (((nesadapter->et_rx_coalesce_usecs_irq) &&
2287 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
2288 ((nesdev->deepcq_count > nesadapter->et_pkt_rate_low) &&
2289 (nesadapter->et_use_adaptive_rx_coalesce) )) ) {
2290 /* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
2291 nesdev->timer_only_int_count = 0;
2292 nesdev->int_req |= NES_INT_TIMER;
2293 nes_write32(nesdev->regs+NES_TIMER_STAT,
2294 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2295 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
2296 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
2297 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2299 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2302 nesdev->deepcq_count = 0;
2309 static void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq)
2312 struct nes_hw_cq *cq;
2316 /* nes_debug(NES_DBG_CQ, "\n"); */
2317 head = ceq->ceq_head;
2318 ceq_size = ceq->ceq_size;
2321 if (le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]) &
2323 u64temp = (((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]))) << 32) |
2324 ((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_LOW_IDX])));
2326 cq = *((struct nes_hw_cq **)&u64temp);
2327 /* nes_debug(NES_DBG_CQ, "pCQ = %p\n", cq); */
2329 ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX] = 0;
2331 /* call the event handler */
2332 cq->ce_handler(nesdev, cq);
2334 if (++head >= ceq_size)
2342 ceq->ceq_head = head;
2349 static void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq)
2356 struct nes_hw_aeqe volatile *aeqe;
2358 head = aeq->aeq_head;
2359 aeq_size = aeq->aeq_size;
2362 aeqe = &aeq->aeq_vbase[head];
2363 if ((le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]) & NES_AEQE_VALID) == 0)
2365 aeqe_misc = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
2366 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
2367 if (aeqe_misc & (NES_AEQE_QP|NES_AEQE_CQ)) {
2368 if (aeqe_cq_id >= NES_FIRST_QPN) {
2369 /* dealing with an accelerated QP related AE */
2371 * u64temp = (((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX]))) << 32) |
2372 * ((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX])));
2374 nes_process_iwarp_aeqe(nesdev, (struct nes_hw_aeqe *)aeqe);
2376 /* TODO: dealing with a CQP related AE */
2377 nes_debug(NES_DBG_AEQ, "Processing CQP related AE, misc = 0x%04X\n",
2378 (u16)(aeqe_misc >> 16));
2382 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = 0;
2384 if (++head >= aeq_size)
2387 nes_write32(nesdev->regs + NES_AEQ_ALLOC, 1 << 16);
2390 aeq->aeq_head = head;
2393 static void nes_reset_link(struct nes_device *nesdev, u32 mac_index)
2395 struct nes_adapter *nesadapter = nesdev->nesadapter;
2400 if (nesadapter->hw_rev == NE020_REV) {
2405 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
2407 if ((mac_index == 0) || ((mac_index == 1) && (nesadapter->OneG_Mode)))
2408 reset_value |= 0x0000001d;
2410 reset_value |= 0x0000002d;
2412 if (4 <= (nesadapter->link_interrupt_count[mac_index] / ((u16)NES_MAX_LINK_INTERRUPTS))) {
2413 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
2414 nesadapter->link_interrupt_count[0] = 0;
2415 nesadapter->link_interrupt_count[1] = 0;
2416 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2417 if (0x00000040 & u32temp)
2418 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2420 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2422 reset_value |= 0x0000003d;
2424 nesadapter->link_interrupt_count[mac_index] = 0;
2427 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2429 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
2430 & 0x00000040) != 0x00000040) && (i++ < 5000));
2432 if (0x0000003d == (reset_value & 0x0000003d)) {
2433 u32 pcs_control_status0, pcs_control_status1;
2435 for (i = 0; i < 10; i++) {
2436 pcs_control_status0 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0);
2437 pcs_control_status1 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2438 if (((0x0F000000 == (pcs_control_status0 & 0x0F000000))
2439 && (pcs_control_status0 & 0x00100000))
2440 || ((0x0F000000 == (pcs_control_status1 & 0x0F000000))
2441 && (pcs_control_status1 & 0x00100000)))
2447 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2448 if (0x00000040 & u32temp)
2449 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2451 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2453 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2455 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET)
2456 & 0x00000040) != 0x00000040) && (i++ < 5000));
2462 * nes_process_mac_intr
2464 static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2466 unsigned long flags;
2467 u32 pcs_control_status;
2468 struct nes_adapter *nesadapter = nesdev->nesadapter;
2469 struct nes_vnic *nesvnic;
2471 u32 mac_index = nesdev->mac_index;
2475 u32 pcs_val = 0x0f0f0000;
2476 u32 pcs_mask = 0x0f1f0000;
2479 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2480 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
2481 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2484 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_INTERRUPT;
2486 /* ack the MAC interrupt */
2487 mac_status = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200));
2488 /* Clear the interrupt */
2489 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200), mac_status);
2491 nes_debug(NES_DBG_PHY, "MAC%u interrupt status = 0x%X.\n", mac_number, mac_status);
2493 if (mac_status & (NES_MAC_INT_LINK_STAT_CHG | NES_MAC_INT_XGMII_EXT)) {
2494 nesdev->link_status_interrupts++;
2495 if (0 == (++nesadapter->link_interrupt_count[mac_index] % ((u16)NES_MAX_LINK_INTERRUPTS)))
2496 nes_reset_link(nesdev, mac_index);
2498 /* read the PHY interrupt status register */
2499 if ((nesadapter->OneG_Mode) &&
2500 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
2502 nes_read_1G_phy_reg(nesdev, 0x1a,
2503 nesadapter->phy_index[mac_index], &phy_data);
2504 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1a = 0x%X.\n",
2505 nesadapter->phy_index[mac_index], phy_data);
2506 } while (phy_data&0x8000);
2510 nes_read_1G_phy_reg(nesdev, 0x11,
2511 nesadapter->phy_index[mac_index], &phy_data);
2512 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x11 = 0x%X.\n",
2513 nesadapter->phy_index[mac_index], phy_data);
2514 if (temp_phy_data == phy_data)
2516 temp_phy_data = phy_data;
2519 nes_read_1G_phy_reg(nesdev, 0x1e,
2520 nesadapter->phy_index[mac_index], &phy_data);
2521 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1e = 0x%X.\n",
2522 nesadapter->phy_index[mac_index], phy_data);
2524 nes_read_1G_phy_reg(nesdev, 1,
2525 nesadapter->phy_index[mac_index], &phy_data);
2526 nes_debug(NES_DBG_PHY, "1G phy%u data from register 1 = 0x%X\n",
2527 nesadapter->phy_index[mac_index], phy_data);
2529 if (temp_phy_data & 0x1000) {
2530 nes_debug(NES_DBG_PHY, "The Link is up according to the PHY\n");
2533 nes_debug(NES_DBG_PHY, "The Link is down according to the PHY\n");
2536 nes_debug(NES_DBG_PHY, "Eth SERDES Common Status: 0=0x%08X, 1=0x%08X\n",
2537 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0),
2538 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0+0x200));
2540 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_PUMA_1G) {
2541 switch (mac_index) {
2544 pcs_control_status = nes_read_indexed(nesdev,
2545 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2548 pcs_control_status = nes_read_indexed(nesdev,
2549 NES_IDX_PHY_PCS_CONTROL_STATUS0);
2553 pcs_control_status = nes_read_indexed(nesdev,
2554 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index & 1) * 0x200));
2555 pcs_control_status = nes_read_indexed(nesdev,
2556 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index & 1) * 0x200));
2559 nes_debug(NES_DBG_PHY, "PCS PHY Control/Status%u: 0x%08X\n",
2560 mac_index, pcs_control_status);
2561 if ((nesadapter->OneG_Mode) &&
2562 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
2563 u32temp = 0x01010000;
2564 if (nesadapter->port_count > 2) {
2565 u32temp |= 0x02020000;
2567 if ((pcs_control_status & u32temp)!= u32temp) {
2569 nes_debug(NES_DBG_PHY, "PCS says the link is down\n");
2572 switch (nesadapter->phy_type[mac_index]) {
2573 case NES_PHY_TYPE_ARGUS:
2574 case NES_PHY_TYPE_SFP_D:
2575 case NES_PHY_TYPE_KR:
2576 /* clear the alarms */
2577 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008);
2578 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001);
2579 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc002);
2580 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc005);
2581 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc006);
2582 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2583 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
2584 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
2585 /* check link status */
2586 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2587 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2589 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2590 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2591 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2592 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2594 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2596 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2597 __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2600 case NES_PHY_TYPE_PUMA_1G:
2602 pcs_val = pcs_mask = 0x01010000;
2604 pcs_val = pcs_mask = 0x02020000;
2607 phy_data = (pcs_val == (pcs_control_status & pcs_mask)) ? 0x4 : 0x0;
2612 if (phy_data & 0x0004) {
2613 if (wide_ppm_offset &&
2614 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2615 (nesadapter->hw_rev != NE020_REV)) {
2616 cdr_ctrl = nes_read_indexed(nesdev,
2617 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2619 nes_write_indexed(nesdev,
2620 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2622 cdr_ctrl | 0x000F0000);
2624 nesadapter->mac_link_down[mac_index] = 0;
2625 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2626 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
2628 if (nesvnic->linkup == 0) {
2629 printk(PFX "The Link is now up for port %s, netdev %p.\n",
2630 nesvnic->netdev->name, nesvnic->netdev);
2631 if (netif_queue_stopped(nesvnic->netdev))
2632 netif_start_queue(nesvnic->netdev);
2633 nesvnic->linkup = 1;
2634 netif_carrier_on(nesvnic->netdev);
2636 spin_lock(&nesvnic->port_ibevent_lock);
2637 if (nesvnic->of_device_registered) {
2638 if (nesdev->iw_status == 0) {
2639 nesdev->iw_status = 1;
2640 nes_port_ibevent(nesvnic);
2643 spin_unlock(&nesvnic->port_ibevent_lock);
2647 if (wide_ppm_offset &&
2648 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2649 (nesadapter->hw_rev != NE020_REV)) {
2650 cdr_ctrl = nes_read_indexed(nesdev,
2651 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2653 nes_write_indexed(nesdev,
2654 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2656 cdr_ctrl & 0xFFF0FFFF);
2658 nesadapter->mac_link_down[mac_index] = 1;
2659 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2660 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
2662 if (nesvnic->linkup == 1) {
2663 printk(PFX "The Link is now down for port %s, netdev %p.\n",
2664 nesvnic->netdev->name, nesvnic->netdev);
2665 if (!(netif_queue_stopped(nesvnic->netdev)))
2666 netif_stop_queue(nesvnic->netdev);
2667 nesvnic->linkup = 0;
2668 netif_carrier_off(nesvnic->netdev);
2670 spin_lock(&nesvnic->port_ibevent_lock);
2671 if (nesvnic->of_device_registered) {
2672 if (nesdev->iw_status == 1) {
2673 nesdev->iw_status = 0;
2674 nes_port_ibevent(nesvnic);
2677 spin_unlock(&nesvnic->port_ibevent_lock);
2681 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_SFP_D) {
2682 if (nesdev->link_recheck)
2683 cancel_delayed_work(&nesdev->work);
2684 nesdev->link_recheck = 1;
2685 schedule_delayed_work(&nesdev->work,
2686 NES_LINK_RECHECK_DELAY);
2690 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2692 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_IDLE;
2695 void nes_recheck_link_status(struct work_struct *work)
2697 unsigned long flags;
2698 struct nes_device *nesdev = container_of(work, struct nes_device, work.work);
2699 struct nes_adapter *nesadapter = nesdev->nesadapter;
2700 struct nes_vnic *nesvnic;
2701 u32 mac_index = nesdev->mac_index;
2705 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2707 /* check link status */
2708 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2709 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2711 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2712 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2713 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2714 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2716 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2718 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2720 nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2722 if (phy_data & 0x0004) {
2723 nesadapter->mac_link_down[mac_index] = 0;
2724 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2725 if (nesvnic->linkup == 0) {
2726 printk(PFX "The Link is now up for port %s, netdev %p.\n",
2727 nesvnic->netdev->name, nesvnic->netdev);
2728 if (netif_queue_stopped(nesvnic->netdev))
2729 netif_start_queue(nesvnic->netdev);
2730 nesvnic->linkup = 1;
2731 netif_carrier_on(nesvnic->netdev);
2733 spin_lock(&nesvnic->port_ibevent_lock);
2734 if (nesvnic->of_device_registered) {
2735 if (nesdev->iw_status == 0) {
2736 nesdev->iw_status = 1;
2737 nes_port_ibevent(nesvnic);
2740 spin_unlock(&nesvnic->port_ibevent_lock);
2745 nesadapter->mac_link_down[mac_index] = 1;
2746 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2747 if (nesvnic->linkup == 1) {
2748 printk(PFX "The Link is now down for port %s, netdev %p.\n",
2749 nesvnic->netdev->name, nesvnic->netdev);
2750 if (!(netif_queue_stopped(nesvnic->netdev)))
2751 netif_stop_queue(nesvnic->netdev);
2752 nesvnic->linkup = 0;
2753 netif_carrier_off(nesvnic->netdev);
2755 spin_lock(&nesvnic->port_ibevent_lock);
2756 if (nesvnic->of_device_registered) {
2757 if (nesdev->iw_status == 1) {
2758 nesdev->iw_status = 0;
2759 nes_port_ibevent(nesvnic);
2762 spin_unlock(&nesvnic->port_ibevent_lock);
2766 if (nesdev->link_recheck++ < NES_LINK_RECHECK_MAX)
2767 schedule_delayed_work(&nesdev->work, NES_LINK_RECHECK_DELAY);
2769 nesdev->link_recheck = 0;
2771 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2775 static void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2777 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2779 napi_schedule(&nesvnic->napi);
2783 /* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
2784 * getting out of nic_ce_handler
2786 #define MAX_RQES_TO_PROCESS 384
2789 * nes_nic_ce_handler
2791 void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2794 dma_addr_t bus_address;
2795 struct nes_hw_nic *nesnic;
2796 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2797 struct nes_adapter *nesadapter = nesdev->nesadapter;
2798 struct nes_hw_nic_rq_wqe *nic_rqe;
2799 struct nes_hw_nic_sq_wqe *nic_sqe;
2800 struct sk_buff *skb;
2801 struct sk_buff *rx_skb;
2802 struct nes_rskb_cb *cb;
2803 __le16 *wqe_fragment_length;
2810 u16 wqe_fragment_index = 1; /* first fragment (0) is used by copy buffer */
2813 u16 rqes_processed = 0;
2818 cq_size = cq->cq_size;
2819 cq->cqes_pending = 1;
2820 if (nesvnic->netdev->features & NETIF_F_LRO)
2823 if (le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]) &
2824 NES_NIC_CQE_VALID) {
2825 nesnic = &nesvnic->nic;
2826 cqe_misc = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]);
2827 if (cqe_misc & NES_NIC_CQE_SQ) {
2829 wqe_fragment_index = 1;
2830 nic_sqe = &nesnic->sq_vbase[nesnic->sq_tail];
2831 skb = nesnic->tx_skb[nesnic->sq_tail];
2832 wqe_fragment_length = (__le16 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
2833 /* bump past the vlan tag */
2834 wqe_fragment_length++;
2835 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
2836 u64temp = (u64) le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX +
2837 wqe_fragment_index * 2]);
2838 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX +
2839 wqe_fragment_index * 2])) << 32;
2840 bus_address = (dma_addr_t)u64temp;
2841 if (test_and_clear_bit(nesnic->sq_tail, nesnic->first_frag_overflow)) {
2842 pci_unmap_single(nesdev->pcidev,
2844 le16_to_cpu(wqe_fragment_length[wqe_fragment_index++]),
2847 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
2848 if (wqe_fragment_length[wqe_fragment_index]) {
2849 u64temp = le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX +
2850 wqe_fragment_index * 2]);
2851 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
2852 + wqe_fragment_index * 2])) <<32;
2853 bus_address = (dma_addr_t)u64temp;
2854 pci_unmap_page(nesdev->pcidev,
2856 le16_to_cpu(wqe_fragment_length[wqe_fragment_index]),
2863 dev_kfree_skb_any(skb);
2865 nesnic->sq_tail &= nesnic->sq_size-1;
2866 if (sq_cqes > 128) {
2868 /* restart the queue if it had been stopped */
2869 if (netif_queue_stopped(nesvnic->netdev))
2870 netif_wake_queue(nesvnic->netdev);
2876 cq->rx_cqes_completed++;
2877 cq->rx_pkts_indicated++;
2878 rx_pkt_size = cqe_misc & 0x0000ffff;
2879 nic_rqe = &nesnic->rq_vbase[nesnic->rq_tail];
2881 rx_skb = nesnic->rx_skb[nesnic->rq_tail];
2882 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_tail];
2883 bus_address = (dma_addr_t)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX]);
2884 bus_address += ((u64)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX])) << 32;
2885 pci_unmap_single(nesdev->pcidev, bus_address,
2886 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
2887 cb = (struct nes_rskb_cb *)&rx_skb->cb[0];
2889 /* rx_skb->tail = rx_skb->data + rx_pkt_size; */
2890 /* rx_skb->len = rx_pkt_size; */
2891 rx_skb->len = 0; /* TODO: see if this is necessary */
2892 skb_put(rx_skb, rx_pkt_size);
2893 rx_skb->protocol = eth_type_trans(rx_skb, nesvnic->netdev);
2895 nesnic->rq_tail &= nesnic->rq_size - 1;
2897 atomic_inc(&nesvnic->rx_skbs_needed);
2898 if (atomic_read(&nesvnic->rx_skbs_needed) > (nesvnic->nic.rq_size>>1)) {
2899 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2900 cq->cq_number | (cqe_count << 16));
2901 /* nesadapter->tune_timer.cq_count += cqe_count; */
2902 nesdev->currcq_count += cqe_count;
2904 nes_replenish_nic_rq(nesvnic);
2906 pkt_type = (u16)(le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX]));
2907 cqe_errv = (cqe_misc & NES_NIC_CQE_ERRV_MASK) >> NES_NIC_CQE_ERRV_SHIFT;
2908 rx_skb->ip_summed = CHECKSUM_NONE;
2910 if ((NES_PKT_TYPE_TCPV4_BITS == (pkt_type & NES_PKT_TYPE_TCPV4_MASK)) ||
2911 (NES_PKT_TYPE_UDPV4_BITS == (pkt_type & NES_PKT_TYPE_UDPV4_MASK))) {
2913 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR |
2914 NES_NIC_ERRV_BITS_IPH_ERR | NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
2915 if (nesvnic->netdev->features & NETIF_F_RXCSUM)
2916 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2918 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2919 " errv = 0x%X, pkt_type = 0x%X.\n",
2920 nesvnic->netdev->name, cqe_errv, pkt_type);
2922 } else if ((pkt_type & NES_PKT_TYPE_IPV4_MASK) == NES_PKT_TYPE_IPV4_BITS) {
2924 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_IPH_ERR |
2925 NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
2926 if (nesvnic->netdev->features & NETIF_F_RXCSUM) {
2927 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2928 /* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
2929 nesvnic->netdev->name); */
2932 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2933 " errv = 0x%X, pkt_type = 0x%X.\n",
2934 nesvnic->netdev->name, cqe_errv, pkt_type);
2936 /* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
2937 pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
2939 if ((pkt_type & NES_PKT_TYPE_APBVT_MASK) == NES_PKT_TYPE_APBVT_BITS) {
2940 if (nes_cm_recv(rx_skb, nesvnic->netdev))
2944 goto skip_rx_indicate0;
2947 if (cqe_misc & NES_NIC_CQE_TAG_VALID) {
2948 vlan_tag = (u16)(le32_to_cpu(
2949 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX])
2951 nes_debug(NES_DBG_CQ, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n",
2952 nesvnic->netdev->name, vlan_tag);
2954 __vlan_hwaccel_put_tag(rx_skb, vlan_tag);
2957 lro_receive_skb(&nesvnic->lro_mgr, rx_skb, NULL);
2959 netif_receive_skb(rx_skb);
2963 /* nesvnic->netstats.rx_packets++; */
2964 /* nesvnic->netstats.rx_bytes += rx_pkt_size; */
2967 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX] = 0;
2970 if (++head >= cq_size)
2972 if (cqe_count == 255) {
2973 /* Replenish Nic CQ */
2974 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2975 cq->cq_number | (cqe_count << 16));
2976 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2977 nesdev->currcq_count += cqe_count;
2981 if (cq->rx_cqes_completed >= nesvnic->budget)
2984 cq->cqes_pending = 0;
2991 lro_flush_all(&nesvnic->lro_mgr);
2994 /* restart the queue if it had been stopped */
2995 if (netif_queue_stopped(nesvnic->netdev))
2996 netif_wake_queue(nesvnic->netdev);
2999 /* nes_debug(NES_DBG_CQ, "CQ%u Processed = %u cqes, new head = %u.\n",
3000 cq->cq_number, cqe_count, cq->cq_head); */
3001 cq->cqe_allocs_pending = cqe_count;
3002 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
3004 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
3005 nesdev->currcq_count += cqe_count;
3006 nes_nic_tune_timer(nesdev);
3008 if (atomic_read(&nesvnic->rx_skbs_needed))
3009 nes_replenish_nic_rq(nesvnic);
3015 * nes_cqp_ce_handler
3017 static void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
3020 unsigned long flags;
3021 struct nes_hw_cqp *cqp = NULL;
3022 struct nes_cqp_request *cqp_request;
3023 struct nes_hw_cqp_wqe *cqp_wqe;
3033 cq_size = cq->cq_size;
3036 /* process the CQE */
3037 /* nes_debug(NES_DBG_CQP, "head=%u cqe_words=%08X\n", head,
3038 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])); */
3040 opcode = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX]);
3041 if (opcode & NES_CQE_VALID) {
3044 error_code = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_ERROR_CODE_IDX]);
3046 nes_debug(NES_DBG_CQP, "Bad Completion code for opcode 0x%02X from CQP,"
3047 " Major/Minor codes = 0x%04X:%04X.\n",
3048 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])&0x3f,
3049 (u16)(error_code >> 16),
3053 u64temp = (((u64)(le32_to_cpu(cq->cq_vbase[head].
3054 cqe_words[NES_CQE_COMP_COMP_CTX_HIGH_IDX]))) << 32) |
3055 ((u64)(le32_to_cpu(cq->cq_vbase[head].
3056 cqe_words[NES_CQE_COMP_COMP_CTX_LOW_IDX])));
3058 cqp_request = (struct nes_cqp_request *)(unsigned long)u64temp;
3060 if (cqp_request->waiting) {
3061 /* nes_debug(NES_DBG_CQP, "%s: Waking up requestor\n"); */
3062 cqp_request->major_code = (u16)(error_code >> 16);
3063 cqp_request->minor_code = (u16)error_code;
3065 cqp_request->request_done = 1;
3066 wake_up(&cqp_request->waitq);
3067 nes_put_cqp_request(nesdev, cqp_request);
3069 if (cqp_request->callback)
3070 cqp_request->cqp_callback(nesdev, cqp_request);
3071 nes_free_cqp_request(nesdev, cqp_request);
3074 wake_up(&nesdev->cqp.waitq);
3077 cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX] = 0;
3078 nes_write32(nesdev->regs + NES_CQE_ALLOC, cq->cq_number | (1 << 16));
3079 if (++cqp->sq_tail >= cqp->sq_size)
3084 if (++head >= cq_size)
3092 spin_lock_irqsave(&nesdev->cqp.lock, flags);
3093 while ((!list_empty(&nesdev->cqp_pending_reqs)) &&
3094 ((((nesdev->cqp.sq_tail+nesdev->cqp.sq_size)-nesdev->cqp.sq_head) &
3095 (nesdev->cqp.sq_size - 1)) != 1)) {
3096 cqp_request = list_entry(nesdev->cqp_pending_reqs.next,
3097 struct nes_cqp_request, list);
3098 list_del_init(&cqp_request->list);
3099 head = nesdev->cqp.sq_head++;
3100 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
3101 cqp_wqe = &nesdev->cqp.sq_vbase[head];
3102 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
3105 opcode = cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX];
3106 if ((opcode & NES_CQP_OPCODE_MASK) == NES_CQP_DOWNLOAD_SEGMENT)
3107 ctx_index = NES_CQP_WQE_DL_COMP_CTX_LOW_IDX;
3109 ctx_index = NES_CQP_WQE_COMP_CTX_LOW_IDX;
3110 cqp_wqe->wqe_words[ctx_index] =
3111 cpu_to_le32((u32)((unsigned long)cqp_request));
3112 cqp_wqe->wqe_words[ctx_index + 1] =
3113 cpu_to_le32((u32)(upper_32_bits((unsigned long)cqp_request)));
3114 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) put on CQPs SQ wqe%u.\n",
3115 cqp_request, le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f, head);
3116 /* Ring doorbell (1 WQEs) */
3118 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
3120 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
3123 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
3125 nes_read32(nesdev->regs+NES_CQE_ALLOC);
3128 static u8 *locate_mpa(u8 *pkt, u32 aeq_info)
3130 if (aeq_info & NES_AEQE_Q2_DATA_ETHERNET) {
3131 /* skip over ethernet header */
3134 /* Skip over IP and TCP headers */
3135 pkt += 4 * (pkt[0] & 0x0f);
3136 pkt += 4 * ((pkt[12] >> 4) & 0x0f);
3141 /* Determine if incoming error pkt is rdma layer */
3142 static u32 iwarp_opcode(struct nes_qp *nesqp, u32 aeq_info)
3146 u32 opcode = 0xffffffff;
3148 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3149 pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3150 mpa = (u16 *)locate_mpa(pkt, aeq_info);
3151 opcode = be16_to_cpu(mpa[1]) & 0xf;
3157 /* Build iWARP terminate header */
3158 static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 aeq_info)
3160 u8 *pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3165 struct nes_terminate_hdr *termhdr;
3167 termhdr = (struct nes_terminate_hdr *)nesqp->hwqp.q2_vbase;
3168 memset(termhdr, 0, 64);
3170 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3172 /* Use data from offending packet to fill in ddp & rdma hdrs */
3173 pkt = locate_mpa(pkt, aeq_info);
3174 ddp_seg_len = be16_to_cpu(*(u16 *)pkt);
3177 termhdr->hdrct = DDP_LEN_FLAG;
3178 if (pkt[2] & 0x80) {
3180 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
3181 copy_len += TERM_DDP_LEN_TAGGED;
3182 termhdr->hdrct |= DDP_HDR_FLAG;
3185 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
3186 copy_len += TERM_DDP_LEN_UNTAGGED;
3187 termhdr->hdrct |= DDP_HDR_FLAG;
3190 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) {
3191 if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) {
3192 copy_len += TERM_RDMA_LEN;
3193 termhdr->hdrct |= RDMA_HDR_FLAG;
3200 switch (async_event_id) {
3201 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
3202 switch (iwarp_opcode(nesqp, aeq_info)) {
3203 case IWARP_OPCODE_WRITE:
3204 flush_code = IB_WC_LOC_PROT_ERR;
3205 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3206 termhdr->error_code = DDP_TAGGED_INV_STAG;
3209 flush_code = IB_WC_REM_ACCESS_ERR;
3210 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3211 termhdr->error_code = RDMAP_INV_STAG;
3214 case NES_AEQE_AEID_AMP_INVALID_STAG:
3215 flush_code = IB_WC_REM_ACCESS_ERR;
3216 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3217 termhdr->error_code = RDMAP_INV_STAG;
3219 case NES_AEQE_AEID_AMP_BAD_QP:
3220 flush_code = IB_WC_LOC_QP_OP_ERR;
3221 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3222 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3224 case NES_AEQE_AEID_AMP_BAD_STAG_KEY:
3225 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
3226 switch (iwarp_opcode(nesqp, aeq_info)) {
3227 case IWARP_OPCODE_SEND_INV:
3228 case IWARP_OPCODE_SEND_SE_INV:
3229 flush_code = IB_WC_REM_OP_ERR;
3230 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3231 termhdr->error_code = RDMAP_CANT_INV_STAG;
3234 flush_code = IB_WC_REM_ACCESS_ERR;
3235 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3236 termhdr->error_code = RDMAP_INV_STAG;
3239 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3240 if (aeq_info & (NES_AEQE_Q2_DATA_ETHERNET | NES_AEQE_Q2_DATA_MPA)) {
3241 flush_code = IB_WC_LOC_PROT_ERR;
3242 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3243 termhdr->error_code = DDP_TAGGED_BOUNDS;
3245 flush_code = IB_WC_REM_ACCESS_ERR;
3246 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3247 termhdr->error_code = RDMAP_INV_BOUNDS;
3250 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3251 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3252 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
3253 flush_code = IB_WC_REM_ACCESS_ERR;
3254 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3255 termhdr->error_code = RDMAP_ACCESS;
3257 case NES_AEQE_AEID_AMP_TO_WRAP:
3258 flush_code = IB_WC_REM_ACCESS_ERR;
3259 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3260 termhdr->error_code = RDMAP_TO_WRAP;
3262 case NES_AEQE_AEID_AMP_BAD_PD:
3263 switch (iwarp_opcode(nesqp, aeq_info)) {
3264 case IWARP_OPCODE_WRITE:
3265 flush_code = IB_WC_LOC_PROT_ERR;
3266 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3267 termhdr->error_code = DDP_TAGGED_UNASSOC_STAG;
3269 case IWARP_OPCODE_SEND_INV:
3270 case IWARP_OPCODE_SEND_SE_INV:
3271 flush_code = IB_WC_REM_ACCESS_ERR;
3272 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3273 termhdr->error_code = RDMAP_CANT_INV_STAG;
3276 flush_code = IB_WC_REM_ACCESS_ERR;
3277 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3278 termhdr->error_code = RDMAP_UNASSOC_STAG;
3281 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
3282 flush_code = IB_WC_LOC_LEN_ERR;
3283 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3284 termhdr->error_code = MPA_MARKER;
3286 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
3287 flush_code = IB_WC_GENERAL_ERR;
3288 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3289 termhdr->error_code = MPA_CRC;
3291 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3292 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
3293 flush_code = IB_WC_LOC_LEN_ERR;
3294 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3295 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3297 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3298 case NES_AEQE_AEID_DDP_NO_L_BIT:
3299 flush_code = IB_WC_FATAL_ERR;
3300 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3301 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3303 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3304 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
3305 flush_code = IB_WC_GENERAL_ERR;
3306 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3307 termhdr->error_code = DDP_UNTAGGED_INV_MSN_RANGE;
3309 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
3310 flush_code = IB_WC_LOC_LEN_ERR;
3311 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3312 termhdr->error_code = DDP_UNTAGGED_INV_TOO_LONG;
3314 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
3315 flush_code = IB_WC_GENERAL_ERR;
3317 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3318 termhdr->error_code = DDP_TAGGED_INV_DDP_VER;
3320 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3321 termhdr->error_code = DDP_UNTAGGED_INV_DDP_VER;
3324 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
3325 flush_code = IB_WC_GENERAL_ERR;
3326 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3327 termhdr->error_code = DDP_UNTAGGED_INV_MO;
3329 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
3330 flush_code = IB_WC_REM_OP_ERR;
3331 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3332 termhdr->error_code = DDP_UNTAGGED_INV_MSN_NO_BUF;
3334 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
3335 flush_code = IB_WC_GENERAL_ERR;
3336 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3337 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3339 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
3340 flush_code = IB_WC_GENERAL_ERR;
3341 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3342 termhdr->error_code = RDMAP_INV_RDMAP_VER;
3344 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
3345 flush_code = IB_WC_LOC_QP_OP_ERR;
3346 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3347 termhdr->error_code = RDMAP_UNEXPECTED_OP;
3350 flush_code = IB_WC_FATAL_ERR;
3351 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3352 termhdr->error_code = RDMAP_UNSPECIFIED;
3357 memcpy(termhdr + 1, pkt, copy_len);
3359 if ((flush_code) && ((NES_AEQE_INBOUND_RDMA & aeq_info) == 0)) {
3360 if (aeq_info & NES_AEQE_SQ)
3361 nesqp->term_sq_flush_code = flush_code;
3363 nesqp->term_rq_flush_code = flush_code;
3366 return sizeof(struct nes_terminate_hdr) + copy_len;
3369 static void nes_terminate_connection(struct nes_device *nesdev, struct nes_qp *nesqp,
3370 struct nes_hw_aeqe *aeqe, enum ib_event_type eventtype)
3373 unsigned long flags;
3379 u32 mod_qp_flags = NES_CQP_QP_IWARP_STATE_TERMINATE |
3380 NES_CQP_QP_TERM_DONT_SEND_FIN;
3381 struct nes_adapter *nesadapter = nesdev->nesadapter;
3383 if (nesqp->term_flags & NES_TERM_SENT)
3384 return; /* Sanity check */
3386 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3387 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3388 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3389 async_event_id = (u16)aeq_info;
3391 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
3392 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]) - NES_FIRST_QPN];
3398 nesqp = (struct nes_qp *)(unsigned long)context;
3399 spin_lock_irqsave(&nesqp->lock, flags);
3400 nesqp->hw_iwarp_state = iwarp_state;
3401 nesqp->hw_tcp_state = tcp_state;
3402 nesqp->last_aeq = async_event_id;
3403 nesqp->terminate_eventtype = eventtype;
3404 spin_unlock_irqrestore(&nesqp->lock, flags);
3406 if (nesadapter->send_term_ok)
3407 termlen = nes_bld_terminate_hdr(nesqp, async_event_id, aeq_info);
3409 mod_qp_flags |= NES_CQP_QP_TERM_DONT_SEND_TERM_MSG;
3411 if (!nesdev->iw_status) {
3412 nesqp->term_flags = NES_TERM_DONE;
3413 nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_ERROR, 0, 0);
3414 nes_cm_disconn(nesqp);
3416 nes_terminate_start_timer(nesqp);
3417 nesqp->term_flags |= NES_TERM_SENT;
3418 nes_hw_modify_qp(nesdev, nesqp, mod_qp_flags, termlen, 0);
3422 static void nes_terminate_send_fin(struct nes_device *nesdev,
3423 struct nes_qp *nesqp, struct nes_hw_aeqe *aeqe)
3429 unsigned long flags;
3431 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3432 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3433 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3434 async_event_id = (u16)aeq_info;
3436 spin_lock_irqsave(&nesqp->lock, flags);
3437 nesqp->hw_iwarp_state = iwarp_state;
3438 nesqp->hw_tcp_state = tcp_state;
3439 nesqp->last_aeq = async_event_id;
3440 spin_unlock_irqrestore(&nesqp->lock, flags);
3442 /* Send the fin only */
3443 nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_TERMINATE |
3444 NES_CQP_QP_TERM_DONT_SEND_TERM_MSG, 0, 0);
3447 /* Cleanup after a terminate sent or received */
3448 static void nes_terminate_done(struct nes_qp *nesqp, int timeout_occurred)
3450 u32 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR;
3451 unsigned long flags;
3452 struct nes_vnic *nesvnic = to_nesvnic(nesqp->ibqp.device);
3453 struct nes_device *nesdev = nesvnic->nesdev;
3456 spin_lock_irqsave(&nesqp->lock, flags);
3457 if (nesqp->hte_added) {
3458 nesqp->hte_added = 0;
3459 next_iwarp_state |= NES_CQP_QP_DEL_HTE;
3462 first_time = (nesqp->term_flags & NES_TERM_DONE) == 0;
3463 nesqp->term_flags |= NES_TERM_DONE;
3464 spin_unlock_irqrestore(&nesqp->lock, flags);
3466 /* Make sure we go through this only once */
3468 if (timeout_occurred == 0)
3469 del_timer(&nesqp->terminate_timer);
3471 next_iwarp_state |= NES_CQP_QP_RESET;
3473 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3474 nes_cm_disconn(nesqp);
3478 static void nes_terminate_received(struct nes_device *nesdev,
3479 struct nes_qp *nesqp, struct nes_hw_aeqe *aeqe)
3488 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3489 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3490 /* Terminate is not a performance path so the silicon */
3491 /* did not validate the frame - do it now */
3492 pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3493 mpa = (u32 *)locate_mpa(pkt, aeq_info);
3494 ddp_ctl = (be32_to_cpu(mpa[0]) >> 8) & 0xff;
3495 rdma_ctl = be32_to_cpu(mpa[0]) & 0xff;
3496 if ((ddp_ctl & 0xc0) != 0x40)
3497 aeq_id = NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC;
3498 else if ((ddp_ctl & 0x03) != 1)
3499 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION;
3500 else if (be32_to_cpu(mpa[2]) != 2)
3501 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_QN;
3502 else if (be32_to_cpu(mpa[3]) != 1)
3503 aeq_id = NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN;
3504 else if (be32_to_cpu(mpa[4]) != 0)
3505 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_MO;
3506 else if ((rdma_ctl & 0xc0) != 0x40)
3507 aeq_id = NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION;
3510 /* Bad terminate recvd - send back a terminate */
3511 aeq_info = (aeq_info & 0xffff0000) | aeq_id;
3512 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3513 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL);
3518 nesqp->term_flags |= NES_TERM_RCVD;
3519 nesqp->terminate_eventtype = IB_EVENT_QP_FATAL;
3520 nes_terminate_start_timer(nesqp);
3521 nes_terminate_send_fin(nesdev, nesqp, aeqe);
3524 /* Timeout routine in case terminate fails to complete */
3525 static void nes_terminate_timeout(unsigned long context)
3527 struct nes_qp *nesqp = (struct nes_qp *)(unsigned long)context;
3529 nes_terminate_done(nesqp, 1);
3532 /* Set a timer in case hw cannot complete the terminate sequence */
3533 static void nes_terminate_start_timer(struct nes_qp *nesqp)
3535 init_timer(&nesqp->terminate_timer);
3536 nesqp->terminate_timer.function = nes_terminate_timeout;
3537 nesqp->terminate_timer.expires = jiffies + HZ;
3538 nesqp->terminate_timer.data = (unsigned long)nesqp;
3539 add_timer(&nesqp->terminate_timer);
3543 * nes_process_iwarp_aeqe
3545 static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
3546 struct nes_hw_aeqe *aeqe)
3549 unsigned long flags;
3550 struct nes_qp *nesqp;
3551 struct nes_hw_cq *hw_cq;
3552 struct nes_cq *nescq;
3553 int resource_allocated;
3554 struct nes_adapter *nesadapter = nesdev->nesadapter;
3556 u32 next_iwarp_state = 0;
3561 struct ib_event ibevent;
3563 nes_debug(NES_DBG_AEQ, "\n");
3564 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3565 if ((NES_AEQE_INBOUND_RDMA & aeq_info) || (!(NES_AEQE_QP & aeq_info))) {
3566 context = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX]);
3567 context += ((u64)le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX])) << 32;
3569 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
3570 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]) - NES_FIRST_QPN];
3574 /* context is nesqp unless async_event_id == CQ ERROR */
3575 nesqp = (struct nes_qp *)(unsigned long)context;
3576 async_event_id = (u16)aeq_info;
3577 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3578 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3579 nes_debug(NES_DBG_AEQ, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p,"
3580 " Tcp state = %d, iWARP state = %d\n",
3582 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), aeqe,
3583 tcp_state, iwarp_state);
3585 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
3586 if (aeq_info & NES_AEQE_QP) {
3587 if (!nes_is_resource_allocated(nesadapter,
3588 nesadapter->allocated_qps,
3593 switch (async_event_id) {
3594 case NES_AEQE_AEID_LLP_FIN_RECEIVED:
3595 if (nesqp->term_flags)
3596 return; /* Ignore it, wait for close complete */
3598 if (atomic_inc_return(&nesqp->close_timer_started) == 1) {
3599 if ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) &&
3600 (nesqp->ibqp_state == IB_QPS_RTS)) {
3601 spin_lock_irqsave(&nesqp->lock, flags);
3602 nesqp->hw_iwarp_state = iwarp_state;
3603 nesqp->hw_tcp_state = tcp_state;
3604 nesqp->last_aeq = async_event_id;
3605 next_iwarp_state = NES_CQP_QP_IWARP_STATE_CLOSING;
3606 nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_CLOSING;
3607 spin_unlock_irqrestore(&nesqp->lock, flags);
3608 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3609 nes_cm_disconn(nesqp);
3611 nesqp->cm_id->add_ref(nesqp->cm_id);
3612 schedule_nes_timer(nesqp->cm_node, (struct sk_buff *)nesqp,
3613 NES_TIMER_TYPE_CLOSE, 1, 0);
3614 nes_debug(NES_DBG_AEQ, "QP%u Not decrementing QP refcount (%d),"
3615 " need ae to finish up, original_last_aeq = 0x%04X."
3616 " last_aeq = 0x%04X, scheduling timer. TCP state = %d\n",
3617 nesqp->hwqp.qp_id, atomic_read(&nesqp->refcount),
3618 async_event_id, nesqp->last_aeq, tcp_state);
3621 case NES_AEQE_AEID_LLP_CLOSE_COMPLETE:
3622 spin_lock_irqsave(&nesqp->lock, flags);
3623 nesqp->hw_iwarp_state = iwarp_state;
3624 nesqp->hw_tcp_state = tcp_state;
3625 nesqp->last_aeq = async_event_id;
3626 spin_unlock_irqrestore(&nesqp->lock, flags);
3627 nes_cm_disconn(nesqp);
3630 case NES_AEQE_AEID_RESET_SENT:
3631 tcp_state = NES_AEQE_TCP_STATE_CLOSED;
3632 spin_lock_irqsave(&nesqp->lock, flags);
3633 nesqp->hw_iwarp_state = iwarp_state;
3634 nesqp->hw_tcp_state = tcp_state;
3635 nesqp->last_aeq = async_event_id;
3636 nesqp->hte_added = 0;
3637 spin_unlock_irqrestore(&nesqp->lock, flags);
3638 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_DEL_HTE;
3639 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3640 nes_cm_disconn(nesqp);
3643 case NES_AEQE_AEID_LLP_CONNECTION_RESET:
3644 if (atomic_read(&nesqp->close_timer_started))
3646 spin_lock_irqsave(&nesqp->lock, flags);
3647 nesqp->hw_iwarp_state = iwarp_state;
3648 nesqp->hw_tcp_state = tcp_state;
3649 nesqp->last_aeq = async_event_id;
3650 spin_unlock_irqrestore(&nesqp->lock, flags);
3651 nes_cm_disconn(nesqp);
3654 case NES_AEQE_AEID_TERMINATE_SENT:
3655 nes_terminate_send_fin(nesdev, nesqp, aeqe);
3658 case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED:
3659 nes_terminate_received(nesdev, nesqp, aeqe);
3662 case NES_AEQE_AEID_AMP_BAD_STAG_KEY:
3663 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
3664 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
3665 case NES_AEQE_AEID_AMP_INVALID_STAG:
3666 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3667 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3668 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
3669 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
3670 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3671 case NES_AEQE_AEID_AMP_TO_WRAP:
3672 printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_ACCESS_ERR\n",
3673 nesqp->hwqp.qp_id, async_event_id);
3674 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_ACCESS_ERR);
3677 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3678 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
3679 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
3680 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
3681 if (iwarp_opcode(nesqp, aeq_info) > IWARP_OPCODE_TERM) {
3682 aeq_info &= 0xffff0000;
3683 aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE;
3684 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3687 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE:
3688 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES:
3689 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
3690 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
3691 case NES_AEQE_AEID_AMP_BAD_QP:
3692 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
3693 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3694 case NES_AEQE_AEID_DDP_NO_L_BIT:
3695 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3696 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
3697 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
3698 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
3699 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
3700 case NES_AEQE_AEID_AMP_BAD_PD:
3701 case NES_AEQE_AEID_AMP_FASTREG_SHARED:
3702 case NES_AEQE_AEID_AMP_FASTREG_VALID_STAG:
3703 case NES_AEQE_AEID_AMP_FASTREG_MW_STAG:
3704 case NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS:
3705 case NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW:
3706 case NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH:
3707 case NES_AEQE_AEID_AMP_INVALIDATE_SHARED:
3708 case NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS:
3709 case NES_AEQE_AEID_AMP_MWBIND_VALID_STAG:
3710 case NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG:
3711 case NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG:
3712 case NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG:
3713 case NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS:
3714 case NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS:
3715 case NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT:
3716 case NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED:
3717 case NES_AEQE_AEID_BAD_CLOSE:
3718 case NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO:
3719 case NES_AEQE_AEID_STAG_ZERO_INVALID:
3720 case NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST:
3721 case NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
3722 printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_FATAL\n",
3723 nesqp->hwqp.qp_id, async_event_id);
3724 print_ip(nesqp->cm_node);
3725 if (!atomic_read(&nesqp->close_timer_started))
3726 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL);
3729 case NES_AEQE_AEID_CQ_OPERATION_ERROR:
3731 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u, %p\n",
3732 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), (void *)(unsigned long)context);
3733 resource_allocated = nes_is_resource_allocated(nesadapter, nesadapter->allocated_cqs,
3734 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
3735 if (resource_allocated) {
3736 printk(KERN_ERR PFX "%s: Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u\n",
3737 __func__, le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
3738 hw_cq = (struct nes_hw_cq *)(unsigned long)context;
3740 nescq = container_of(hw_cq, struct nes_cq, hw_cq);
3741 if (nescq->ibcq.event_handler) {
3742 ibevent.device = nescq->ibcq.device;
3743 ibevent.event = IB_EVENT_CQ_ERR;
3744 ibevent.element.cq = &nescq->ibcq;
3745 nescq->ibcq.event_handler(&ibevent, nescq->ibcq.cq_context);
3752 nes_debug(NES_DBG_AEQ, "Processing an iWARP related AE for QP, misc = 0x%04X\n",
3760 * nes_iwarp_ce_handler
3762 void nes_iwarp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *hw_cq)
3764 struct nes_cq *nescq = container_of(hw_cq, struct nes_cq, hw_cq);
3766 /* nes_debug(NES_DBG_CQ, "Processing completion event for iWARP CQ%u.\n",
3767 nescq->hw_cq.cq_number); */
3768 nes_write32(nesdev->regs+NES_CQ_ACK, nescq->hw_cq.cq_number);
3770 if (nescq->ibcq.comp_handler)
3771 nescq->ibcq.comp_handler(&nescq->ibcq, nescq->ibcq.cq_context);
3778 * nes_manage_apbvt()
3780 int nes_manage_apbvt(struct nes_vnic *nesvnic, u32 accel_local_port,
3781 u32 nic_index, u32 add_port)
3783 struct nes_device *nesdev = nesvnic->nesdev;
3784 struct nes_hw_cqp_wqe *cqp_wqe;
3785 struct nes_cqp_request *cqp_request;
3789 /* Send manage APBVT request to CQP */
3790 cqp_request = nes_get_cqp_request(nesdev);
3791 if (cqp_request == NULL) {
3792 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3795 cqp_request->waiting = 1;
3796 cqp_wqe = &cqp_request->cqp_wqe;
3798 nes_debug(NES_DBG_QP, "%s APBV for local port=%u(0x%04x), nic_index=%u\n",
3799 (add_port == NES_MANAGE_APBVT_ADD) ? "ADD" : "DEL",
3800 accel_local_port, accel_local_port, nic_index);
3802 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3803 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, (NES_CQP_MANAGE_APBVT |
3804 ((add_port == NES_MANAGE_APBVT_ADD) ? NES_CQP_APBVT_ADD : 0)));
3805 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
3806 ((nic_index << NES_CQP_APBVT_NIC_SHIFT) | accel_local_port));
3808 nes_debug(NES_DBG_QP, "Waiting for CQP completion for APBVT.\n");
3810 atomic_set(&cqp_request->refcount, 2);
3811 nes_post_cqp_request(nesdev, cqp_request);
3813 if (add_port == NES_MANAGE_APBVT_ADD)
3814 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3816 nes_debug(NES_DBG_QP, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
3817 ret, cqp_request->major_code, cqp_request->minor_code);
3818 major_code = cqp_request->major_code;
3820 nes_put_cqp_request(nesdev, cqp_request);
3824 else if (major_code)
3832 * nes_manage_arp_cache
3834 void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
3835 u32 ip_addr, u32 action)
3837 struct nes_hw_cqp_wqe *cqp_wqe;
3838 struct nes_vnic *nesvnic = netdev_priv(netdev);
3839 struct nes_device *nesdev;
3840 struct nes_cqp_request *cqp_request;
3843 nesdev = nesvnic->nesdev;
3844 arp_index = nes_arp_table(nesdev, ip_addr, mac_addr, action);
3845 if (arp_index == -1) {
3849 /* update the ARP entry */
3850 cqp_request = nes_get_cqp_request(nesdev);
3851 if (cqp_request == NULL) {
3852 nes_debug(NES_DBG_NETDEV, "Failed to get a cqp_request.\n");
3855 cqp_request->waiting = 0;
3856 cqp_wqe = &cqp_request->cqp_wqe;
3857 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3859 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
3860 NES_CQP_MANAGE_ARP_CACHE | NES_CQP_ARP_PERM);
3861 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(
3862 (u32)PCI_FUNC(nesdev->pcidev->devfn) << NES_CQP_ARP_AEQ_INDEX_SHIFT);
3863 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(arp_index);
3865 if (action == NES_ARP_ADD) {
3866 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(NES_CQP_ARP_VALID);
3867 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = cpu_to_le32(
3868 (((u32)mac_addr[2]) << 24) | (((u32)mac_addr[3]) << 16) |
3869 (((u32)mac_addr[4]) << 8) | (u32)mac_addr[5]);
3870 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = cpu_to_le32(
3871 (((u32)mac_addr[0]) << 16) | (u32)mac_addr[1]);
3873 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = 0;
3874 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = 0;
3877 nes_debug(NES_DBG_NETDEV, "Not waiting for CQP, cqp.sq_head=%u, cqp.sq_tail=%u\n",
3878 nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
3880 atomic_set(&cqp_request->refcount, 1);
3881 nes_post_cqp_request(nesdev, cqp_request);
3888 void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
3889 u32 which_wq, u32 wait_completion)
3891 struct nes_cqp_request *cqp_request;
3892 struct nes_hw_cqp_wqe *cqp_wqe;
3893 u32 sq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3894 u32 rq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3897 cqp_request = nes_get_cqp_request(nesdev);
3898 if (cqp_request == NULL) {
3899 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3902 if (wait_completion) {
3903 cqp_request->waiting = 1;
3904 atomic_set(&cqp_request->refcount, 2);
3906 cqp_request->waiting = 0;
3908 cqp_wqe = &cqp_request->cqp_wqe;
3909 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3911 /* If wqe in error was identified, set code to be put into cqe */
3912 if ((nesqp->term_sq_flush_code) && (which_wq & NES_CQP_FLUSH_SQ)) {
3913 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3914 sq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_sq_flush_code;
3915 nesqp->term_sq_flush_code = 0;
3918 if ((nesqp->term_rq_flush_code) && (which_wq & NES_CQP_FLUSH_RQ)) {
3919 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3920 rq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_rq_flush_code;
3921 nesqp->term_rq_flush_code = 0;
3924 if (which_wq & NES_CQP_FLUSH_MAJ_MIN) {
3925 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_SQ_CODE] = cpu_to_le32(sq_code);
3926 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_RQ_CODE] = cpu_to_le32(rq_code);
3929 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
3930 cpu_to_le32(NES_CQP_FLUSH_WQES | which_wq);
3931 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesqp->hwqp.qp_id);
3933 nes_post_cqp_request(nesdev, cqp_request);
3935 if (wait_completion) {
3937 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3939 nes_debug(NES_DBG_QP, "Flush SQ QP WQEs completed, ret=%u,"
3940 " CQP Major:Minor codes = 0x%04X:0x%04X\n",
3941 ret, cqp_request->major_code, cqp_request->minor_code);
3942 nes_put_cqp_request(nesdev, cqp_request);