1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
20 * Contact Information:
21 * linux-drivers@emulex.com
25 * Costa Mesa, CA 92626
26 *******************************************************************/
31 #include <linux/mutex.h>
32 #include <linux/list.h>
33 #include <linux/spinlock.h>
34 #include <linux/pci.h>
36 #include <rdma/ib_verbs.h>
37 #include <rdma/ib_user_verbs.h>
40 #include "ocrdma_sli.h"
42 #define OCRDMA_ROCE_DRV_VERSION "10.2.145.0u"
44 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
45 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
47 #define OCRDMA_MAX_AH 512
49 #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
51 struct ocrdma_dev_attr {
73 int max_pages_per_frmr;
78 u8 cq_overflow_detect;
84 u8 local_ca_ack_delay;
94 struct ocrdma_queue_info {
99 u16 entry_size; /* Size of an element in the queue */
100 u16 id; /* qid, where to ring the doorbell. */
106 struct ocrdma_queue_info q;
109 struct ocrdma_dev *dev;
114 struct ocrdma_queue_info sq;
115 struct ocrdma_queue_info cq;
120 struct mutex lock; /* for serializing mailbox commands on MQ */
121 wait_queue_head_t cmd_wait;
128 struct ocrdma_hw_mr {
139 struct ocrdma_pbl *pbl_table;
150 struct ib_umem *umem;
151 struct ocrdma_hw_mr hwmr;
155 struct ib_device ibdev;
156 struct ocrdma_dev_attr attr;
158 struct mutex dev_lock; /* provides syncronise access to device data */
159 spinlock_t flush_q_lock ____cacheline_aligned;
161 struct ocrdma_cq **cq_tbl;
162 struct ocrdma_qp **qp_tbl;
164 struct ocrdma_eq *eq_tbl;
169 union ib_gid *sgid_tbl;
170 /* provided synchronization to sgid table for
171 * updating gid entries triggered by notifier.
173 spinlock_t sgid_lock;
176 struct ocrdma_cq *gsi_sqcq;
177 struct ocrdma_cq *gsi_rqcq;
180 struct ocrdma_av *va;
184 /* provide synchronization for av
189 struct ocrdma_pbl pbl;
194 struct mqe_ctx mqe_ctx;
196 struct be_dev_info nic_info;
198 struct list_head entry;
201 struct ocrdma_mr *stag_arr[OCRDMA_MAX_STAG];
208 struct ocrdma_cqe *va;
210 u32 getp; /* pointer to pending wrs to
211 * return to stack, wrap arounds
216 bool deferred_arm, deferred_sol;
219 spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
222 /* syncronizes cq completion handler invoked from multiple context */
223 spinlock_t comp_handler_lock ____cacheline_aligned;
227 struct ocrdma_ucontext *ucontext;
232 /* head of all qp's sq and rq for which cqes need to be flushed
235 struct list_head sq_head, rq_head;
240 struct ocrdma_dev *dev;
241 struct ocrdma_ucontext *uctx;
250 struct ocrdma_av *av;
255 struct ocrdma_qp_hwq_info {
256 u8 *va; /* virtual address */
262 u16 dbid; /* qid, where to ring the doorbell. */
270 struct ocrdma_qp_hwq_info rq;
275 /* provide synchronization to multiple context(s) posting rqe */
276 spinlock_t q_lock ____cacheline_aligned;
278 struct ocrdma_pd *pd;
284 struct ocrdma_dev *dev;
287 struct ocrdma_qp_hwq_info sq;
290 uint16_t dpp_wqe_idx;
297 /* provide synchronization to multiple context(s) posting wqe, rqe */
298 spinlock_t q_lock ____cacheline_aligned;
299 struct ocrdma_cq *sq_cq;
300 /* list maintained per CQ to flush SQ errors */
301 struct list_head sq_entry;
304 struct ocrdma_qp_hwq_info rq;
306 struct ocrdma_cq *rq_cq;
307 struct ocrdma_srq *srq;
308 /* list maintained per CQ to flush RQ errors */
309 struct list_head rq_entry;
311 enum ocrdma_qp_state state; /* QP state */
313 u32 max_ord, max_ird;
316 struct ocrdma_pd *pd;
318 enum ib_qp_type qp_type;
329 struct ocrdma_ucontext {
330 struct ib_ucontext ibucontext;
332 struct list_head mm_head;
333 struct mutex mm_list_lock; /* protects list entries of mm type */
334 struct ocrdma_pd *cntxt_pd;
349 struct list_head entry;
352 static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev)
354 return container_of(ibdev, struct ocrdma_dev, ibdev);
357 static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext
360 return container_of(ibucontext, struct ocrdma_ucontext, ibucontext);
363 static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd)
365 return container_of(ibpd, struct ocrdma_pd, ibpd);
368 static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq)
370 return container_of(ibcq, struct ocrdma_cq, ibcq);
373 static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp)
375 return container_of(ibqp, struct ocrdma_qp, ibqp);
378 static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr)
380 return container_of(ibmr, struct ocrdma_mr, ibmr);
383 static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah)
385 return container_of(ibah, struct ocrdma_ah, ibah);
388 static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq)
390 return container_of(ibsrq, struct ocrdma_srq, ibsrq);
393 static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe)
396 cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID;
397 return (cqe_valid == cq->phase);
400 static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe)
402 return (le32_to_cpu(cqe->flags_status_srcqpn) &
403 OCRDMA_CQE_QTYPE) ? 0 : 1;
406 static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe)
408 return (le32_to_cpu(cqe->flags_status_srcqpn) &
409 OCRDMA_CQE_INVALIDATE) ? 1 : 0;
412 static inline int is_cqe_imm(struct ocrdma_cqe *cqe)
414 return (le32_to_cpu(cqe->flags_status_srcqpn) &
415 OCRDMA_CQE_IMM) ? 1 : 0;
418 static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe)
420 return (le32_to_cpu(cqe->flags_status_srcqpn) &
421 OCRDMA_CQE_WRITE_IMM) ? 1 : 0;
424 static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev,
425 struct ib_ah_attr *ah_attr, u8 *mac_addr)
429 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
430 if (rdma_is_multicast_addr(&in6))
431 rdma_get_mcast_mac(&in6, mac_addr);
433 memcpy(mac_addr, ah_attr->dmac, ETH_ALEN);
437 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev,
442 for (indx = 0; indx < dev->eq_cnt; indx++) {
443 if (dev->eq_tbl[indx].q.id == eqid)
450 static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
452 if (dev->nic_info.dev_family == 0xF && !dev->asic_id) {
453 pci_read_config_dword(
455 OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id);
458 return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >>
459 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;