drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35
  36 #include "ocrdma.h"
  37 #include "ocrdma_hw.h"
  38 #include "ocrdma_verbs.h"
  39 #include "ocrdma_ah.h"
  40
  41 enum mbx_status {
  42         OCRDMA_MBX_STATUS_FAILED                = 1,
  43         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  44         OCRDMA_MBX_STATUS_OOR                   = 100,
  45         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  46         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  47         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  48         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  49         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  50         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  51         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  52         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  53         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  54         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  55         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  56         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  57         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  58         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  59         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  60         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  61         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  62         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  63         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  64         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  66         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  67         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  68         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  69         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  70         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  71         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  72         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  73         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  74         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  75         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  76         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  77         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  78         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  80 };
  81
  82 enum additional_status {
  83         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  84 };
  85
  86 enum cqe_status {
  87         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  88         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  89         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  90         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  91         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  92 };
  93
  94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  95 {
  96         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  97 }
  98
  99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 100 {
 101         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 102 }
 103
 104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 105 {
 106         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 107             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 108
 109         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 110                 return NULL;
 111         return cqe;
 112 }
 113
 114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 115 {
 116         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 117 }
 118
 119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 120 {
 121         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 122 }
 123
 124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 125 {
 126         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 127 }
 128
 129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 130 {
 131         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 132 }
 133
 134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 135 {
 136         switch (qps) {
 137         case OCRDMA_QPS_RST:
 138                 return IB_QPS_RESET;
 139         case OCRDMA_QPS_INIT:
 140                 return IB_QPS_INIT;
 141         case OCRDMA_QPS_RTR:
 142                 return IB_QPS_RTR;
 143         case OCRDMA_QPS_RTS:
 144                 return IB_QPS_RTS;
 145         case OCRDMA_QPS_SQD:
 146         case OCRDMA_QPS_SQ_DRAINING:
 147                 return IB_QPS_SQD;
 148         case OCRDMA_QPS_SQE:
 149                 return IB_QPS_SQE;
 150         case OCRDMA_QPS_ERR:
 151                 return IB_QPS_ERR;
 152         }
 153         return IB_QPS_ERR;
 154 }
 155
 156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 157 {
 158         switch (qps) {
 159         case IB_QPS_RESET:
 160                 return OCRDMA_QPS_RST;
 161         case IB_QPS_INIT:
 162                 return OCRDMA_QPS_INIT;
 163         case IB_QPS_RTR:
 164                 return OCRDMA_QPS_RTR;
 165         case IB_QPS_RTS:
 166                 return OCRDMA_QPS_RTS;
 167         case IB_QPS_SQD:
 168                 return OCRDMA_QPS_SQD;
 169         case IB_QPS_SQE:
 170                 return OCRDMA_QPS_SQE;
 171         case IB_QPS_ERR:
 172                 return OCRDMA_QPS_ERR;
 173         }
 174         return OCRDMA_QPS_ERR;
 175 }
 176
 177 static int ocrdma_get_mbx_errno(u32 status)
 178 {
 179         int err_num;
 180         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 181                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 182         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 183                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 184
 185         switch (mbox_status) {
 186         case OCRDMA_MBX_STATUS_OOR:
 187         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 188                 err_num = -EAGAIN;
 189                 break;
 190
 191         case OCRDMA_MBX_STATUS_INVALID_PD:
 192         case OCRDMA_MBX_STATUS_INVALID_CQ:
 193         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 194         case OCRDMA_MBX_STATUS_INVALID_QP:
 195         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 196         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 197         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 198         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 200         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 201         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 202         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 203         case OCRDMA_MBX_STATUS_INVALID_VA:
 204         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 205         case OCRDMA_MBX_STATUS_INVALID_FBO:
 206         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 207         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 208         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 209         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 210         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 211                 err_num = -EINVAL;
 212                 break;
 213
 214         case OCRDMA_MBX_STATUS_PD_INUSE:
 215         case OCRDMA_MBX_STATUS_QP_BOUND:
 216         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_BOUND:
 218                 err_num = -EBUSY;
 219                 break;
 220
 221         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 222         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 230                 err_num = -ENOBUFS;
 231                 break;
 232
 233         case OCRDMA_MBX_STATUS_FAILED:
 234                 switch (add_status) {
 235                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 236                         err_num = -EAGAIN;
 237                         break;
 238                 }
 239         default:
 240                 err_num = -EFAULT;
 241         }
 242         return err_num;
 243 }
 244
 245 char *port_speed_string(struct ocrdma_dev *dev)
 246 {
 247         char *str = "";
 248         u16 speeds_supported;
 249
 250         speeds_supported = dev->phy.fixed_speeds_supported |
 251                                 dev->phy.auto_speeds_supported;
 252         if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
 253                 str = "40Gbps ";
 254         else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
 255                 str = "10Gbps ";
 256         else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
 257                 str = "1Gbps ";
 258
 259         return str;
 260 }
 261
 262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 263 {
 264         int err_num = -EINVAL;
 265
 266         switch (cqe_status) {
 267         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 268                 err_num = -EPERM;
 269                 break;
 270         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 271                 err_num = -EINVAL;
 272                 break;
 273         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 274         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 275                 err_num = -EINVAL;
 276                 break;
 277         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 278         default:
 279                 err_num = -EINVAL;
 280                 break;
 281         }
 282         return err_num;
 283 }
 284
 285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 286                        bool solicited, u16 cqe_popped)
 287 {
 288         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 289
 290         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 291              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 292
 293         if (armed)
 294                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 295         if (solicited)
 296                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 297         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 298         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 299 }
 300
 301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 302 {
 303         u32 val = 0;
 304
 305         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 306         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 308 }
 309
 310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 311                               bool arm, bool clear_int, u16 num_eqe)
 312 {
 313         u32 val = 0;
 314
 315         val |= eq_id & OCRDMA_EQ_ID_MASK;
 316         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 317         if (arm)
 318                 val |= (1 << OCRDMA_REARM_SHIFT);
 319         if (clear_int)
 320                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 321         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 322         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 323         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 324 }
 325
 326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 327                             u8 opcode, u8 subsys, u32 cmd_len)
 328 {
 329         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 330         cmd_hdr->timeout = 20; /* seconds */
 331         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 332 }
 333
 334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 335 {
 336         struct ocrdma_mqe *mqe;
 337
 338         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 339         if (!mqe)
 340                 return NULL;
 341         mqe->hdr.spcl_sge_cnt_emb |=
 342                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 343                                         OCRDMA_MQE_HDR_EMB_MASK;
 344         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 345
 346         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 347                         mqe->hdr.pyld_len);
 348         return mqe;
 349 }
 350
 351 static void *ocrdma_alloc_mqe(void)
 352 {
 353         return kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 354 }
 355
 356 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 357 {
 358         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 359 }
 360
 361 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 362                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 363 {
 364         memset(q, 0, sizeof(*q));
 365         q->len = len;
 366         q->entry_size = entry_size;
 367         q->size = len * entry_size;
 368         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 369                                    &q->dma, GFP_KERNEL);
 370         if (!q->va)
 371                 return -ENOMEM;
 372         memset(q->va, 0, q->size);
 373         return 0;
 374 }
 375
 376 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 377                                         dma_addr_t host_pa, int hw_page_size)
 378 {
 379         int i;
 380
 381         for (i = 0; i < cnt; i++) {
 382                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 383                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 384                 host_pa += hw_page_size;
 385         }
 386 }
 387
 388 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
 389                                struct ocrdma_queue_info *q, int queue_type)
 390 {
 391         u8 opcode = 0;
 392         int status;
 393         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 394
 395         switch (queue_type) {
 396         case QTYPE_MCCQ:
 397                 opcode = OCRDMA_CMD_DELETE_MQ;
 398                 break;
 399         case QTYPE_CQ:
 400                 opcode = OCRDMA_CMD_DELETE_CQ;
 401                 break;
 402         case QTYPE_EQ:
 403                 opcode = OCRDMA_CMD_DELETE_EQ;
 404                 break;
 405         default:
 406                 BUG();
 407         }
 408         memset(cmd, 0, sizeof(*cmd));
 409         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 410         cmd->id = q->id;
 411
 412         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 413                                  cmd, sizeof(*cmd), NULL, NULL);
 414         if (!status)
 415                 q->created = false;
 416         return status;
 417 }
 418
 419 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 420 {
 421         int status;
 422         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 423         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 424
 425         memset(cmd, 0, sizeof(*cmd));
 426         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 427                         sizeof(*cmd));
 428
 429         cmd->req.rsvd_version = 2;
 430         cmd->num_pages = 4;
 431         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 432         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 433
 434         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 435                              PAGE_SIZE_4K);
 436         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 437                                  NULL);
 438         if (!status) {
 439                 eq->q.id = rsp->vector_eqid & 0xffff;
 440                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 441                 eq->q.created = true;
 442         }
 443         return status;
 444 }
 445
 446 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 447                             struct ocrdma_eq *eq, u16 q_len)
 448 {
 449         int status;
 450
 451         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 452                                 sizeof(struct ocrdma_eqe));
 453         if (status)
 454                 return status;
 455
 456         status = ocrdma_mbx_create_eq(dev, eq);
 457         if (status)
 458                 goto mbx_err;
 459         eq->dev = dev;
 460         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 461
 462         return 0;
 463 mbx_err:
 464         ocrdma_free_q(dev, &eq->q);
 465         return status;
 466 }
 467
 468 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 469 {
 470         int irq;
 471
 472         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 473                 irq = dev->nic_info.pdev->irq;
 474         else
 475                 irq = dev->nic_info.msix.vector_list[eq->vector];
 476         return irq;
 477 }
 478
 479 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 480 {
 481         if (eq->q.created) {
 482                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 483                 ocrdma_free_q(dev, &eq->q);
 484         }
 485 }
 486
 487 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 488 {
 489         int irq;
 490
 491         /* disarm EQ so that interrupts are not generated
 492          * during freeing and EQ delete is in progress.
 493          */
 494         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 495
 496         irq = ocrdma_get_irq(dev, eq);
 497         free_irq(irq, eq);
 498         _ocrdma_destroy_eq(dev, eq);
 499 }
 500
 501 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 502 {
 503         int i;
 504
 505         for (i = 0; i < dev->eq_cnt; i++)
 506                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 507 }
 508
 509 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 510                                    struct ocrdma_queue_info *cq,
 511                                    struct ocrdma_queue_info *eq)
 512 {
 513         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 514         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 515         int status;
 516
 517         memset(cmd, 0, sizeof(*cmd));
 518         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 519                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 520
 521         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 522         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 523                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 524         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 525
 526         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 527         cmd->eqn = eq->id;
 528         cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
 529
 530         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 531                              cq->dma, PAGE_SIZE_4K);
 532         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 533                                  cmd, sizeof(*cmd), NULL, NULL);
 534         if (!status) {
 535                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 536                 cq->created = true;
 537         }
 538         return status;
 539 }
 540
 541 static u32 ocrdma_encoded_q_len(int q_len)
 542 {
 543         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 544
 545         if (len_encoded == 16)
 546                 len_encoded = 0;
 547         return len_encoded;
 548 }
 549
 550 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 551                                 struct ocrdma_queue_info *mq,
 552                                 struct ocrdma_queue_info *cq)
 553 {
 554         int num_pages, status;
 555         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 556         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 557         struct ocrdma_pa *pa;
 558
 559         memset(cmd, 0, sizeof(*cmd));
 560         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 561
 562         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 563                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 564         cmd->req.rsvd_version = 1;
 565         cmd->cqid_pages = num_pages;
 566         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 567         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 568
 569         cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
 570         cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
 571
 572         cmd->async_cqid_ringsize = cq->id;
 573         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 574                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 575         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 576         pa = &cmd->pa[0];
 577
 578         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 579         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 580                                  cmd, sizeof(*cmd), NULL, NULL);
 581         if (!status) {
 582                 mq->id = rsp->id;
 583                 mq->created = true;
 584         }
 585         return status;
 586 }
 587
 588 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 589 {
 590         int status;
 591
 592         /* Alloc completion queue for Mailbox queue */
 593         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 594                                 sizeof(struct ocrdma_mcqe));
 595         if (status)
 596                 goto alloc_err;
 597
 598         dev->eq_tbl[0].cq_cnt++;
 599         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 600         if (status)
 601                 goto mbx_cq_free;
 602
 603         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 604         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 605         mutex_init(&dev->mqe_ctx.lock);
 606
 607         /* Alloc Mailbox queue */
 608         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 609                                 sizeof(struct ocrdma_mqe));
 610         if (status)
 611                 goto mbx_cq_destroy;
 612         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 613         if (status)
 614                 goto mbx_q_free;
 615         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 616         return 0;
 617
 618 mbx_q_free:
 619         ocrdma_free_q(dev, &dev->mq.sq);
 620 mbx_cq_destroy:
 621         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 622 mbx_cq_free:
 623         ocrdma_free_q(dev, &dev->mq.cq);
 624 alloc_err:
 625         return status;
 626 }
 627
 628 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 629 {
 630         struct ocrdma_queue_info *mbxq, *cq;
 631
 632         /* mqe_ctx lock synchronizes with any other pending cmds. */
 633         mutex_lock(&dev->mqe_ctx.lock);
 634         mbxq = &dev->mq.sq;
 635         if (mbxq->created) {
 636                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 637                 ocrdma_free_q(dev, mbxq);
 638         }
 639         mutex_unlock(&dev->mqe_ctx.lock);
 640
 641         cq = &dev->mq.cq;
 642         if (cq->created) {
 643                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 644                 ocrdma_free_q(dev, cq);
 645         }
 646 }
 647
 648 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 649                                        struct ocrdma_qp *qp)
 650 {
 651         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 652         enum ib_qp_state old_ib_qps;
 653
 654         if (qp == NULL)
 655                 BUG();
 656         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 657 }
 658
 659 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 660                                     struct ocrdma_ae_mcqe *cqe)
 661 {
 662         struct ocrdma_qp *qp = NULL;
 663         struct ocrdma_cq *cq = NULL;
 664         struct ib_event ib_evt;
 665         int cq_event = 0;
 666         int qp_event = 1;
 667         int srq_event = 0;
 668         int dev_event = 0;
 669         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 670             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 671
 672         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 673                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 674         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 675                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 676
 677         memset(&ib_evt, 0, sizeof(ib_evt));
 678
 679         ib_evt.device = &dev->ibdev;
 680
 681         switch (type) {
 682         case OCRDMA_CQ_ERROR:
 683                 ib_evt.element.cq = &cq->ibcq;
 684                 ib_evt.event = IB_EVENT_CQ_ERR;
 685                 cq_event = 1;
 686                 qp_event = 0;
 687                 break;
 688         case OCRDMA_CQ_OVERRUN_ERROR:
 689                 ib_evt.element.cq = &cq->ibcq;
 690                 ib_evt.event = IB_EVENT_CQ_ERR;
 691                 cq_event = 1;
 692                 qp_event = 0;
 693                 break;
 694         case OCRDMA_CQ_QPCAT_ERROR:
 695                 ib_evt.element.qp = &qp->ibqp;
 696                 ib_evt.event = IB_EVENT_QP_FATAL;
 697                 ocrdma_process_qpcat_error(dev, qp);
 698                 break;
 699         case OCRDMA_QP_ACCESS_ERROR:
 700                 ib_evt.element.qp = &qp->ibqp;
 701                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 702                 break;
 703         case OCRDMA_QP_COMM_EST_EVENT:
 704                 ib_evt.element.qp = &qp->ibqp;
 705                 ib_evt.event = IB_EVENT_COMM_EST;
 706                 break;
 707         case OCRDMA_SQ_DRAINED_EVENT:
 708                 ib_evt.element.qp = &qp->ibqp;
 709                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 710                 break;
 711         case OCRDMA_DEVICE_FATAL_EVENT:
 712                 ib_evt.element.port_num = 1;
 713                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 714                 qp_event = 0;
 715                 dev_event = 1;
 716                 break;
 717         case OCRDMA_SRQCAT_ERROR:
 718                 ib_evt.element.srq = &qp->srq->ibsrq;
 719                 ib_evt.event = IB_EVENT_SRQ_ERR;
 720                 srq_event = 1;
 721                 qp_event = 0;
 722                 break;
 723         case OCRDMA_SRQ_LIMIT_EVENT:
 724                 ib_evt.element.srq = &qp->srq->ibsrq;
 725                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 726                 srq_event = 1;
 727                 qp_event = 0;
 728                 break;
 729         case OCRDMA_QP_LAST_WQE_EVENT:
 730                 ib_evt.element.qp = &qp->ibqp;
 731                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 732                 break;
 733         default:
 734                 cq_event = 0;
 735                 qp_event = 0;
 736                 srq_event = 0;
 737                 dev_event = 0;
 738                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 739                 break;
 740         }
 741
 742         if (qp_event) {
 743                 if (qp->ibqp.event_handler)
 744                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 745         } else if (cq_event) {
 746                 if (cq->ibcq.event_handler)
 747                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 748         } else if (srq_event) {
 749                 if (qp->srq->ibsrq.event_handler)
 750                         qp->srq->ibsrq.event_handler(&ib_evt,
 751                                                      qp->srq->ibsrq.
 752                                                      srq_context);
 753         } else if (dev_event) {
 754                 pr_err("%s: Fatal event received\n", dev->ibdev.name);
 755                 ib_dispatch_event(&ib_evt);
 756         }
 757
 758 }
 759
 760 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 761                                         struct ocrdma_ae_mcqe *cqe)
 762 {
 763         struct ocrdma_ae_pvid_mcqe *evt;
 764         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 765                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 766
 767         switch (type) {
 768         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 769                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 770                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 771                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 772                         dev->pvid = ((evt->tag_enabled &
 773                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 774                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 775                 break;
 776
 777         case OCRDMA_ASYNC_EVENT_COS_VALUE:
 778                 atomic_set(&dev->update_sl, 1);
 779                 break;
 780         default:
 781                 /* Not interested evts. */
 782                 break;
 783         }
 784 }
 785
 786 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 787 {
 788         /* async CQE processing */
 789         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 790         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 791                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 792
 793         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 794                 ocrdma_dispatch_ibevent(dev, cqe);
 795         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 796                 ocrdma_process_grp5_aync(dev, cqe);
 797         else
 798                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 799                        dev->id, evt_code);
 800 }
 801
 802 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 803 {
 804         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 805                 dev->mqe_ctx.cqe_status = (cqe->status &
 806                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 807                 dev->mqe_ctx.ext_status =
 808                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 809                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 810                 dev->mqe_ctx.cmd_done = true;
 811                 wake_up(&dev->mqe_ctx.cmd_wait);
 812         } else
 813                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 814                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 815 }
 816
 817 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 818 {
 819         u16 cqe_popped = 0;
 820         struct ocrdma_mcqe *cqe;
 821
 822         while (1) {
 823                 cqe = ocrdma_get_mcqe(dev);
 824                 if (cqe == NULL)
 825                         break;
 826                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 827                 cqe_popped += 1;
 828                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 829                         ocrdma_process_acqe(dev, cqe);
 830                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 831                         ocrdma_process_mcqe(dev, cqe);
 832                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 833                 ocrdma_mcq_inc_tail(dev);
 834         }
 835         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 836         return 0;
 837 }
 838
 839 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 840                                        struct ocrdma_cq *cq)
 841 {
 842         unsigned long flags;
 843         struct ocrdma_qp *qp;
 844         bool buddy_cq_found = false;
 845         /* Go through list of QPs in error state which are using this CQ
 846          * and invoke its callback handler to trigger CQE processing for
 847          * error/flushed CQE. It is rare to find more than few entries in
 848          * this list as most consumers stops after getting error CQE.
 849          * List is traversed only once when a matching buddy cq found for a QP.
 850          */
 851         spin_lock_irqsave(&dev->flush_q_lock, flags);
 852         list_for_each_entry(qp, &cq->sq_head, sq_entry) {
 853                 if (qp->srq)
 854                         continue;
 855                 /* if wq and rq share the same cq, than comp_handler
 856                  * is already invoked.
 857                  */
 858                 if (qp->sq_cq == qp->rq_cq)
 859                         continue;
 860                 /* if completion came on sq, rq's cq is buddy cq.
 861                  * if completion came on rq, sq's cq is buddy cq.
 862                  */
 863                 if (qp->sq_cq == cq)
 864                         cq = qp->rq_cq;
 865                 else
 866                         cq = qp->sq_cq;
 867                 buddy_cq_found = true;
 868                 break;
 869         }
 870         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 871         if (buddy_cq_found == false)
 872                 return;
 873         if (cq->ibcq.comp_handler) {
 874                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 875                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 876                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 877         }
 878 }
 879
 880 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 881 {
 882         unsigned long flags;
 883         struct ocrdma_cq *cq;
 884
 885         if (cq_idx >= OCRDMA_MAX_CQ)
 886                 BUG();
 887
 888         cq = dev->cq_tbl[cq_idx];
 889         if (cq == NULL)
 890                 return;
 891
 892         if (cq->ibcq.comp_handler) {
 893                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 894                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 895                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 896         }
 897         ocrdma_qp_buddy_cq_handler(dev, cq);
 898 }
 899
 900 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 901 {
 902         /* process the MQ-CQE. */
 903         if (cq_id == dev->mq.cq.id)
 904                 ocrdma_mq_cq_handler(dev, cq_id);
 905         else
 906                 ocrdma_qp_cq_handler(dev, cq_id);
 907 }
 908
 909 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 910 {
 911         struct ocrdma_eq *eq = handle;
 912         struct ocrdma_dev *dev = eq->dev;
 913         struct ocrdma_eqe eqe;
 914         struct ocrdma_eqe *ptr;
 915         u16 cq_id;
 916         int budget = eq->cq_cnt;
 917
 918         do {
 919                 ptr = ocrdma_get_eqe(eq);
 920                 eqe = *ptr;
 921                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 922                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 923                         break;
 924
 925                 ptr->id_valid = 0;
 926                 /* ring eq doorbell as soon as its consumed. */
 927                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 928                 /* check whether its CQE or not. */
 929                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 930                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 931                         ocrdma_cq_handler(dev, cq_id);
 932                 }
 933                 ocrdma_eq_inc_tail(eq);
 934
 935                 /* There can be a stale EQE after the last bound CQ is
 936                  * destroyed. EQE valid and budget == 0 implies this.
 937                  */
 938                 if (budget)
 939                         budget--;
 940
 941         } while (budget);
 942
 943         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 944         return IRQ_HANDLED;
 945 }
 946
 947 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 948 {
 949         struct ocrdma_mqe *mqe;
 950
 951         dev->mqe_ctx.tag = dev->mq.sq.head;
 952         dev->mqe_ctx.cmd_done = false;
 953         mqe = ocrdma_get_mqe(dev);
 954         cmd->hdr.tag_lo = dev->mq.sq.head;
 955         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 956         /* make sure descriptor is written before ringing doorbell */
 957         wmb();
 958         ocrdma_mq_inc_head(dev);
 959         ocrdma_ring_mq_db(dev);
 960 }
 961
 962 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 963 {
 964         long status;
 965         /* 30 sec timeout */
 966         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 967                                     (dev->mqe_ctx.cmd_done != false),
 968                                     msecs_to_jiffies(30000));
 969         if (status)
 970                 return 0;
 971         else {
 972                 dev->mqe_ctx.fw_error_state = true;
 973                 pr_err("%s(%d) mailbox timeout: fw not responding\n",
 974                        __func__, dev->id);
 975                 return -1;
 976         }
 977 }
 978
 979 /* issue a mailbox command on the MQ */
 980 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
 981 {
 982         int status = 0;
 983         u16 cqe_status, ext_status;
 984         struct ocrdma_mqe *rsp_mqe;
 985         struct ocrdma_mbx_rsp *rsp = NULL;
 986
 987         mutex_lock(&dev->mqe_ctx.lock);
 988         if (dev->mqe_ctx.fw_error_state)
 989                 goto mbx_err;
 990         ocrdma_post_mqe(dev, mqe);
 991         status = ocrdma_wait_mqe_cmpl(dev);
 992         if (status)
 993                 goto mbx_err;
 994         cqe_status = dev->mqe_ctx.cqe_status;
 995         ext_status = dev->mqe_ctx.ext_status;
 996         rsp_mqe = ocrdma_get_mqe_rsp(dev);
 997         ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
 998         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
 999                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1000                 rsp = &mqe->u.rsp;
1001
1002         if (cqe_status || ext_status) {
1003                 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1004                        __func__, cqe_status, ext_status);
1005                 if (rsp) {
1006                         /* This is for embedded cmds. */
1007                         pr_err("opcode=0x%x, subsystem=0x%x\n",
1008                                (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1009                                 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1010                                 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1011                                 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1012                 }
1013                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1014                 goto mbx_err;
1015         }
1016         /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1017         if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1018                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1019 mbx_err:
1020         mutex_unlock(&dev->mqe_ctx.lock);
1021         return status;
1022 }
1023
1024 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1025                                  void *payload_va)
1026 {
1027         int status = 0;
1028         struct ocrdma_mbx_rsp *rsp = payload_va;
1029
1030         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1031                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1032                 BUG();
1033
1034         status = ocrdma_mbx_cmd(dev, mqe);
1035         if (!status)
1036                 /* For non embedded, only CQE failures are handled in
1037                  * ocrdma_mbx_cmd. We need to check for RSP errors.
1038                  */
1039                 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1040                         status = ocrdma_get_mbx_errno(rsp->status);
1041
1042         if (status)
1043                 pr_err("opcode=0x%x, subsystem=0x%x\n",
1044                        (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1045                         OCRDMA_MBX_RSP_OPCODE_SHIFT,
1046                         (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1047                         OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1048         return status;
1049 }
1050
1051 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1052                               struct ocrdma_dev_attr *attr,
1053                               struct ocrdma_mbx_query_config *rsp)
1054 {
1055         attr->max_pd =
1056             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1057             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1058         attr->max_qp =
1059             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1060             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1061         attr->max_srq =
1062                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1063                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1064         attr->max_send_sge = ((rsp->max_write_send_sge &
1065                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1066                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1067         attr->max_recv_sge = (rsp->max_write_send_sge &
1068                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1069             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1070         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1071                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1072             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1073         attr->max_rdma_sge = (rsp->max_write_send_sge &
1074                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1075             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1076         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1077                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1078             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1079         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1080                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1081             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1082         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1083                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1084             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1085         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1086                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1087             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1088         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1089                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1090             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1091         attr->max_mw = rsp->max_mw;
1092         attr->max_mr = rsp->max_mr;
1093         attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1094                               rsp->max_mr_size_lo;
1095         attr->max_fmr = 0;
1096         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1097         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1098         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1099                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1100         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1101                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1102                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1103         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1104                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1105                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1106                 OCRDMA_WQE_STRIDE;
1107         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1108                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1109                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1110                 OCRDMA_WQE_STRIDE;
1111         attr->max_inline_data =
1112             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1113                               sizeof(struct ocrdma_sge));
1114         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1115                 attr->ird = 1;
1116                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1117                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1118         }
1119         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1120                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1121         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1122                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1123 }
1124
1125 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1126                                    struct ocrdma_fw_conf_rsp *conf)
1127 {
1128         u32 fn_mode;
1129
1130         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1131         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1132                 return -EINVAL;
1133         dev->base_eqid = conf->base_eqid;
1134         dev->max_eq = conf->max_eq;
1135         return 0;
1136 }
1137
1138 /* can be issued only during init time. */
1139 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1140 {
1141         int status = -ENOMEM;
1142         struct ocrdma_mqe *cmd;
1143         struct ocrdma_fw_ver_rsp *rsp;
1144
1145         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1146         if (!cmd)
1147                 return -ENOMEM;
1148         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1149                         OCRDMA_CMD_GET_FW_VER,
1150                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1151
1152         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1153         if (status)
1154                 goto mbx_err;
1155         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1156         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1157         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1158                sizeof(rsp->running_ver));
1159         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1160 mbx_err:
1161         kfree(cmd);
1162         return status;
1163 }
1164
1165 /* can be issued only during init time. */
1166 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1167 {
1168         int status = -ENOMEM;
1169         struct ocrdma_mqe *cmd;
1170         struct ocrdma_fw_conf_rsp *rsp;
1171
1172         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1173         if (!cmd)
1174                 return -ENOMEM;
1175         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1176                         OCRDMA_CMD_GET_FW_CONFIG,
1177                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1178         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1179         if (status)
1180                 goto mbx_err;
1181         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1182         status = ocrdma_check_fw_config(dev, rsp);
1183 mbx_err:
1184         kfree(cmd);
1185         return status;
1186 }
1187
1188 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1189 {
1190         struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1191         struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1192         struct ocrdma_rdma_stats_resp *old_stats = NULL;
1193         int status;
1194
1195         old_stats = kzalloc(sizeof(*old_stats), GFP_KERNEL);
1196         if (old_stats == NULL)
1197                 return -ENOMEM;
1198
1199         memset(mqe, 0, sizeof(*mqe));
1200         mqe->hdr.pyld_len = dev->stats_mem.size;
1201         mqe->hdr.spcl_sge_cnt_emb |=
1202                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1203                                 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1204         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1205         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1206         mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1207
1208         /* Cache the old stats */
1209         memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1210         memset(req, 0, dev->stats_mem.size);
1211
1212         ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1213                         OCRDMA_CMD_GET_RDMA_STATS,
1214                         OCRDMA_SUBSYS_ROCE,
1215                         dev->stats_mem.size);
1216         if (reset)
1217                 req->reset_stats = reset;
1218
1219         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1220         if (status)
1221                 /* Copy from cache, if mbox fails */
1222                 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1223         else
1224                 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1225
1226         kfree(old_stats);
1227         return status;
1228 }
1229
1230 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1231 {
1232         int status = -ENOMEM;
1233         struct ocrdma_dma_mem dma;
1234         struct ocrdma_mqe *mqe;
1235         struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1236         struct mgmt_hba_attribs *hba_attribs;
1237
1238         mqe = ocrdma_alloc_mqe();
1239         if (!mqe)
1240                 return status;
1241         memset(mqe, 0, sizeof(*mqe));
1242
1243         dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1244         dma.va   = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1245                                         dma.size, &dma.pa, GFP_KERNEL);
1246         if (!dma.va)
1247                 goto free_mqe;
1248
1249         mqe->hdr.pyld_len = dma.size;
1250         mqe->hdr.spcl_sge_cnt_emb |=
1251                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1252                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
1253         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1254         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1255         mqe->u.nonemb_req.sge[0].len = dma.size;
1256
1257         memset(dma.va, 0, dma.size);
1258         ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1259                         OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1260                         OCRDMA_SUBSYS_COMMON,
1261                         dma.size);
1262
1263         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1264         if (!status) {
1265                 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1266                 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1267
1268                 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1269                                         OCRDMA_HBA_ATTRB_PTNUM_MASK)
1270                                         >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1271                 strncpy(dev->model_number,
1272                         hba_attribs->controller_model_number, 31);
1273         }
1274         dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1275 free_mqe:
1276         kfree(mqe);
1277         return status;
1278 }
1279
1280 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1281 {
1282         int status = -ENOMEM;
1283         struct ocrdma_mbx_query_config *rsp;
1284         struct ocrdma_mqe *cmd;
1285
1286         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1287         if (!cmd)
1288                 return status;
1289         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1290         if (status)
1291                 goto mbx_err;
1292         rsp = (struct ocrdma_mbx_query_config *)cmd;
1293         ocrdma_get_attr(dev, &dev->attr, rsp);
1294 mbx_err:
1295         kfree(cmd);
1296         return status;
1297 }
1298
1299 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1300 {
1301         int status = -ENOMEM;
1302         struct ocrdma_get_link_speed_rsp *rsp;
1303         struct ocrdma_mqe *cmd;
1304
1305         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1306                                   sizeof(*cmd));
1307         if (!cmd)
1308                 return status;
1309         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1310                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1311                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1312
1313         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1314
1315         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1316         if (status)
1317                 goto mbx_err;
1318
1319         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1320         *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1321                         >> OCRDMA_PHY_PS_SHIFT;
1322
1323 mbx_err:
1324         kfree(cmd);
1325         return status;
1326 }
1327
1328 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1329 {
1330         int status = -ENOMEM;
1331         struct ocrdma_mqe *cmd;
1332         struct ocrdma_get_phy_info_rsp *rsp;
1333
1334         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1335         if (!cmd)
1336                 return status;
1337
1338         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1339                         OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1340                         sizeof(*cmd));
1341
1342         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1343         if (status)
1344                 goto mbx_err;
1345
1346         rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1347         dev->phy.phy_type =
1348                         (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1349         dev->phy.interface_type =
1350                         (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1351                                 >> OCRDMA_IF_TYPE_SHIFT;
1352         dev->phy.auto_speeds_supported  =
1353                         (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1354         dev->phy.fixed_speeds_supported =
1355                         (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1356                                 >> OCRDMA_FSPEED_SUPP_SHIFT;
1357 mbx_err:
1358         kfree(cmd);
1359         return status;
1360 }
1361
1362 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1363 {
1364         int status = -ENOMEM;
1365         struct ocrdma_alloc_pd *cmd;
1366         struct ocrdma_alloc_pd_rsp *rsp;
1367
1368         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1369         if (!cmd)
1370                 return status;
1371         if (pd->dpp_enabled)
1372                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1373         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1374         if (status)
1375                 goto mbx_err;
1376         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1377         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1378         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1379                 pd->dpp_enabled = true;
1380                 pd->dpp_page = rsp->dpp_page_pdid >>
1381                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1382         } else {
1383                 pd->dpp_enabled = false;
1384                 pd->num_dpp_qp = 0;
1385         }
1386 mbx_err:
1387         kfree(cmd);
1388         return status;
1389 }
1390
1391 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1392 {
1393         int status = -ENOMEM;
1394         struct ocrdma_dealloc_pd *cmd;
1395
1396         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1397         if (!cmd)
1398                 return status;
1399         cmd->id = pd->id;
1400         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1401         kfree(cmd);
1402         return status;
1403 }
1404
1405 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1406                                int *num_pages, int *page_size)
1407 {
1408         int i;
1409         int mem_size;
1410
1411         *num_entries = roundup_pow_of_two(*num_entries);
1412         mem_size = *num_entries * entry_size;
1413         /* find the possible lowest possible multiplier */
1414         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1415                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1416                         break;
1417         }
1418         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1419                 return -EINVAL;
1420         mem_size = roundup(mem_size,
1421                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1422         *num_pages =
1423             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1424         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1425         *num_entries = mem_size / entry_size;
1426         return 0;
1427 }
1428
1429 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1430 {
1431         int i;
1432         int status = 0;
1433         int max_ah;
1434         struct ocrdma_create_ah_tbl *cmd;
1435         struct ocrdma_create_ah_tbl_rsp *rsp;
1436         struct pci_dev *pdev = dev->nic_info.pdev;
1437         dma_addr_t pa;
1438         struct ocrdma_pbe *pbes;
1439
1440         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1441         if (!cmd)
1442                 return status;
1443
1444         max_ah = OCRDMA_MAX_AH;
1445         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1446
1447         /* number of PBEs in PBL */
1448         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1449                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1450                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1451
1452         /* page size */
1453         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1454                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1455                         break;
1456         }
1457         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1458                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1459
1460         /* ah_entry size */
1461         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1462                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1463                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1464
1465         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1466                                                 &dev->av_tbl.pbl.pa,
1467                                                 GFP_KERNEL);
1468         if (dev->av_tbl.pbl.va == NULL)
1469                 goto mem_err;
1470
1471         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1472                                             &pa, GFP_KERNEL);
1473         if (dev->av_tbl.va == NULL)
1474                 goto mem_err_ah;
1475         dev->av_tbl.pa = pa;
1476         dev->av_tbl.num_ah = max_ah;
1477         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1478
1479         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1480         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1481                 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1482                 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1483                 pa += PAGE_SIZE;
1484         }
1485         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1486         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1487         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1488         if (status)
1489                 goto mbx_err;
1490         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1491         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1492         kfree(cmd);
1493         return 0;
1494
1495 mbx_err:
1496         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1497                           dev->av_tbl.pa);
1498         dev->av_tbl.va = NULL;
1499 mem_err_ah:
1500         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1501                           dev->av_tbl.pbl.pa);
1502         dev->av_tbl.pbl.va = NULL;
1503         dev->av_tbl.size = 0;
1504 mem_err:
1505         kfree(cmd);
1506         return status;
1507 }
1508
1509 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1510 {
1511         struct ocrdma_delete_ah_tbl *cmd;
1512         struct pci_dev *pdev = dev->nic_info.pdev;
1513
1514         if (dev->av_tbl.va == NULL)
1515                 return;
1516
1517         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1518         if (!cmd)
1519                 return;
1520         cmd->ahid = dev->av_tbl.ahid;
1521
1522         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1523         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1524                           dev->av_tbl.pa);
1525         dev->av_tbl.va = NULL;
1526         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1527                           dev->av_tbl.pbl.pa);
1528         kfree(cmd);
1529 }
1530
1531 /* Multiple CQs uses the EQ. This routine returns least used
1532  * EQ to associate with CQ. This will distributes the interrupt
1533  * processing and CPU load to associated EQ, vector and so to that CPU.
1534  */
1535 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1536 {
1537         int i, selected_eq = 0, cq_cnt = 0;
1538         u16 eq_id;
1539
1540         mutex_lock(&dev->dev_lock);
1541         cq_cnt = dev->eq_tbl[0].cq_cnt;
1542         eq_id = dev->eq_tbl[0].q.id;
1543         /* find the EQ which is has the least number of
1544          * CQs associated with it.
1545          */
1546         for (i = 0; i < dev->eq_cnt; i++) {
1547                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1548                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1549                         eq_id = dev->eq_tbl[i].q.id;
1550                         selected_eq = i;
1551                 }
1552         }
1553         dev->eq_tbl[selected_eq].cq_cnt += 1;
1554         mutex_unlock(&dev->dev_lock);
1555         return eq_id;
1556 }
1557
1558 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1559 {
1560         int i;
1561
1562         mutex_lock(&dev->dev_lock);
1563         i = ocrdma_get_eq_table_index(dev, eq_id);
1564         if (i == -EINVAL)
1565                 BUG();
1566         dev->eq_tbl[i].cq_cnt -= 1;
1567         mutex_unlock(&dev->dev_lock);
1568 }
1569
1570 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1571                          int entries, int dpp_cq, u16 pd_id)
1572 {
1573         int status = -ENOMEM; int max_hw_cqe;
1574         struct pci_dev *pdev = dev->nic_info.pdev;
1575         struct ocrdma_create_cq *cmd;
1576         struct ocrdma_create_cq_rsp *rsp;
1577         u32 hw_pages, cqe_size, page_size, cqe_count;
1578
1579         if (entries > dev->attr.max_cqe) {
1580                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1581                        __func__, dev->id, dev->attr.max_cqe, entries);
1582                 return -EINVAL;
1583         }
1584         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1585                 return -EINVAL;
1586
1587         if (dpp_cq) {
1588                 cq->max_hw_cqe = 1;
1589                 max_hw_cqe = 1;
1590                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1591                 hw_pages = 1;
1592         } else {
1593                 cq->max_hw_cqe = dev->attr.max_cqe;
1594                 max_hw_cqe = dev->attr.max_cqe;
1595                 cqe_size = sizeof(struct ocrdma_cqe);
1596                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1597         }
1598
1599         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1600
1601         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1602         if (!cmd)
1603                 return -ENOMEM;
1604         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1605                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1606         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1607         if (!cq->va) {
1608                 status = -ENOMEM;
1609                 goto mem_err;
1610         }
1611         memset(cq->va, 0, cq->len);
1612         page_size = cq->len / hw_pages;
1613         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1614                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1615         cmd->cmd.pgsz_pgcnt |= hw_pages;
1616         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1617
1618         cq->eqn = ocrdma_bind_eq(dev);
1619         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1620         cqe_count = cq->len / cqe_size;
1621         cq->cqe_cnt = cqe_count;
1622         if (cqe_count > 1024) {
1623                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1624                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1625         } else {
1626                 u8 count = 0;
1627                 switch (cqe_count) {
1628                 case 256:
1629                         count = 0;
1630                         break;
1631                 case 512:
1632                         count = 1;
1633                         break;
1634                 case 1024:
1635                         count = 2;
1636                         break;
1637                 default:
1638                         goto mbx_err;
1639                 }
1640                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1641         }
1642         /* shared eq between all the consumer cqs. */
1643         cmd->cmd.eqn = cq->eqn;
1644         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1645                 if (dpp_cq)
1646                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1647                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1648                 cq->phase_change = false;
1649                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1650         } else {
1651                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1652                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1653                 cq->phase_change = true;
1654         }
1655
1656         /* pd_id valid only for v3 */
1657         cmd->cmd.pdid_cqecnt |= (pd_id <<
1658                 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1659         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1660         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1661         if (status)
1662                 goto mbx_err;
1663
1664         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1665         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1666         kfree(cmd);
1667         return 0;
1668 mbx_err:
1669         ocrdma_unbind_eq(dev, cq->eqn);
1670         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1671 mem_err:
1672         kfree(cmd);
1673         return status;
1674 }
1675
1676 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1677 {
1678         int status = -ENOMEM;
1679         struct ocrdma_destroy_cq *cmd;
1680
1681         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1682         if (!cmd)
1683                 return status;
1684         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1685                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1686
1687         cmd->bypass_flush_qid |=
1688             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1689             OCRDMA_DESTROY_CQ_QID_MASK;
1690
1691         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1692         ocrdma_unbind_eq(dev, cq->eqn);
1693         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1694         kfree(cmd);
1695         return status;
1696 }
1697
1698 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1699                           u32 pdid, int addr_check)
1700 {
1701         int status = -ENOMEM;
1702         struct ocrdma_alloc_lkey *cmd;
1703         struct ocrdma_alloc_lkey_rsp *rsp;
1704
1705         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1706         if (!cmd)
1707                 return status;
1708         cmd->pdid = pdid;
1709         cmd->pbl_sz_flags |= addr_check;
1710         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1711         cmd->pbl_sz_flags |=
1712             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1713         cmd->pbl_sz_flags |=
1714             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1715         cmd->pbl_sz_flags |=
1716             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1717         cmd->pbl_sz_flags |=
1718             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1719         cmd->pbl_sz_flags |=
1720             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1721
1722         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1723         if (status)
1724                 goto mbx_err;
1725         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1726         hwmr->lkey = rsp->lrkey;
1727 mbx_err:
1728         kfree(cmd);
1729         return status;
1730 }
1731
1732 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1733 {
1734         int status = -ENOMEM;
1735         struct ocrdma_dealloc_lkey *cmd;
1736
1737         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1738         if (!cmd)
1739                 return -ENOMEM;
1740         cmd->lkey = lkey;
1741         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1742         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1743         if (status)
1744                 goto mbx_err;
1745 mbx_err:
1746         kfree(cmd);
1747         return status;
1748 }
1749
1750 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1751                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1752 {
1753         int status = -ENOMEM;
1754         int i;
1755         struct ocrdma_reg_nsmr *cmd;
1756         struct ocrdma_reg_nsmr_rsp *rsp;
1757
1758         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1759         if (!cmd)
1760                 return -ENOMEM;
1761         cmd->num_pbl_pdid =
1762             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1763         cmd->fr_mr = hwmr->fr_mr;
1764
1765         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1766                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1767         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1768                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1769         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1770                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1771         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1772                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1773         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1774                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1775         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1776
1777         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1778         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1779                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1780         cmd->totlen_low = hwmr->len;
1781         cmd->totlen_high = upper_32_bits(hwmr->len);
1782         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1783         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1784         cmd->va_loaddr = (u32) hwmr->va;
1785         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1786
1787         for (i = 0; i < pbl_cnt; i++) {
1788                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1789                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1790         }
1791         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1792         if (status)
1793                 goto mbx_err;
1794         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1795         hwmr->lkey = rsp->lrkey;
1796 mbx_err:
1797         kfree(cmd);
1798         return status;
1799 }
1800
1801 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1802                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1803                                   u32 pbl_offset, u32 last)
1804 {
1805         int status = -ENOMEM;
1806         int i;
1807         struct ocrdma_reg_nsmr_cont *cmd;
1808
1809         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1810         if (!cmd)
1811                 return -ENOMEM;
1812         cmd->lrkey = hwmr->lkey;
1813         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1814             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1815         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1816
1817         for (i = 0; i < pbl_cnt; i++) {
1818                 cmd->pbl[i].lo =
1819                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1820                 cmd->pbl[i].hi =
1821                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1822         }
1823         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1824         if (status)
1825                 goto mbx_err;
1826 mbx_err:
1827         kfree(cmd);
1828         return status;
1829 }
1830
1831 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1832                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1833 {
1834         int status;
1835         u32 last = 0;
1836         u32 cur_pbl_cnt, pbl_offset;
1837         u32 pending_pbl_cnt = hwmr->num_pbls;
1838
1839         pbl_offset = 0;
1840         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1841         if (cur_pbl_cnt == pending_pbl_cnt)
1842                 last = 1;
1843
1844         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1845                                    cur_pbl_cnt, hwmr->pbe_size, last);
1846         if (status) {
1847                 pr_err("%s() status=%d\n", __func__, status);
1848                 return status;
1849         }
1850         /* if there is no more pbls to register then exit. */
1851         if (last)
1852                 return 0;
1853
1854         while (!last) {
1855                 pbl_offset += cur_pbl_cnt;
1856                 pending_pbl_cnt -= cur_pbl_cnt;
1857                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1858                 /* if we reach the end of the pbls, then need to set the last
1859                  * bit, indicating no more pbls to register for this memory key.
1860                  */
1861                 if (cur_pbl_cnt == pending_pbl_cnt)
1862                         last = 1;
1863
1864                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1865                                                 pbl_offset, last);
1866                 if (status)
1867                         break;
1868         }
1869         if (status)
1870                 pr_err("%s() err. status=%d\n", __func__, status);
1871
1872         return status;
1873 }
1874
1875 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1876 {
1877         struct ocrdma_qp *tmp;
1878         bool found = false;
1879         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1880                 if (qp == tmp) {
1881                         found = true;
1882                         break;
1883                 }
1884         }
1885         return found;
1886 }
1887
1888 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1889 {
1890         struct ocrdma_qp *tmp;
1891         bool found = false;
1892         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1893                 if (qp == tmp) {
1894                         found = true;
1895                         break;
1896                 }
1897         }
1898         return found;
1899 }
1900
1901 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1902 {
1903         bool found;
1904         unsigned long flags;
1905
1906         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1907         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1908         if (!found)
1909                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1910         if (!qp->srq) {
1911                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1912                 if (!found)
1913                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1914         }
1915         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1916 }
1917
1918 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1919 {
1920         qp->sq.head = 0;
1921         qp->sq.tail = 0;
1922         qp->rq.head = 0;
1923         qp->rq.tail = 0;
1924 }
1925
1926 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1927                            enum ib_qp_state *old_ib_state)
1928 {
1929         unsigned long flags;
1930         int status = 0;
1931         enum ocrdma_qp_state new_state;
1932         new_state = get_ocrdma_qp_state(new_ib_state);
1933
1934         /* sync with wqe and rqe posting */
1935         spin_lock_irqsave(&qp->q_lock, flags);
1936
1937         if (old_ib_state)
1938                 *old_ib_state = get_ibqp_state(qp->state);
1939         if (new_state == qp->state) {
1940                 spin_unlock_irqrestore(&qp->q_lock, flags);
1941                 return 1;
1942         }
1943
1944
1945         if (new_state == OCRDMA_QPS_INIT) {
1946                 ocrdma_init_hwq_ptr(qp);
1947                 ocrdma_del_flush_qp(qp);
1948         } else if (new_state == OCRDMA_QPS_ERR) {
1949                 ocrdma_flush_qp(qp);
1950         }
1951
1952         qp->state = new_state;
1953
1954         spin_unlock_irqrestore(&qp->q_lock, flags);
1955         return status;
1956 }
1957
1958 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1959 {
1960         u32 flags = 0;
1961         if (qp->cap_flags & OCRDMA_QP_INB_RD)
1962                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1963         if (qp->cap_flags & OCRDMA_QP_INB_WR)
1964                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1965         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1966                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1967         if (qp->cap_flags & OCRDMA_QP_LKEY0)
1968                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1969         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1970                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1971         return flags;
1972 }
1973
1974 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1975                                         struct ib_qp_init_attr *attrs,
1976                                         struct ocrdma_qp *qp)
1977 {
1978         int status;
1979         u32 len, hw_pages, hw_page_size;
1980         dma_addr_t pa;
1981         struct ocrdma_dev *dev = qp->dev;
1982         struct pci_dev *pdev = dev->nic_info.pdev;
1983         u32 max_wqe_allocated;
1984         u32 max_sges = attrs->cap.max_send_sge;
1985
1986         /* QP1 may exceed 127 */
1987         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
1988                                 dev->attr.max_wqe);
1989
1990         status = ocrdma_build_q_conf(&max_wqe_allocated,
1991                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1992         if (status) {
1993                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1994                        max_wqe_allocated);
1995                 return -EINVAL;
1996         }
1997         qp->sq.max_cnt = max_wqe_allocated;
1998         len = (hw_pages * hw_page_size);
1999
2000         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2001         if (!qp->sq.va)
2002                 return -EINVAL;
2003         memset(qp->sq.va, 0, len);
2004         qp->sq.len = len;
2005         qp->sq.pa = pa;
2006         qp->sq.entry_size = dev->attr.wqe_size;
2007         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2008
2009         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2010                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2011         cmd->num_wq_rq_pages |= (hw_pages <<
2012                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2013             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2014         cmd->max_sge_send_write |= (max_sges <<
2015                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2016             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2017         cmd->max_sge_send_write |= (max_sges <<
2018                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2019                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2020         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2021                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2022                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2023         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2024                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2025                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2026         return 0;
2027 }
2028
2029 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2030                                         struct ib_qp_init_attr *attrs,
2031                                         struct ocrdma_qp *qp)
2032 {
2033         int status;
2034         u32 len, hw_pages, hw_page_size;
2035         dma_addr_t pa = 0;
2036         struct ocrdma_dev *dev = qp->dev;
2037         struct pci_dev *pdev = dev->nic_info.pdev;
2038         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2039
2040         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2041                                      &hw_pages, &hw_page_size);
2042         if (status) {
2043                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2044                        attrs->cap.max_recv_wr + 1);
2045                 return status;
2046         }
2047         qp->rq.max_cnt = max_rqe_allocated;
2048         len = (hw_pages * hw_page_size);
2049
2050         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2051         if (!qp->rq.va)
2052                 return -ENOMEM;
2053         memset(qp->rq.va, 0, len);
2054         qp->rq.pa = pa;
2055         qp->rq.len = len;
2056         qp->rq.entry_size = dev->attr.rqe_size;
2057
2058         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2059         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2060                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2061         cmd->num_wq_rq_pages |=
2062             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2063             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2064         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2065                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2066                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2067         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2068                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2069                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2070         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2071                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2072                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2073         return 0;
2074 }
2075
2076 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2077                                          struct ocrdma_pd *pd,
2078                                          struct ocrdma_qp *qp,
2079                                          u8 enable_dpp_cq, u16 dpp_cq_id)
2080 {
2081         pd->num_dpp_qp--;
2082         qp->dpp_enabled = true;
2083         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2084         if (!enable_dpp_cq)
2085                 return;
2086         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2087         cmd->dpp_credits_cqid = dpp_cq_id;
2088         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2089                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2090 }
2091
2092 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2093                                         struct ocrdma_qp *qp)
2094 {
2095         struct ocrdma_dev *dev = qp->dev;
2096         struct pci_dev *pdev = dev->nic_info.pdev;
2097         dma_addr_t pa = 0;
2098         int ird_page_size = dev->attr.ird_page_size;
2099         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2100         struct ocrdma_hdr_wqe *rqe;
2101         int i  = 0;
2102
2103         if (dev->attr.ird == 0)
2104                 return 0;
2105
2106         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2107                                         &pa, GFP_KERNEL);
2108         if (!qp->ird_q_va)
2109                 return -ENOMEM;
2110         memset(qp->ird_q_va, 0, ird_q_len);
2111         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2112                              pa, ird_page_size);
2113         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2114                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2115                         (i * dev->attr.rqe_size));
2116                 rqe->cw = 0;
2117                 rqe->cw |= 2;
2118                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2119                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2120                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2121         }
2122         return 0;
2123 }
2124
2125 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2126                                      struct ocrdma_qp *qp,
2127                                      struct ib_qp_init_attr *attrs,
2128                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
2129 {
2130         u32 max_wqe_allocated, max_rqe_allocated;
2131         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2132         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2133         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2134         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2135         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2136         qp->dpp_enabled = false;
2137         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2138                 qp->dpp_enabled = true;
2139                 *dpp_credit_lmt = (rsp->dpp_response &
2140                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2141                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2142                 *dpp_offset = (rsp->dpp_response &
2143                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2144                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2145         }
2146         max_wqe_allocated =
2147                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2148         max_wqe_allocated = 1 << max_wqe_allocated;
2149         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2150
2151         qp->sq.max_cnt = max_wqe_allocated;
2152         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2153
2154         if (!attrs->srq) {
2155                 qp->rq.max_cnt = max_rqe_allocated;
2156                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2157         }
2158 }
2159
2160 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2161                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2162                          u16 *dpp_credit_lmt)
2163 {
2164         int status = -ENOMEM;
2165         u32 flags = 0;
2166         struct ocrdma_dev *dev = qp->dev;
2167         struct ocrdma_pd *pd = qp->pd;
2168         struct pci_dev *pdev = dev->nic_info.pdev;
2169         struct ocrdma_cq *cq;
2170         struct ocrdma_create_qp_req *cmd;
2171         struct ocrdma_create_qp_rsp *rsp;
2172         int qptype;
2173
2174         switch (attrs->qp_type) {
2175         case IB_QPT_GSI:
2176                 qptype = OCRDMA_QPT_GSI;
2177                 break;
2178         case IB_QPT_RC:
2179                 qptype = OCRDMA_QPT_RC;
2180                 break;
2181         case IB_QPT_UD:
2182                 qptype = OCRDMA_QPT_UD;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2189         if (!cmd)
2190                 return status;
2191         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2192                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2193         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2194         if (status)
2195                 goto sq_err;
2196
2197         if (attrs->srq) {
2198                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2199                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2200                 cmd->rq_addr[0].lo = srq->id;
2201                 qp->srq = srq;
2202         } else {
2203                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2204                 if (status)
2205                         goto rq_err;
2206         }
2207
2208         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2209         if (status)
2210                 goto mbx_err;
2211
2212         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2213                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2214
2215         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2216
2217         cmd->max_sge_recv_flags |= flags;
2218         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2219                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2220                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2221         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2222                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2223                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2224         cq = get_ocrdma_cq(attrs->send_cq);
2225         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2226                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2227         qp->sq_cq = cq;
2228         cq = get_ocrdma_cq(attrs->recv_cq);
2229         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2230                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2231         qp->rq_cq = cq;
2232
2233         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2234             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2235                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2236                                              dpp_cq_id);
2237         }
2238
2239         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2240         if (status)
2241                 goto mbx_err;
2242         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2243         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2244         qp->state = OCRDMA_QPS_RST;
2245         kfree(cmd);
2246         return 0;
2247 mbx_err:
2248         if (qp->rq.va)
2249                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2250 rq_err:
2251         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2252         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2253 sq_err:
2254         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2255         kfree(cmd);
2256         return status;
2257 }
2258
2259 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2260                         struct ocrdma_qp_params *param)
2261 {
2262         int status = -ENOMEM;
2263         struct ocrdma_query_qp *cmd;
2264         struct ocrdma_query_qp_rsp *rsp;
2265
2266         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2267         if (!cmd)
2268                 return status;
2269         cmd->qp_id = qp->id;
2270         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2271         if (status)
2272                 goto mbx_err;
2273         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2274         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2275 mbx_err:
2276         kfree(cmd);
2277         return status;
2278 }
2279
2280 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2281                                 struct ocrdma_modify_qp *cmd,
2282                                 struct ib_qp_attr *attrs,
2283                                 int attr_mask)
2284 {
2285         int status;
2286         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2287         union ib_gid sgid, zgid;
2288         u32 vlan_id;
2289         u8 mac_addr[6];
2290
2291         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2292                 return -EINVAL;
2293         if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2294                 ocrdma_init_service_level(qp->dev);
2295         cmd->params.tclass_sq_psn |=
2296             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2297         cmd->params.rnt_rc_sl_fl |=
2298             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2299         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2300         cmd->params.hop_lmt_rq_psn |=
2301             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2302         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2303         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2304                sizeof(cmd->params.dgid));
2305         status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2306                         ah_attr->grh.sgid_index, &sgid);
2307         if (status)
2308                 return status;
2309
2310         memset(&zgid, 0, sizeof(zgid));
2311         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2312                 return -EINVAL;
2313
2314         qp->sgid_idx = ah_attr->grh.sgid_index;
2315         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2316         ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2317         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2318                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2319         /* convert them to LE format. */
2320         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2321         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2322         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2323         if (attr_mask & IB_QP_VID) {
2324                 vlan_id = attrs->vlan_id;
2325                 cmd->params.vlan_dmac_b4_to_b5 |=
2326                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2327                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2328                 cmd->params.rnt_rc_sl_fl |=
2329                         (qp->dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2330         }
2331         return 0;
2332 }
2333
2334 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2335                                 struct ocrdma_modify_qp *cmd,
2336                                 struct ib_qp_attr *attrs, int attr_mask)
2337 {
2338         int status = 0;
2339
2340         if (attr_mask & IB_QP_PKEY_INDEX) {
2341                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2342                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2343                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2344         }
2345         if (attr_mask & IB_QP_QKEY) {
2346                 qp->qkey = attrs->qkey;
2347                 cmd->params.qkey = attrs->qkey;
2348                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2349         }
2350         if (attr_mask & IB_QP_AV) {
2351                 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2352                 if (status)
2353                         return status;
2354         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2355                 /* set the default mac address for UD, GSI QPs */
2356                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2357                         (qp->dev->nic_info.mac_addr[1] << 8) |
2358                         (qp->dev->nic_info.mac_addr[2] << 16) |
2359                         (qp->dev->nic_info.mac_addr[3] << 24);
2360                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2361                                         (qp->dev->nic_info.mac_addr[5] << 8);
2362         }
2363         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2364             attrs->en_sqd_async_notify) {
2365                 cmd->params.max_sge_recv_flags |=
2366                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2367                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2368         }
2369         if (attr_mask & IB_QP_DEST_QPN) {
2370                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2371                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2372                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2373         }
2374         if (attr_mask & IB_QP_PATH_MTU) {
2375                 if (attrs->path_mtu < IB_MTU_256 ||
2376                     attrs->path_mtu > IB_MTU_4096) {
2377                         status = -EINVAL;
2378                         goto pmtu_err;
2379                 }
2380                 cmd->params.path_mtu_pkey_indx |=
2381                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2382                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2383                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2384                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2385         }
2386         if (attr_mask & IB_QP_TIMEOUT) {
2387                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2388                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2389                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2390         }
2391         if (attr_mask & IB_QP_RETRY_CNT) {
2392                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2393                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2394                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2395                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2396         }
2397         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2398                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2399                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2400                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2401                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2402         }
2403         if (attr_mask & IB_QP_RNR_RETRY) {
2404                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2405                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2406                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2407                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2408         }
2409         if (attr_mask & IB_QP_SQ_PSN) {
2410                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2411                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2412         }
2413         if (attr_mask & IB_QP_RQ_PSN) {
2414                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2415                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2416         }
2417         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2418                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2419                         status = -EINVAL;
2420                         goto pmtu_err;
2421                 }
2422                 qp->max_ord = attrs->max_rd_atomic;
2423                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2424         }
2425         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2426                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2427                         status = -EINVAL;
2428                         goto pmtu_err;
2429                 }
2430                 qp->max_ird = attrs->max_dest_rd_atomic;
2431                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2432         }
2433         cmd->params.max_ord_ird = (qp->max_ord <<
2434                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2435                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2436 pmtu_err:
2437         return status;
2438 }
2439
2440 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2441                          struct ib_qp_attr *attrs, int attr_mask)
2442 {
2443         int status = -ENOMEM;
2444         struct ocrdma_modify_qp *cmd;
2445
2446         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2447         if (!cmd)
2448                 return status;
2449
2450         cmd->params.id = qp->id;
2451         cmd->flags = 0;
2452         if (attr_mask & IB_QP_STATE) {
2453                 cmd->params.max_sge_recv_flags |=
2454                     (get_ocrdma_qp_state(attrs->qp_state) <<
2455                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2456                     OCRDMA_QP_PARAMS_STATE_MASK;
2457                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2458         } else {
2459                 cmd->params.max_sge_recv_flags |=
2460                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2461                     OCRDMA_QP_PARAMS_STATE_MASK;
2462         }
2463
2464         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2465         if (status)
2466                 goto mbx_err;
2467         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2468         if (status)
2469                 goto mbx_err;
2470
2471 mbx_err:
2472         kfree(cmd);
2473         return status;
2474 }
2475
2476 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2477 {
2478         int status = -ENOMEM;
2479         struct ocrdma_destroy_qp *cmd;
2480         struct pci_dev *pdev = dev->nic_info.pdev;
2481
2482         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2483         if (!cmd)
2484                 return status;
2485         cmd->qp_id = qp->id;
2486         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2487         if (status)
2488                 goto mbx_err;
2489
2490 mbx_err:
2491         kfree(cmd);
2492         if (qp->sq.va)
2493                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2494         if (!qp->srq && qp->rq.va)
2495                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2496         if (qp->dpp_enabled)
2497                 qp->pd->num_dpp_qp++;
2498         return status;
2499 }
2500
2501 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2502                           struct ib_srq_init_attr *srq_attr,
2503                           struct ocrdma_pd *pd)
2504 {
2505         int status = -ENOMEM;
2506         int hw_pages, hw_page_size;
2507         int len;
2508         struct ocrdma_create_srq_rsp *rsp;
2509         struct ocrdma_create_srq *cmd;
2510         dma_addr_t pa;
2511         struct pci_dev *pdev = dev->nic_info.pdev;
2512         u32 max_rqe_allocated;
2513
2514         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2515         if (!cmd)
2516                 return status;
2517
2518         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2519         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2520         status = ocrdma_build_q_conf(&max_rqe_allocated,
2521                                 dev->attr.rqe_size,
2522                                 &hw_pages, &hw_page_size);
2523         if (status) {
2524                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2525                        srq_attr->attr.max_wr);
2526                 status = -EINVAL;
2527                 goto ret;
2528         }
2529         len = hw_pages * hw_page_size;
2530         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2531         if (!srq->rq.va) {
2532                 status = -ENOMEM;
2533                 goto ret;
2534         }
2535         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2536
2537         srq->rq.entry_size = dev->attr.rqe_size;
2538         srq->rq.pa = pa;
2539         srq->rq.len = len;
2540         srq->rq.max_cnt = max_rqe_allocated;
2541
2542         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2543         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2544                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2545
2546         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2547                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2548         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2549                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2550                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2551         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2552
2553         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2554         if (status)
2555                 goto mbx_err;
2556         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2557         srq->id = rsp->id;
2558         srq->rq.dbid = rsp->id;
2559         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2560                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2561                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2562         max_rqe_allocated = (1 << max_rqe_allocated);
2563         srq->rq.max_cnt = max_rqe_allocated;
2564         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2565         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2566                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2567                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2568         goto ret;
2569 mbx_err:
2570         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2571 ret:
2572         kfree(cmd);
2573         return status;
2574 }
2575
2576 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2577 {
2578         int status = -ENOMEM;
2579         struct ocrdma_modify_srq *cmd;
2580         struct ocrdma_pd *pd = srq->pd;
2581         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2582
2583         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2584         if (!cmd)
2585                 return status;
2586         cmd->id = srq->id;
2587         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2588             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2589         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2590         kfree(cmd);
2591         return status;
2592 }
2593
2594 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2595 {
2596         int status = -ENOMEM;
2597         struct ocrdma_query_srq *cmd;
2598         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2599
2600         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2601         if (!cmd)
2602                 return status;
2603         cmd->id = srq->rq.dbid;
2604         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2605         if (status == 0) {
2606                 struct ocrdma_query_srq_rsp *rsp =
2607                     (struct ocrdma_query_srq_rsp *)cmd;
2608                 srq_attr->max_sge =
2609                     rsp->srq_lmt_max_sge &
2610                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2611                 srq_attr->max_wr =
2612                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2613                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2614                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2615         }
2616         kfree(cmd);
2617         return status;
2618 }
2619
2620 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2621 {
2622         int status = -ENOMEM;
2623         struct ocrdma_destroy_srq *cmd;
2624         struct pci_dev *pdev = dev->nic_info.pdev;
2625         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2626         if (!cmd)
2627                 return status;
2628         cmd->id = srq->id;
2629         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2630         if (srq->rq.va)
2631                 dma_free_coherent(&pdev->dev, srq->rq.len,
2632                                   srq->rq.va, srq->rq.pa);
2633         kfree(cmd);
2634         return status;
2635 }
2636
2637 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2638                                       struct ocrdma_dcbx_cfg *dcbxcfg)
2639 {
2640         int status = 0;
2641         dma_addr_t pa;
2642         struct ocrdma_mqe cmd;
2643
2644         struct ocrdma_get_dcbx_cfg_req *req = NULL;
2645         struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2646         struct pci_dev *pdev = dev->nic_info.pdev;
2647         struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2648
2649         memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2650         cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2651                                         sizeof(struct ocrdma_get_dcbx_cfg_req));
2652         req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2653         if (!req) {
2654                 status = -ENOMEM;
2655                 goto mem_err;
2656         }
2657
2658         cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2659                                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
2660         mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2661         mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2662         mqe_sge->len = cmd.hdr.pyld_len;
2663
2664         memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2665         ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2666                         OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2667         req->param_type = ptype;
2668
2669         status = ocrdma_mbx_cmd(dev, &cmd);
2670         if (status)
2671                 goto mbx_err;
2672
2673         rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2674         ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2675         memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2676
2677 mbx_err:
2678         dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2679 mem_err:
2680         return status;
2681 }
2682
2683 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX  0x08
2684 #define OCRDMA_DEFAULT_SERVICE_LEVEL    0x05
2685
2686 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2687                                     struct ocrdma_dcbx_cfg *dcbxcfg,
2688                                     u8 *srvc_lvl)
2689 {
2690         int status = -EINVAL, indx, slindx;
2691         int ventry_cnt;
2692         struct ocrdma_app_parameter *app_param;
2693         u8 valid, proto_sel;
2694         u8 app_prio, pfc_prio;
2695         u16 proto;
2696
2697         if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2698                 pr_info("%s ocrdma%d DCBX is disabled\n",
2699                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2700                 goto out;
2701         }
2702
2703         if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2704                 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2705                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2706                         (ptype > 0 ? "operational" : "admin"),
2707                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2708                         "enabled" : "disabled",
2709                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2710                         "" : ", not sync'ed");
2711                 goto out;
2712         } else {
2713                 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2714                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2715         }
2716
2717         ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2718                                 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2719                                 & OCRDMA_DCBX_STATE_MASK;
2720
2721         for (indx = 0; indx < ventry_cnt; indx++) {
2722                 app_param = &dcbxcfg->app_param[indx];
2723                 valid = (app_param->valid_proto_app >>
2724                                 OCRDMA_APP_PARAM_VALID_SHIFT)
2725                                 & OCRDMA_APP_PARAM_VALID_MASK;
2726                 proto_sel = (app_param->valid_proto_app
2727                                 >>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2728                                 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2729                 proto = app_param->valid_proto_app &
2730                                 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2731
2732                 if (
2733                         valid && proto == OCRDMA_APP_PROTO_ROCE &&
2734                         proto_sel == OCRDMA_PROTO_SELECT_L2) {
2735                         for (slindx = 0; slindx <
2736                                 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2737                                 app_prio = ocrdma_get_app_prio(
2738                                                 (u8 *)app_param->app_prio,
2739                                                 slindx);
2740                                 pfc_prio = ocrdma_get_pfc_prio(
2741                                                 (u8 *)dcbxcfg->pfc_prio,
2742                                                 slindx);
2743
2744                                 if (app_prio && pfc_prio) {
2745                                         *srvc_lvl = slindx;
2746                                         status = 0;
2747                                         goto out;
2748                                 }
2749                         }
2750                         if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2751                                 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2752                                         dev_name(&dev->nic_info.pdev->dev),
2753                                         dev->id, proto);
2754                         }
2755                 }
2756         }
2757
2758 out:
2759         return status;
2760 }
2761
2762 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2763 {
2764         int status = 0, indx;
2765         struct ocrdma_dcbx_cfg dcbxcfg;
2766         u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2767         int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2768
2769         for (indx = 0; indx < 2; indx++) {
2770                 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2771                 if (status) {
2772                         pr_err("%s(): status=%d\n", __func__, status);
2773                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2774                         continue;
2775                 }
2776
2777                 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2778                                                   &dcbxcfg, &srvc_lvl);
2779                 if (status) {
2780                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2781                         continue;
2782                 }
2783
2784                 break;
2785         }
2786
2787         if (status)
2788                 pr_info("%s ocrdma%d service level default\n",
2789                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2790         else
2791                 pr_info("%s ocrdma%d service level %d\n",
2792                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2793                         srvc_lvl);
2794
2795         dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2796         dev->sl = srvc_lvl;
2797 }
2798
2799 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2800 {
2801         int i;
2802         int status = -EINVAL;
2803         struct ocrdma_av *av;
2804         unsigned long flags;
2805
2806         av = dev->av_tbl.va;
2807         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2808         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2809                 if (av->valid == 0) {
2810                         av->valid = OCRDMA_AV_VALID;
2811                         ah->av = av;
2812                         ah->id = i;
2813                         status = 0;
2814                         break;
2815                 }
2816                 av++;
2817         }
2818         if (i == dev->av_tbl.num_ah)
2819                 status = -EAGAIN;
2820         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2821         return status;
2822 }
2823
2824 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2825 {
2826         unsigned long flags;
2827         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2828         ah->av->valid = 0;
2829         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2830         return 0;
2831 }
2832
2833 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2834 {
2835         int num_eq, i, status = 0;
2836         int irq;
2837         unsigned long flags = 0;
2838
2839         num_eq = dev->nic_info.msix.num_vectors -
2840                         dev->nic_info.msix.start_vector;
2841         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2842                 num_eq = 1;
2843                 flags = IRQF_SHARED;
2844         } else {
2845                 num_eq = min_t(u32, num_eq, num_online_cpus());
2846         }
2847
2848         if (!num_eq)
2849                 return -EINVAL;
2850
2851         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2852         if (!dev->eq_tbl)
2853                 return -ENOMEM;
2854
2855         for (i = 0; i < num_eq; i++) {
2856                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2857                                         OCRDMA_EQ_LEN);
2858                 if (status) {
2859                         status = -EINVAL;
2860                         break;
2861                 }
2862                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2863                         dev->id, i);
2864                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2865                 status = request_irq(irq, ocrdma_irq_handler, flags,
2866                                      dev->eq_tbl[i].irq_name,
2867                                      &dev->eq_tbl[i]);
2868                 if (status)
2869                         goto done;
2870                 dev->eq_cnt += 1;
2871         }
2872         /* one eq is sufficient for data path to work */
2873         return 0;
2874 done:
2875         ocrdma_destroy_eqs(dev);
2876         return status;
2877 }
2878
2879 int ocrdma_init_hw(struct ocrdma_dev *dev)
2880 {
2881         int status;
2882
2883         /* create the eqs  */
2884         status = ocrdma_create_eqs(dev);
2885         if (status)
2886                 goto qpeq_err;
2887         status = ocrdma_create_mq(dev);
2888         if (status)
2889                 goto mq_err;
2890         status = ocrdma_mbx_query_fw_config(dev);
2891         if (status)
2892                 goto conf_err;
2893         status = ocrdma_mbx_query_dev(dev);
2894         if (status)
2895                 goto conf_err;
2896         status = ocrdma_mbx_query_fw_ver(dev);
2897         if (status)
2898                 goto conf_err;
2899         status = ocrdma_mbx_create_ah_tbl(dev);
2900         if (status)
2901                 goto conf_err;
2902         status = ocrdma_mbx_get_phy_info(dev);
2903         if (status)
2904                 goto info_attrb_err;
2905         status = ocrdma_mbx_get_ctrl_attribs(dev);
2906         if (status)
2907                 goto info_attrb_err;
2908
2909         return 0;
2910
2911 info_attrb_err:
2912         ocrdma_mbx_delete_ah_tbl(dev);
2913 conf_err:
2914         ocrdma_destroy_mq(dev);
2915 mq_err:
2916         ocrdma_destroy_eqs(dev);
2917 qpeq_err:
2918         pr_err("%s() status=%d\n", __func__, status);
2919         return status;
2920 }
2921
2922 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2923 {
2924         ocrdma_mbx_delete_ah_tbl(dev);
2925
2926         /* cleanup the eqs */
2927         ocrdma_destroy_eqs(dev);
2928
2929         /* cleanup the control path */
2930         ocrdma_destroy_mq(dev);
2931 }