drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35 #include <rdma/ib_addr.h>
  36
  37 #include "ocrdma.h"
  38 #include "ocrdma_hw.h"
  39 #include "ocrdma_verbs.h"
  40 #include "ocrdma_ah.h"
  41
  42 enum mbx_status {
  43         OCRDMA_MBX_STATUS_FAILED                = 1,
  44         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  45         OCRDMA_MBX_STATUS_OOR                   = 100,
  46         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  47         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  48         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  49         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  50         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  51         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  52         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  53         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  54         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  55         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  56         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  57         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  58         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  59         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  60         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  61         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  62         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  63         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  64         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  66         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  67         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  68         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  69         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  70         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  71         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  72         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  73         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  74         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  75         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  76         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  77         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  78         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  80         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  81 };
  82
  83 enum additional_status {
  84         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  85 };
  86
  87 enum cqe_status {
  88         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  89         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  90         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  91         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  92         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  93 };
  94
  95 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  96 {
  97         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  98 }
  99
 100 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 101 {
 102         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 103 }
 104
 105 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 106 {
 107         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 108             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 109
 110         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 111                 return NULL;
 112         return cqe;
 113 }
 114
 115 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 116 {
 117         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 118 }
 119
 120 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 121 {
 122         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 123 }
 124
 125 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 126 {
 127         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 128 }
 129
 130 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 131 {
 132         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 133 }
 134
 135 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 136 {
 137         switch (qps) {
 138         case OCRDMA_QPS_RST:
 139                 return IB_QPS_RESET;
 140         case OCRDMA_QPS_INIT:
 141                 return IB_QPS_INIT;
 142         case OCRDMA_QPS_RTR:
 143                 return IB_QPS_RTR;
 144         case OCRDMA_QPS_RTS:
 145                 return IB_QPS_RTS;
 146         case OCRDMA_QPS_SQD:
 147         case OCRDMA_QPS_SQ_DRAINING:
 148                 return IB_QPS_SQD;
 149         case OCRDMA_QPS_SQE:
 150                 return IB_QPS_SQE;
 151         case OCRDMA_QPS_ERR:
 152                 return IB_QPS_ERR;
 153         }
 154         return IB_QPS_ERR;
 155 }
 156
 157 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 158 {
 159         switch (qps) {
 160         case IB_QPS_RESET:
 161                 return OCRDMA_QPS_RST;
 162         case IB_QPS_INIT:
 163                 return OCRDMA_QPS_INIT;
 164         case IB_QPS_RTR:
 165                 return OCRDMA_QPS_RTR;
 166         case IB_QPS_RTS:
 167                 return OCRDMA_QPS_RTS;
 168         case IB_QPS_SQD:
 169                 return OCRDMA_QPS_SQD;
 170         case IB_QPS_SQE:
 171                 return OCRDMA_QPS_SQE;
 172         case IB_QPS_ERR:
 173                 return OCRDMA_QPS_ERR;
 174         }
 175         return OCRDMA_QPS_ERR;
 176 }
 177
 178 static int ocrdma_get_mbx_errno(u32 status)
 179 {
 180         int err_num;
 181         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 182                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 183         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 184                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 185
 186         switch (mbox_status) {
 187         case OCRDMA_MBX_STATUS_OOR:
 188         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 189                 err_num = -EAGAIN;
 190                 break;
 191
 192         case OCRDMA_MBX_STATUS_INVALID_PD:
 193         case OCRDMA_MBX_STATUS_INVALID_CQ:
 194         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 195         case OCRDMA_MBX_STATUS_INVALID_QP:
 196         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 197         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 198         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 200         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 201         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 202         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 203         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 204         case OCRDMA_MBX_STATUS_INVALID_VA:
 205         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 206         case OCRDMA_MBX_STATUS_INVALID_FBO:
 207         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 208         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 209         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 210         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 211         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 212                 err_num = -EINVAL;
 213                 break;
 214
 215         case OCRDMA_MBX_STATUS_PD_INUSE:
 216         case OCRDMA_MBX_STATUS_QP_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 218         case OCRDMA_MBX_STATUS_MW_BOUND:
 219                 err_num = -EBUSY;
 220                 break;
 221
 222         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 230         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 231                 err_num = -ENOBUFS;
 232                 break;
 233
 234         case OCRDMA_MBX_STATUS_FAILED:
 235                 switch (add_status) {
 236                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 237                         err_num = -EAGAIN;
 238                         break;
 239                 }
 240         default:
 241                 err_num = -EFAULT;
 242         }
 243         return err_num;
 244 }
 245
 246 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 247 {
 248         int err_num = -EINVAL;
 249
 250         switch (cqe_status) {
 251         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 252                 err_num = -EPERM;
 253                 break;
 254         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 255                 err_num = -EINVAL;
 256                 break;
 257         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 258         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 259                 err_num = -EINVAL;
 260                 break;
 261         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 262         default:
 263                 err_num = -EINVAL;
 264                 break;
 265         }
 266         return err_num;
 267 }
 268
 269 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 270                        bool solicited, u16 cqe_popped)
 271 {
 272         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 273
 274         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 275              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 276
 277         if (armed)
 278                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 279         if (solicited)
 280                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 281         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 282         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 283 }
 284
 285 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 286 {
 287         u32 val = 0;
 288
 289         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 290         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 291         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 292 }
 293
 294 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 295                               bool arm, bool clear_int, u16 num_eqe)
 296 {
 297         u32 val = 0;
 298
 299         val |= eq_id & OCRDMA_EQ_ID_MASK;
 300         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 301         if (arm)
 302                 val |= (1 << OCRDMA_REARM_SHIFT);
 303         if (clear_int)
 304                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 305         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 306         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 308 }
 309
 310 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 311                             u8 opcode, u8 subsys, u32 cmd_len)
 312 {
 313         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 314         cmd_hdr->timeout = 20; /* seconds */
 315         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 316 }
 317
 318 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 319 {
 320         struct ocrdma_mqe *mqe;
 321
 322         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 323         if (!mqe)
 324                 return NULL;
 325         mqe->hdr.spcl_sge_cnt_emb |=
 326                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 327                                         OCRDMA_MQE_HDR_EMB_MASK;
 328         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 329
 330         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 331                         mqe->hdr.pyld_len);
 332         return mqe;
 333 }
 334
 335 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 336 {
 337         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 338 }
 339
 340 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 341                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 342 {
 343         memset(q, 0, sizeof(*q));
 344         q->len = len;
 345         q->entry_size = entry_size;
 346         q->size = len * entry_size;
 347         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 348                                    &q->dma, GFP_KERNEL);
 349         if (!q->va)
 350                 return -ENOMEM;
 351         memset(q->va, 0, q->size);
 352         return 0;
 353 }
 354
 355 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 356                                         dma_addr_t host_pa, int hw_page_size)
 357 {
 358         int i;
 359
 360         for (i = 0; i < cnt; i++) {
 361                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 362                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 363                 host_pa += hw_page_size;
 364         }
 365 }
 366
 367 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
 368                                int queue_type)
 369 {
 370         u8 opcode = 0;
 371         int status;
 372         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 373
 374         switch (queue_type) {
 375         case QTYPE_MCCQ:
 376                 opcode = OCRDMA_CMD_DELETE_MQ;
 377                 break;
 378         case QTYPE_CQ:
 379                 opcode = OCRDMA_CMD_DELETE_CQ;
 380                 break;
 381         case QTYPE_EQ:
 382                 opcode = OCRDMA_CMD_DELETE_EQ;
 383                 break;
 384         default:
 385                 BUG();
 386         }
 387         memset(cmd, 0, sizeof(*cmd));
 388         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 389         cmd->id = q->id;
 390
 391         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 392                                  cmd, sizeof(*cmd), NULL, NULL);
 393         if (!status)
 394                 q->created = false;
 395         return status;
 396 }
 397
 398 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 399 {
 400         int status;
 401         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 402         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 403
 404         memset(cmd, 0, sizeof(*cmd));
 405         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 406                         sizeof(*cmd));
 407
 408         cmd->req.rsvd_version = 2;
 409         cmd->num_pages = 4;
 410         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 411         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 412
 413         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 414                              PAGE_SIZE_4K);
 415         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 416                                  NULL);
 417         if (!status) {
 418                 eq->q.id = rsp->vector_eqid & 0xffff;
 419                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 420                 eq->q.created = true;
 421         }
 422         return status;
 423 }
 424
 425 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 426                             struct ocrdma_eq *eq, u16 q_len)
 427 {
 428         int status;
 429
 430         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 431                                 sizeof(struct ocrdma_eqe));
 432         if (status)
 433                 return status;
 434
 435         status = ocrdma_mbx_create_eq(dev, eq);
 436         if (status)
 437                 goto mbx_err;
 438         eq->dev = dev;
 439         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 440
 441         return 0;
 442 mbx_err:
 443         ocrdma_free_q(dev, &eq->q);
 444         return status;
 445 }
 446
 447 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 448 {
 449         int irq;
 450
 451         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 452                 irq = dev->nic_info.pdev->irq;
 453         else
 454                 irq = dev->nic_info.msix.vector_list[eq->vector];
 455         return irq;
 456 }
 457
 458 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 459 {
 460         if (eq->q.created) {
 461                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 462                 ocrdma_free_q(dev, &eq->q);
 463         }
 464 }
 465
 466 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 467 {
 468         int irq;
 469
 470         /* disarm EQ so that interrupts are not generated
 471          * during freeing and EQ delete is in progress.
 472          */
 473         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 474
 475         irq = ocrdma_get_irq(dev, eq);
 476         free_irq(irq, eq);
 477         _ocrdma_destroy_eq(dev, eq);
 478 }
 479
 480 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 481 {
 482         int i;
 483
 484         for (i = 0; i < dev->eq_cnt; i++)
 485                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 486 }
 487
 488 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 489                                    struct ocrdma_queue_info *cq,
 490                                    struct ocrdma_queue_info *eq)
 491 {
 492         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 493         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 494         int status;
 495
 496         memset(cmd, 0, sizeof(*cmd));
 497         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 498                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 499
 500         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 501         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 502                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 503         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 504
 505         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 506         cmd->eqn = eq->id;
 507         cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
 508
 509         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 510                              cq->dma, PAGE_SIZE_4K);
 511         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 512                                  cmd, sizeof(*cmd), NULL, NULL);
 513         if (!status) {
 514                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 515                 cq->created = true;
 516         }
 517         return status;
 518 }
 519
 520 static u32 ocrdma_encoded_q_len(int q_len)
 521 {
 522         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 523
 524         if (len_encoded == 16)
 525                 len_encoded = 0;
 526         return len_encoded;
 527 }
 528
 529 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 530                                 struct ocrdma_queue_info *mq,
 531                                 struct ocrdma_queue_info *cq)
 532 {
 533         int num_pages, status;
 534         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 535         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 536         struct ocrdma_pa *pa;
 537
 538         memset(cmd, 0, sizeof(*cmd));
 539         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 540
 541         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 542                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 543         cmd->req.rsvd_version = 1;
 544         cmd->cqid_pages = num_pages;
 545         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 546         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 547
 548         cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
 549         cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
 550
 551         cmd->async_cqid_ringsize = cq->id;
 552         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 553                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 554         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 555         pa = &cmd->pa[0];
 556
 557         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 558         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 559                                  cmd, sizeof(*cmd), NULL, NULL);
 560         if (!status) {
 561                 mq->id = rsp->id;
 562                 mq->created = true;
 563         }
 564         return status;
 565 }
 566
 567 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 568 {
 569         int status;
 570
 571         /* Alloc completion queue for Mailbox queue */
 572         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 573                                 sizeof(struct ocrdma_mcqe));
 574         if (status)
 575                 goto alloc_err;
 576
 577         dev->eq_tbl[0].cq_cnt++;
 578         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 579         if (status)
 580                 goto mbx_cq_free;
 581
 582         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 583         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 584         mutex_init(&dev->mqe_ctx.lock);
 585
 586         /* Alloc Mailbox queue */
 587         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 588                                 sizeof(struct ocrdma_mqe));
 589         if (status)
 590                 goto mbx_cq_destroy;
 591         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 592         if (status)
 593                 goto mbx_q_free;
 594         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 595         return 0;
 596
 597 mbx_q_free:
 598         ocrdma_free_q(dev, &dev->mq.sq);
 599 mbx_cq_destroy:
 600         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 601 mbx_cq_free:
 602         ocrdma_free_q(dev, &dev->mq.cq);
 603 alloc_err:
 604         return status;
 605 }
 606
 607 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 608 {
 609         struct ocrdma_queue_info *mbxq, *cq;
 610
 611         /* mqe_ctx lock synchronizes with any other pending cmds. */
 612         mutex_lock(&dev->mqe_ctx.lock);
 613         mbxq = &dev->mq.sq;
 614         if (mbxq->created) {
 615                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 616                 ocrdma_free_q(dev, mbxq);
 617         }
 618         mutex_unlock(&dev->mqe_ctx.lock);
 619
 620         cq = &dev->mq.cq;
 621         if (cq->created) {
 622                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 623                 ocrdma_free_q(dev, cq);
 624         }
 625 }
 626
 627 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 628                                        struct ocrdma_qp *qp)
 629 {
 630         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 631         enum ib_qp_state old_ib_qps;
 632
 633         if (qp == NULL)
 634                 BUG();
 635         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 636 }
 637
 638 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 639                                     struct ocrdma_ae_mcqe *cqe)
 640 {
 641         struct ocrdma_qp *qp = NULL;
 642         struct ocrdma_cq *cq = NULL;
 643         struct ib_event ib_evt;
 644         int cq_event = 0;
 645         int qp_event = 1;
 646         int srq_event = 0;
 647         int dev_event = 0;
 648         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 649             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 650
 651         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 652                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 653         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 654                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 655
 656         ib_evt.device = &dev->ibdev;
 657
 658         switch (type) {
 659         case OCRDMA_CQ_ERROR:
 660                 ib_evt.element.cq = &cq->ibcq;
 661                 ib_evt.event = IB_EVENT_CQ_ERR;
 662                 cq_event = 1;
 663                 qp_event = 0;
 664                 break;
 665         case OCRDMA_CQ_OVERRUN_ERROR:
 666                 ib_evt.element.cq = &cq->ibcq;
 667                 ib_evt.event = IB_EVENT_CQ_ERR;
 668                 break;
 669         case OCRDMA_CQ_QPCAT_ERROR:
 670                 ib_evt.element.qp = &qp->ibqp;
 671                 ib_evt.event = IB_EVENT_QP_FATAL;
 672                 ocrdma_process_qpcat_error(dev, qp);
 673                 break;
 674         case OCRDMA_QP_ACCESS_ERROR:
 675                 ib_evt.element.qp = &qp->ibqp;
 676                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 677                 break;
 678         case OCRDMA_QP_COMM_EST_EVENT:
 679                 ib_evt.element.qp = &qp->ibqp;
 680                 ib_evt.event = IB_EVENT_COMM_EST;
 681                 break;
 682         case OCRDMA_SQ_DRAINED_EVENT:
 683                 ib_evt.element.qp = &qp->ibqp;
 684                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 685                 break;
 686         case OCRDMA_DEVICE_FATAL_EVENT:
 687                 ib_evt.element.port_num = 1;
 688                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 689                 qp_event = 0;
 690                 dev_event = 1;
 691                 break;
 692         case OCRDMA_SRQCAT_ERROR:
 693                 ib_evt.element.srq = &qp->srq->ibsrq;
 694                 ib_evt.event = IB_EVENT_SRQ_ERR;
 695                 srq_event = 1;
 696                 qp_event = 0;
 697                 break;
 698         case OCRDMA_SRQ_LIMIT_EVENT:
 699                 ib_evt.element.srq = &qp->srq->ibsrq;
 700                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 701                 srq_event = 1;
 702                 qp_event = 0;
 703                 break;
 704         case OCRDMA_QP_LAST_WQE_EVENT:
 705                 ib_evt.element.qp = &qp->ibqp;
 706                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 707                 break;
 708         default:
 709                 cq_event = 0;
 710                 qp_event = 0;
 711                 srq_event = 0;
 712                 dev_event = 0;
 713                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 714                 break;
 715         }
 716
 717         if (qp_event) {
 718                 if (qp->ibqp.event_handler)
 719                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 720         } else if (cq_event) {
 721                 if (cq->ibcq.event_handler)
 722                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 723         } else if (srq_event) {
 724                 if (qp->srq->ibsrq.event_handler)
 725                         qp->srq->ibsrq.event_handler(&ib_evt,
 726                                                      qp->srq->ibsrq.
 727                                                      srq_context);
 728         } else if (dev_event) {
 729                 ib_dispatch_event(&ib_evt);
 730         }
 731
 732 }
 733
 734 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 735                                         struct ocrdma_ae_mcqe *cqe)
 736 {
 737         struct ocrdma_ae_pvid_mcqe *evt;
 738         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 739                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 740
 741         switch (type) {
 742         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 743                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 744                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 745                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 746                         dev->pvid = ((evt->tag_enabled &
 747                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 748                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 749                 break;
 750         default:
 751                 /* Not interested evts. */
 752                 break;
 753         }
 754 }
 755
 756
 757 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 758 {
 759         /* async CQE processing */
 760         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 761         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 762                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 763
 764         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 765                 ocrdma_dispatch_ibevent(dev, cqe);
 766         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 767                 ocrdma_process_grp5_aync(dev, cqe);
 768         else
 769                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 770                        dev->id, evt_code);
 771 }
 772
 773 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 774 {
 775         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 776                 dev->mqe_ctx.cqe_status = (cqe->status &
 777                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 778                 dev->mqe_ctx.ext_status =
 779                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 780                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 781                 dev->mqe_ctx.cmd_done = true;
 782                 wake_up(&dev->mqe_ctx.cmd_wait);
 783         } else
 784                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 785                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 786 }
 787
 788 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 789 {
 790         u16 cqe_popped = 0;
 791         struct ocrdma_mcqe *cqe;
 792
 793         while (1) {
 794                 cqe = ocrdma_get_mcqe(dev);
 795                 if (cqe == NULL)
 796                         break;
 797                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 798                 cqe_popped += 1;
 799                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 800                         ocrdma_process_acqe(dev, cqe);
 801                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 802                         ocrdma_process_mcqe(dev, cqe);
 803                 else
 804                         pr_err("%s() cqe->compl is not set.\n", __func__);
 805                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 806                 ocrdma_mcq_inc_tail(dev);
 807         }
 808         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 809         return 0;
 810 }
 811
 812 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 813                                        struct ocrdma_cq *cq)
 814 {
 815         unsigned long flags;
 816         struct ocrdma_qp *qp;
 817         bool buddy_cq_found = false;
 818         /* Go through list of QPs in error state which are using this CQ
 819          * and invoke its callback handler to trigger CQE processing for
 820          * error/flushed CQE. It is rare to find more than few entries in
 821          * this list as most consumers stops after getting error CQE.
 822          * List is traversed only once when a matching buddy cq found for a QP.
 823          */
 824         spin_lock_irqsave(&dev->flush_q_lock, flags);
 825         list_for_each_entry(qp, &cq->sq_head, sq_entry) {
 826                 if (qp->srq)
 827                         continue;
 828                 /* if wq and rq share the same cq, than comp_handler
 829                  * is already invoked.
 830                  */
 831                 if (qp->sq_cq == qp->rq_cq)
 832                         continue;
 833                 /* if completion came on sq, rq's cq is buddy cq.
 834                  * if completion came on rq, sq's cq is buddy cq.
 835                  */
 836                 if (qp->sq_cq == cq)
 837                         cq = qp->rq_cq;
 838                 else
 839                         cq = qp->sq_cq;
 840                 buddy_cq_found = true;
 841                 break;
 842         }
 843         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 844         if (buddy_cq_found == false)
 845                 return;
 846         if (cq->ibcq.comp_handler) {
 847                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 848                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 849                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 850         }
 851 }
 852
 853 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 854 {
 855         unsigned long flags;
 856         struct ocrdma_cq *cq;
 857
 858         if (cq_idx >= OCRDMA_MAX_CQ)
 859                 BUG();
 860
 861         cq = dev->cq_tbl[cq_idx];
 862         if (cq == NULL)
 863                 return;
 864
 865         if (cq->ibcq.comp_handler) {
 866                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 867                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 868                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 869         }
 870         ocrdma_qp_buddy_cq_handler(dev, cq);
 871 }
 872
 873 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 874 {
 875         /* process the MQ-CQE. */
 876         if (cq_id == dev->mq.cq.id)
 877                 ocrdma_mq_cq_handler(dev, cq_id);
 878         else
 879                 ocrdma_qp_cq_handler(dev, cq_id);
 880 }
 881
 882 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 883 {
 884         struct ocrdma_eq *eq = handle;
 885         struct ocrdma_dev *dev = eq->dev;
 886         struct ocrdma_eqe eqe;
 887         struct ocrdma_eqe *ptr;
 888         u16 cq_id;
 889         int budget = eq->cq_cnt;
 890
 891         do {
 892                 ptr = ocrdma_get_eqe(eq);
 893                 eqe = *ptr;
 894                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 895                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 896                         break;
 897
 898                 ptr->id_valid = 0;
 899                 /* ring eq doorbell as soon as its consumed. */
 900                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 901                 /* check whether its CQE or not. */
 902                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 903                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 904                         ocrdma_cq_handler(dev, cq_id);
 905                 }
 906                 ocrdma_eq_inc_tail(eq);
 907
 908                 /* There can be a stale EQE after the last bound CQ is
 909                  * destroyed. EQE valid and budget == 0 implies this.
 910                  */
 911                 if (budget)
 912                         budget--;
 913
 914         } while (budget);
 915
 916         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 917         return IRQ_HANDLED;
 918 }
 919
 920 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 921 {
 922         struct ocrdma_mqe *mqe;
 923
 924         dev->mqe_ctx.tag = dev->mq.sq.head;
 925         dev->mqe_ctx.cmd_done = false;
 926         mqe = ocrdma_get_mqe(dev);
 927         cmd->hdr.tag_lo = dev->mq.sq.head;
 928         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 929         /* make sure descriptor is written before ringing doorbell */
 930         wmb();
 931         ocrdma_mq_inc_head(dev);
 932         ocrdma_ring_mq_db(dev);
 933 }
 934
 935 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 936 {
 937         long status;
 938         /* 30 sec timeout */
 939         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 940                                     (dev->mqe_ctx.cmd_done != false),
 941                                     msecs_to_jiffies(30000));
 942         if (status)
 943                 return 0;
 944         else
 945                 return -1;
 946 }
 947
 948 /* issue a mailbox command on the MQ */
 949 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
 950 {
 951         int status = 0;
 952         u16 cqe_status, ext_status;
 953         struct ocrdma_mqe *rsp;
 954
 955         mutex_lock(&dev->mqe_ctx.lock);
 956         ocrdma_post_mqe(dev, mqe);
 957         status = ocrdma_wait_mqe_cmpl(dev);
 958         if (status)
 959                 goto mbx_err;
 960         cqe_status = dev->mqe_ctx.cqe_status;
 961         ext_status = dev->mqe_ctx.ext_status;
 962         rsp = ocrdma_get_mqe_rsp(dev);
 963         ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
 964         if (cqe_status || ext_status) {
 965                 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
 966                        __func__,
 967                      (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
 968                      OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
 969                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
 970                 goto mbx_err;
 971         }
 972         if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
 973                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
 974 mbx_err:
 975         mutex_unlock(&dev->mqe_ctx.lock);
 976         return status;
 977 }
 978
 979 static void ocrdma_get_attr(struct ocrdma_dev *dev,
 980                               struct ocrdma_dev_attr *attr,
 981                               struct ocrdma_mbx_query_config *rsp)
 982 {
 983         attr->max_pd =
 984             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
 985             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
 986         attr->max_qp =
 987             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
 988             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
 989         attr->max_send_sge = ((rsp->max_write_send_sge &
 990                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
 991                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
 992         attr->max_recv_sge = (rsp->max_write_send_sge &
 993                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
 994             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
 995         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
 996                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
 997             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
 998         attr->max_rdma_sge = (rsp->max_write_send_sge &
 999                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1000             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1001         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1002                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1003             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1004         attr->max_srq =
1005                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1006                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1007         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1008                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1009             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1010         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1011                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1012             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1013         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1014                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1015             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1016         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1017                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1018             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1019         attr->max_mr = rsp->max_mr;
1020         attr->max_mr_size = ~0ull;
1021         attr->max_fmr = 0;
1022         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1023         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1024         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1025                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1026         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1027                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1028                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1029         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1030                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1031                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1032                 OCRDMA_WQE_STRIDE;
1033         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1034                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1035                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1036                 OCRDMA_WQE_STRIDE;
1037         attr->max_inline_data =
1038             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1039                               sizeof(struct ocrdma_sge));
1040         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1041                 attr->ird = 1;
1042                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1043                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1044         }
1045         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1046                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1047         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1048                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1049 }
1050
1051 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1052                                    struct ocrdma_fw_conf_rsp *conf)
1053 {
1054         u32 fn_mode;
1055
1056         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1057         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1058                 return -EINVAL;
1059         dev->base_eqid = conf->base_eqid;
1060         dev->max_eq = conf->max_eq;
1061         return 0;
1062 }
1063
1064 /* can be issued only during init time. */
1065 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1066 {
1067         int status = -ENOMEM;
1068         struct ocrdma_mqe *cmd;
1069         struct ocrdma_fw_ver_rsp *rsp;
1070
1071         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1072         if (!cmd)
1073                 return -ENOMEM;
1074         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1075                         OCRDMA_CMD_GET_FW_VER,
1076                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1077
1078         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1079         if (status)
1080                 goto mbx_err;
1081         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1082         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1083         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1084                sizeof(rsp->running_ver));
1085         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1086 mbx_err:
1087         kfree(cmd);
1088         return status;
1089 }
1090
1091 /* can be issued only during init time. */
1092 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1093 {
1094         int status = -ENOMEM;
1095         struct ocrdma_mqe *cmd;
1096         struct ocrdma_fw_conf_rsp *rsp;
1097
1098         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1099         if (!cmd)
1100                 return -ENOMEM;
1101         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1102                         OCRDMA_CMD_GET_FW_CONFIG,
1103                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1104         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1105         if (status)
1106                 goto mbx_err;
1107         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1108         status = ocrdma_check_fw_config(dev, rsp);
1109 mbx_err:
1110         kfree(cmd);
1111         return status;
1112 }
1113
1114 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1115 {
1116         int status = -ENOMEM;
1117         struct ocrdma_mbx_query_config *rsp;
1118         struct ocrdma_mqe *cmd;
1119
1120         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1121         if (!cmd)
1122                 return status;
1123         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1124         if (status)
1125                 goto mbx_err;
1126         rsp = (struct ocrdma_mbx_query_config *)cmd;
1127         ocrdma_get_attr(dev, &dev->attr, rsp);
1128 mbx_err:
1129         kfree(cmd);
1130         return status;
1131 }
1132
1133 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1134 {
1135         int status = -ENOMEM;
1136         struct ocrdma_get_link_speed_rsp *rsp;
1137         struct ocrdma_mqe *cmd;
1138
1139         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1140                                   sizeof(*cmd));
1141         if (!cmd)
1142                 return status;
1143         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1144                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1145                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1146
1147         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1148
1149         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1150         if (status)
1151                 goto mbx_err;
1152
1153         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1154         *lnk_speed = rsp->phys_port_speed;
1155
1156 mbx_err:
1157         kfree(cmd);
1158         return status;
1159 }
1160
1161 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1162 {
1163         int status = -ENOMEM;
1164         struct ocrdma_alloc_pd *cmd;
1165         struct ocrdma_alloc_pd_rsp *rsp;
1166
1167         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1168         if (!cmd)
1169                 return status;
1170         if (pd->dpp_enabled)
1171                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1172         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1173         if (status)
1174                 goto mbx_err;
1175         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1176         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1177         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1178                 pd->dpp_enabled = true;
1179                 pd->dpp_page = rsp->dpp_page_pdid >>
1180                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1181         } else {
1182                 pd->dpp_enabled = false;
1183                 pd->num_dpp_qp = 0;
1184         }
1185 mbx_err:
1186         kfree(cmd);
1187         return status;
1188 }
1189
1190 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1191 {
1192         int status = -ENOMEM;
1193         struct ocrdma_dealloc_pd *cmd;
1194
1195         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1196         if (!cmd)
1197                 return status;
1198         cmd->id = pd->id;
1199         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1200         kfree(cmd);
1201         return status;
1202 }
1203
1204 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1205                                int *num_pages, int *page_size)
1206 {
1207         int i;
1208         int mem_size;
1209
1210         *num_entries = roundup_pow_of_two(*num_entries);
1211         mem_size = *num_entries * entry_size;
1212         /* find the possible lowest possible multiplier */
1213         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1214                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1215                         break;
1216         }
1217         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1218                 return -EINVAL;
1219         mem_size = roundup(mem_size,
1220                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1221         *num_pages =
1222             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1223         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1224         *num_entries = mem_size / entry_size;
1225         return 0;
1226 }
1227
1228 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1229 {
1230         int i ;
1231         int status = 0;
1232         int max_ah;
1233         struct ocrdma_create_ah_tbl *cmd;
1234         struct ocrdma_create_ah_tbl_rsp *rsp;
1235         struct pci_dev *pdev = dev->nic_info.pdev;
1236         dma_addr_t pa;
1237         struct ocrdma_pbe *pbes;
1238
1239         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1240         if (!cmd)
1241                 return status;
1242
1243         max_ah = OCRDMA_MAX_AH;
1244         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1245
1246         /* number of PBEs in PBL */
1247         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1248                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1249                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1250
1251         /* page size */
1252         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1253                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1254                         break;
1255         }
1256         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1257                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1258
1259         /* ah_entry size */
1260         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1261                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1262                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1263
1264         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1265                                                 &dev->av_tbl.pbl.pa,
1266                                                 GFP_KERNEL);
1267         if (dev->av_tbl.pbl.va == NULL)
1268                 goto mem_err;
1269
1270         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1271                                             &pa, GFP_KERNEL);
1272         if (dev->av_tbl.va == NULL)
1273                 goto mem_err_ah;
1274         dev->av_tbl.pa = pa;
1275         dev->av_tbl.num_ah = max_ah;
1276         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1277
1278         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1279         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1280                 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1281                 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1282                 pa += PAGE_SIZE;
1283         }
1284         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1285         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1286         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1287         if (status)
1288                 goto mbx_err;
1289         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1290         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1291         kfree(cmd);
1292         return 0;
1293
1294 mbx_err:
1295         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1296                           dev->av_tbl.pa);
1297         dev->av_tbl.va = NULL;
1298 mem_err_ah:
1299         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1300                           dev->av_tbl.pbl.pa);
1301         dev->av_tbl.pbl.va = NULL;
1302         dev->av_tbl.size = 0;
1303 mem_err:
1304         kfree(cmd);
1305         return status;
1306 }
1307
1308 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1309 {
1310         struct ocrdma_delete_ah_tbl *cmd;
1311         struct pci_dev *pdev = dev->nic_info.pdev;
1312
1313         if (dev->av_tbl.va == NULL)
1314                 return;
1315
1316         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1317         if (!cmd)
1318                 return;
1319         cmd->ahid = dev->av_tbl.ahid;
1320
1321         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1322         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1323                           dev->av_tbl.pa);
1324         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1325                           dev->av_tbl.pbl.pa);
1326         kfree(cmd);
1327 }
1328
1329 /* Multiple CQs uses the EQ. This routine returns least used
1330  * EQ to associate with CQ. This will distributes the interrupt
1331  * processing and CPU load to associated EQ, vector and so to that CPU.
1332  */
1333 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1334 {
1335         int i, selected_eq = 0, cq_cnt = 0;
1336         u16 eq_id;
1337
1338         mutex_lock(&dev->dev_lock);
1339         cq_cnt = dev->eq_tbl[0].cq_cnt;
1340         eq_id = dev->eq_tbl[0].q.id;
1341         /* find the EQ which is has the least number of
1342          * CQs associated with it.
1343          */
1344         for (i = 0; i < dev->eq_cnt; i++) {
1345                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1346                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1347                         eq_id = dev->eq_tbl[i].q.id;
1348                         selected_eq = i;
1349                 }
1350         }
1351         dev->eq_tbl[selected_eq].cq_cnt += 1;
1352         mutex_unlock(&dev->dev_lock);
1353         return eq_id;
1354 }
1355
1356 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1357 {
1358         int i;
1359
1360         mutex_lock(&dev->dev_lock);
1361         i = ocrdma_get_eq_table_index(dev, eq_id);
1362         if (i == -EINVAL)
1363                 BUG();
1364         dev->eq_tbl[i].cq_cnt -= 1;
1365         mutex_unlock(&dev->dev_lock);
1366 }
1367
1368 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1369                          int entries, int dpp_cq, u16 pd_id)
1370 {
1371         int status = -ENOMEM; int max_hw_cqe;
1372         struct pci_dev *pdev = dev->nic_info.pdev;
1373         struct ocrdma_create_cq *cmd;
1374         struct ocrdma_create_cq_rsp *rsp;
1375         u32 hw_pages, cqe_size, page_size, cqe_count;
1376
1377         if (entries > dev->attr.max_cqe) {
1378                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1379                        __func__, dev->id, dev->attr.max_cqe, entries);
1380                 return -EINVAL;
1381         }
1382         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1383                 return -EINVAL;
1384
1385         if (dpp_cq) {
1386                 cq->max_hw_cqe = 1;
1387                 max_hw_cqe = 1;
1388                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1389                 hw_pages = 1;
1390         } else {
1391                 cq->max_hw_cqe = dev->attr.max_cqe;
1392                 max_hw_cqe = dev->attr.max_cqe;
1393                 cqe_size = sizeof(struct ocrdma_cqe);
1394                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1395         }
1396
1397         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1398
1399         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1400         if (!cmd)
1401                 return -ENOMEM;
1402         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1403                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1404         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1405         if (!cq->va) {
1406                 status = -ENOMEM;
1407                 goto mem_err;
1408         }
1409         memset(cq->va, 0, cq->len);
1410         page_size = cq->len / hw_pages;
1411         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1412                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1413         cmd->cmd.pgsz_pgcnt |= hw_pages;
1414         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1415
1416         cq->eqn = ocrdma_bind_eq(dev);
1417         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1418         cqe_count = cq->len / cqe_size;
1419         cq->cqe_cnt = cqe_count;
1420         if (cqe_count > 1024) {
1421                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1422                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1423         } else {
1424                 u8 count = 0;
1425                 switch (cqe_count) {
1426                 case 256:
1427                         count = 0;
1428                         break;
1429                 case 512:
1430                         count = 1;
1431                         break;
1432                 case 1024:
1433                         count = 2;
1434                         break;
1435                 default:
1436                         goto mbx_err;
1437                 }
1438                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1439         }
1440         /* shared eq between all the consumer cqs. */
1441         cmd->cmd.eqn = cq->eqn;
1442         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1443                 if (dpp_cq)
1444                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1445                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1446                 cq->phase_change = false;
1447                 cmd->cmd.cqe_count = (cq->len / cqe_size);
1448         } else {
1449                 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1450                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1451                 cq->phase_change = true;
1452         }
1453
1454         cmd->cmd.pd_id = pd_id; /* valid only for v3 */
1455         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1456         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1457         if (status)
1458                 goto mbx_err;
1459
1460         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1461         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1462         kfree(cmd);
1463         return 0;
1464 mbx_err:
1465         ocrdma_unbind_eq(dev, cq->eqn);
1466         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1467 mem_err:
1468         kfree(cmd);
1469         return status;
1470 }
1471
1472 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1473 {
1474         int status = -ENOMEM;
1475         struct ocrdma_destroy_cq *cmd;
1476
1477         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1478         if (!cmd)
1479                 return status;
1480         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1481                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1482
1483         cmd->bypass_flush_qid |=
1484             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1485             OCRDMA_DESTROY_CQ_QID_MASK;
1486
1487         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1488         ocrdma_unbind_eq(dev, cq->eqn);
1489         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1490         kfree(cmd);
1491         return status;
1492 }
1493
1494 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1495                           u32 pdid, int addr_check)
1496 {
1497         int status = -ENOMEM;
1498         struct ocrdma_alloc_lkey *cmd;
1499         struct ocrdma_alloc_lkey_rsp *rsp;
1500
1501         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1502         if (!cmd)
1503                 return status;
1504         cmd->pdid = pdid;
1505         cmd->pbl_sz_flags |= addr_check;
1506         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1507         cmd->pbl_sz_flags |=
1508             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1509         cmd->pbl_sz_flags |=
1510             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1511         cmd->pbl_sz_flags |=
1512             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1513         cmd->pbl_sz_flags |=
1514             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1515         cmd->pbl_sz_flags |=
1516             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1517
1518         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1519         if (status)
1520                 goto mbx_err;
1521         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1522         hwmr->lkey = rsp->lrkey;
1523 mbx_err:
1524         kfree(cmd);
1525         return status;
1526 }
1527
1528 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1529 {
1530         int status = -ENOMEM;
1531         struct ocrdma_dealloc_lkey *cmd;
1532
1533         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1534         if (!cmd)
1535                 return -ENOMEM;
1536         cmd->lkey = lkey;
1537         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1538         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1539         if (status)
1540                 goto mbx_err;
1541 mbx_err:
1542         kfree(cmd);
1543         return status;
1544 }
1545
1546 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1547                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1548 {
1549         int status = -ENOMEM;
1550         int i;
1551         struct ocrdma_reg_nsmr *cmd;
1552         struct ocrdma_reg_nsmr_rsp *rsp;
1553
1554         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1555         if (!cmd)
1556                 return -ENOMEM;
1557         cmd->num_pbl_pdid =
1558             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1559         cmd->fr_mr = hwmr->fr_mr;
1560
1561         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1562                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1563         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1564                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1565         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1566                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1567         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1568                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1569         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1570                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1571         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1572
1573         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1574         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1575                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1576         cmd->totlen_low = hwmr->len;
1577         cmd->totlen_high = upper_32_bits(hwmr->len);
1578         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1579         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1580         cmd->va_loaddr = (u32) hwmr->va;
1581         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1582
1583         for (i = 0; i < pbl_cnt; i++) {
1584                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1585                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1586         }
1587         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1588         if (status)
1589                 goto mbx_err;
1590         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1591         hwmr->lkey = rsp->lrkey;
1592 mbx_err:
1593         kfree(cmd);
1594         return status;
1595 }
1596
1597 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1598                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1599                                   u32 pbl_offset, u32 last)
1600 {
1601         int status = -ENOMEM;
1602         int i;
1603         struct ocrdma_reg_nsmr_cont *cmd;
1604
1605         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1606         if (!cmd)
1607                 return -ENOMEM;
1608         cmd->lrkey = hwmr->lkey;
1609         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1610             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1611         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1612
1613         for (i = 0; i < pbl_cnt; i++) {
1614                 cmd->pbl[i].lo =
1615                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1616                 cmd->pbl[i].hi =
1617                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1618         }
1619         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1620         if (status)
1621                 goto mbx_err;
1622 mbx_err:
1623         kfree(cmd);
1624         return status;
1625 }
1626
1627 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1628                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1629 {
1630         int status;
1631         u32 last = 0;
1632         u32 cur_pbl_cnt, pbl_offset;
1633         u32 pending_pbl_cnt = hwmr->num_pbls;
1634
1635         pbl_offset = 0;
1636         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1637         if (cur_pbl_cnt == pending_pbl_cnt)
1638                 last = 1;
1639
1640         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1641                                    cur_pbl_cnt, hwmr->pbe_size, last);
1642         if (status) {
1643                 pr_err("%s() status=%d\n", __func__, status);
1644                 return status;
1645         }
1646         /* if there is no more pbls to register then exit. */
1647         if (last)
1648                 return 0;
1649
1650         while (!last) {
1651                 pbl_offset += cur_pbl_cnt;
1652                 pending_pbl_cnt -= cur_pbl_cnt;
1653                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1654                 /* if we reach the end of the pbls, then need to set the last
1655                  * bit, indicating no more pbls to register for this memory key.
1656                  */
1657                 if (cur_pbl_cnt == pending_pbl_cnt)
1658                         last = 1;
1659
1660                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1661                                                 pbl_offset, last);
1662                 if (status)
1663                         break;
1664         }
1665         if (status)
1666                 pr_err("%s() err. status=%d\n", __func__, status);
1667
1668         return status;
1669 }
1670
1671 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1672 {
1673         struct ocrdma_qp *tmp;
1674         bool found = false;
1675         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1676                 if (qp == tmp) {
1677                         found = true;
1678                         break;
1679                 }
1680         }
1681         return found;
1682 }
1683
1684 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1685 {
1686         struct ocrdma_qp *tmp;
1687         bool found = false;
1688         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1689                 if (qp == tmp) {
1690                         found = true;
1691                         break;
1692                 }
1693         }
1694         return found;
1695 }
1696
1697 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1698 {
1699         bool found;
1700         unsigned long flags;
1701
1702         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1703         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1704         if (!found)
1705                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1706         if (!qp->srq) {
1707                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1708                 if (!found)
1709                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1710         }
1711         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1712 }
1713
1714 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1715 {
1716         qp->sq.head = 0;
1717         qp->sq.tail = 0;
1718         qp->rq.head = 0;
1719         qp->rq.tail = 0;
1720 }
1721
1722 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1723                            enum ib_qp_state *old_ib_state)
1724 {
1725         unsigned long flags;
1726         int status = 0;
1727         enum ocrdma_qp_state new_state;
1728         new_state = get_ocrdma_qp_state(new_ib_state);
1729
1730         /* sync with wqe and rqe posting */
1731         spin_lock_irqsave(&qp->q_lock, flags);
1732
1733         if (old_ib_state)
1734                 *old_ib_state = get_ibqp_state(qp->state);
1735         if (new_state == qp->state) {
1736                 spin_unlock_irqrestore(&qp->q_lock, flags);
1737                 return 1;
1738         }
1739
1740
1741         if (new_state == OCRDMA_QPS_INIT) {
1742                 ocrdma_init_hwq_ptr(qp);
1743                 ocrdma_del_flush_qp(qp);
1744         } else if (new_state == OCRDMA_QPS_ERR) {
1745                 ocrdma_flush_qp(qp);
1746         }
1747
1748         qp->state = new_state;
1749
1750         spin_unlock_irqrestore(&qp->q_lock, flags);
1751         return status;
1752 }
1753
1754 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1755 {
1756         u32 flags = 0;
1757         if (qp->cap_flags & OCRDMA_QP_INB_RD)
1758                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1759         if (qp->cap_flags & OCRDMA_QP_INB_WR)
1760                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1761         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1762                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1763         if (qp->cap_flags & OCRDMA_QP_LKEY0)
1764                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1765         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1766                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1767         return flags;
1768 }
1769
1770 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1771                                         struct ib_qp_init_attr *attrs,
1772                                         struct ocrdma_qp *qp)
1773 {
1774         int status;
1775         u32 len, hw_pages, hw_page_size;
1776         dma_addr_t pa;
1777         struct ocrdma_dev *dev = qp->dev;
1778         struct pci_dev *pdev = dev->nic_info.pdev;
1779         u32 max_wqe_allocated;
1780         u32 max_sges = attrs->cap.max_send_sge;
1781
1782         /* QP1 may exceed 127 */
1783         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
1784                                 dev->attr.max_wqe);
1785
1786         status = ocrdma_build_q_conf(&max_wqe_allocated,
1787                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1788         if (status) {
1789                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1790                        max_wqe_allocated);
1791                 return -EINVAL;
1792         }
1793         qp->sq.max_cnt = max_wqe_allocated;
1794         len = (hw_pages * hw_page_size);
1795
1796         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1797         if (!qp->sq.va)
1798                 return -EINVAL;
1799         memset(qp->sq.va, 0, len);
1800         qp->sq.len = len;
1801         qp->sq.pa = pa;
1802         qp->sq.entry_size = dev->attr.wqe_size;
1803         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1804
1805         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1806                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1807         cmd->num_wq_rq_pages |= (hw_pages <<
1808                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1809             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1810         cmd->max_sge_send_write |= (max_sges <<
1811                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1812             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1813         cmd->max_sge_send_write |= (max_sges <<
1814                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1815                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1816         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1817                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1818                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1819         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1820                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1821                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1822         return 0;
1823 }
1824
1825 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1826                                         struct ib_qp_init_attr *attrs,
1827                                         struct ocrdma_qp *qp)
1828 {
1829         int status;
1830         u32 len, hw_pages, hw_page_size;
1831         dma_addr_t pa = 0;
1832         struct ocrdma_dev *dev = qp->dev;
1833         struct pci_dev *pdev = dev->nic_info.pdev;
1834         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1835
1836         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1837                                      &hw_pages, &hw_page_size);
1838         if (status) {
1839                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1840                        attrs->cap.max_recv_wr + 1);
1841                 return status;
1842         }
1843         qp->rq.max_cnt = max_rqe_allocated;
1844         len = (hw_pages * hw_page_size);
1845
1846         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1847         if (!qp->rq.va)
1848                 return -ENOMEM;
1849         memset(qp->rq.va, 0, len);
1850         qp->rq.pa = pa;
1851         qp->rq.len = len;
1852         qp->rq.entry_size = dev->attr.rqe_size;
1853
1854         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1855         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1856                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1857         cmd->num_wq_rq_pages |=
1858             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1859             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1860         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1861                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1862                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1863         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1864                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1865                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1866         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1867                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1868                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1869         return 0;
1870 }
1871
1872 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1873                                          struct ocrdma_pd *pd,
1874                                          struct ocrdma_qp *qp,
1875                                          u8 enable_dpp_cq, u16 dpp_cq_id)
1876 {
1877         pd->num_dpp_qp--;
1878         qp->dpp_enabled = true;
1879         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1880         if (!enable_dpp_cq)
1881                 return;
1882         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1883         cmd->dpp_credits_cqid = dpp_cq_id;
1884         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1885                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1886 }
1887
1888 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1889                                         struct ocrdma_qp *qp)
1890 {
1891         struct ocrdma_dev *dev = qp->dev;
1892         struct pci_dev *pdev = dev->nic_info.pdev;
1893         dma_addr_t pa = 0;
1894         int ird_page_size = dev->attr.ird_page_size;
1895         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
1896         struct ocrdma_hdr_wqe *rqe;
1897         int i  = 0;
1898
1899         if (dev->attr.ird == 0)
1900                 return 0;
1901
1902         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1903                                         &pa, GFP_KERNEL);
1904         if (!qp->ird_q_va)
1905                 return -ENOMEM;
1906         memset(qp->ird_q_va, 0, ird_q_len);
1907         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1908                              pa, ird_page_size);
1909         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
1910                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
1911                         (i * dev->attr.rqe_size));
1912                 rqe->cw = 0;
1913                 rqe->cw |= 2;
1914                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
1915                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
1916                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
1917         }
1918         return 0;
1919 }
1920
1921 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1922                                      struct ocrdma_qp *qp,
1923                                      struct ib_qp_init_attr *attrs,
1924                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
1925 {
1926         u32 max_wqe_allocated, max_rqe_allocated;
1927         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1928         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1929         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1930         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1931         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1932         qp->dpp_enabled = false;
1933         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1934                 qp->dpp_enabled = true;
1935                 *dpp_credit_lmt = (rsp->dpp_response &
1936                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1937                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1938                 *dpp_offset = (rsp->dpp_response &
1939                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1940                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1941         }
1942         max_wqe_allocated =
1943                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1944         max_wqe_allocated = 1 << max_wqe_allocated;
1945         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1946
1947         qp->sq.max_cnt = max_wqe_allocated;
1948         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1949
1950         if (!attrs->srq) {
1951                 qp->rq.max_cnt = max_rqe_allocated;
1952                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
1953         }
1954 }
1955
1956 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1957                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1958                          u16 *dpp_credit_lmt)
1959 {
1960         int status = -ENOMEM;
1961         u32 flags = 0;
1962         struct ocrdma_dev *dev = qp->dev;
1963         struct ocrdma_pd *pd = qp->pd;
1964         struct pci_dev *pdev = dev->nic_info.pdev;
1965         struct ocrdma_cq *cq;
1966         struct ocrdma_create_qp_req *cmd;
1967         struct ocrdma_create_qp_rsp *rsp;
1968         int qptype;
1969
1970         switch (attrs->qp_type) {
1971         case IB_QPT_GSI:
1972                 qptype = OCRDMA_QPT_GSI;
1973                 break;
1974         case IB_QPT_RC:
1975                 qptype = OCRDMA_QPT_RC;
1976                 break;
1977         case IB_QPT_UD:
1978                 qptype = OCRDMA_QPT_UD;
1979                 break;
1980         default:
1981                 return -EINVAL;
1982         }
1983
1984         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
1985         if (!cmd)
1986                 return status;
1987         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
1988                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
1989         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
1990         if (status)
1991                 goto sq_err;
1992
1993         if (attrs->srq) {
1994                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
1995                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
1996                 cmd->rq_addr[0].lo = srq->id;
1997                 qp->srq = srq;
1998         } else {
1999                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2000                 if (status)
2001                         goto rq_err;
2002         }
2003
2004         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2005         if (status)
2006                 goto mbx_err;
2007
2008         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2009                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2010
2011         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2012
2013         cmd->max_sge_recv_flags |= flags;
2014         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2015                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2016                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2017         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2018                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2019                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2020         cq = get_ocrdma_cq(attrs->send_cq);
2021         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2022                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2023         qp->sq_cq = cq;
2024         cq = get_ocrdma_cq(attrs->recv_cq);
2025         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2026                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2027         qp->rq_cq = cq;
2028
2029         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2030             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2031                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2032                                              dpp_cq_id);
2033         }
2034
2035         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2036         if (status)
2037                 goto mbx_err;
2038         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2039         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2040         qp->state = OCRDMA_QPS_RST;
2041         kfree(cmd);
2042         return 0;
2043 mbx_err:
2044         if (qp->rq.va)
2045                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2046 rq_err:
2047         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2048         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2049 sq_err:
2050         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2051         kfree(cmd);
2052         return status;
2053 }
2054
2055 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2056                         struct ocrdma_qp_params *param)
2057 {
2058         int status = -ENOMEM;
2059         struct ocrdma_query_qp *cmd;
2060         struct ocrdma_query_qp_rsp *rsp;
2061
2062         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2063         if (!cmd)
2064                 return status;
2065         cmd->qp_id = qp->id;
2066         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2067         if (status)
2068                 goto mbx_err;
2069         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2070         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2071 mbx_err:
2072         kfree(cmd);
2073         return status;
2074 }
2075
2076 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2077                                 struct ocrdma_modify_qp *cmd,
2078                                 struct ib_qp_attr *attrs)
2079 {
2080         int status;
2081         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2082         union ib_gid sgid, zgid;
2083         u32 vlan_id;
2084         u8 mac_addr[6];
2085
2086         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2087                 return -EINVAL;
2088         cmd->params.tclass_sq_psn |=
2089             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2090         cmd->params.rnt_rc_sl_fl |=
2091             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2092         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2093         cmd->params.hop_lmt_rq_psn |=
2094             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2095         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2096         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2097                sizeof(cmd->params.dgid));
2098         status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2099                          ah_attr->grh.sgid_index, &sgid);
2100         if (status)
2101                 return status;
2102
2103         memset(&zgid, 0, sizeof(zgid));
2104         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2105                 return -EINVAL;
2106
2107         qp->sgid_idx = ah_attr->grh.sgid_index;
2108         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2109         ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2110         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2111                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2112         /* convert them to LE format. */
2113         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2114         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2115         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2116         vlan_id = ah_attr->vlan_id;
2117         if (vlan_id && (vlan_id < 0x1000)) {
2118                 cmd->params.vlan_dmac_b4_to_b5 |=
2119                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2120                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2121         }
2122         return 0;
2123 }
2124
2125 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2126                                 struct ocrdma_modify_qp *cmd,
2127                                 struct ib_qp_attr *attrs, int attr_mask)
2128 {
2129         int status = 0;
2130
2131         if (attr_mask & IB_QP_PKEY_INDEX) {
2132                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2133                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2134                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2135         }
2136         if (attr_mask & IB_QP_QKEY) {
2137                 qp->qkey = attrs->qkey;
2138                 cmd->params.qkey = attrs->qkey;
2139                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2140         }
2141         if (attr_mask & IB_QP_AV) {
2142                 status = ocrdma_set_av_params(qp, cmd, attrs);
2143                 if (status)
2144                         return status;
2145         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2146                 /* set the default mac address for UD, GSI QPs */
2147                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2148                         (qp->dev->nic_info.mac_addr[1] << 8) |
2149                         (qp->dev->nic_info.mac_addr[2] << 16) |
2150                         (qp->dev->nic_info.mac_addr[3] << 24);
2151                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2152                                         (qp->dev->nic_info.mac_addr[5] << 8);
2153         }
2154         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2155             attrs->en_sqd_async_notify) {
2156                 cmd->params.max_sge_recv_flags |=
2157                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2158                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2159         }
2160         if (attr_mask & IB_QP_DEST_QPN) {
2161                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2162                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2163                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2164         }
2165         if (attr_mask & IB_QP_PATH_MTU) {
2166                 if (attrs->path_mtu < IB_MTU_256 ||
2167                     attrs->path_mtu > IB_MTU_4096) {
2168                         status = -EINVAL;
2169                         goto pmtu_err;
2170                 }
2171                 cmd->params.path_mtu_pkey_indx |=
2172                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2173                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2174                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2175                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2176         }
2177         if (attr_mask & IB_QP_TIMEOUT) {
2178                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2179                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2180                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2181         }
2182         if (attr_mask & IB_QP_RETRY_CNT) {
2183                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2184                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2185                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2186                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2187         }
2188         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2189                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2190                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2191                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2192                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2193         }
2194         if (attr_mask & IB_QP_RNR_RETRY) {
2195                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2196                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2197                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2198                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2199         }
2200         if (attr_mask & IB_QP_SQ_PSN) {
2201                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2202                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2203         }
2204         if (attr_mask & IB_QP_RQ_PSN) {
2205                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2206                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2207         }
2208         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2209                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2210                         status = -EINVAL;
2211                         goto pmtu_err;
2212                 }
2213                 qp->max_ord = attrs->max_rd_atomic;
2214                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2215         }
2216         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2217                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2218                         status = -EINVAL;
2219                         goto pmtu_err;
2220                 }
2221                 qp->max_ird = attrs->max_dest_rd_atomic;
2222                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2223         }
2224         cmd->params.max_ord_ird = (qp->max_ord <<
2225                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2226                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2227 pmtu_err:
2228         return status;
2229 }
2230
2231 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2232                          struct ib_qp_attr *attrs, int attr_mask)
2233 {
2234         int status = -ENOMEM;
2235         struct ocrdma_modify_qp *cmd;
2236
2237         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2238         if (!cmd)
2239                 return status;
2240
2241         cmd->params.id = qp->id;
2242         cmd->flags = 0;
2243         if (attr_mask & IB_QP_STATE) {
2244                 cmd->params.max_sge_recv_flags |=
2245                     (get_ocrdma_qp_state(attrs->qp_state) <<
2246                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2247                     OCRDMA_QP_PARAMS_STATE_MASK;
2248                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2249         } else {
2250                 cmd->params.max_sge_recv_flags |=
2251                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2252                     OCRDMA_QP_PARAMS_STATE_MASK;
2253         }
2254
2255         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2256         if (status)
2257                 goto mbx_err;
2258         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2259         if (status)
2260                 goto mbx_err;
2261
2262 mbx_err:
2263         kfree(cmd);
2264         return status;
2265 }
2266
2267 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2268 {
2269         int status = -ENOMEM;
2270         struct ocrdma_destroy_qp *cmd;
2271         struct pci_dev *pdev = dev->nic_info.pdev;
2272
2273         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2274         if (!cmd)
2275                 return status;
2276         cmd->qp_id = qp->id;
2277         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2278         if (status)
2279                 goto mbx_err;
2280
2281 mbx_err:
2282         kfree(cmd);
2283         if (qp->sq.va)
2284                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2285         if (!qp->srq && qp->rq.va)
2286                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2287         if (qp->dpp_enabled)
2288                 qp->pd->num_dpp_qp++;
2289         return status;
2290 }
2291
2292 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2293                           struct ib_srq_init_attr *srq_attr,
2294                           struct ocrdma_pd *pd)
2295 {
2296         int status = -ENOMEM;
2297         int hw_pages, hw_page_size;
2298         int len;
2299         struct ocrdma_create_srq_rsp *rsp;
2300         struct ocrdma_create_srq *cmd;
2301         dma_addr_t pa;
2302         struct pci_dev *pdev = dev->nic_info.pdev;
2303         u32 max_rqe_allocated;
2304
2305         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2306         if (!cmd)
2307                 return status;
2308
2309         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2310         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2311         status = ocrdma_build_q_conf(&max_rqe_allocated,
2312                                 dev->attr.rqe_size,
2313                                 &hw_pages, &hw_page_size);
2314         if (status) {
2315                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2316                        srq_attr->attr.max_wr);
2317                 status = -EINVAL;
2318                 goto ret;
2319         }
2320         len = hw_pages * hw_page_size;
2321         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2322         if (!srq->rq.va) {
2323                 status = -ENOMEM;
2324                 goto ret;
2325         }
2326         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2327
2328         srq->rq.entry_size = dev->attr.rqe_size;
2329         srq->rq.pa = pa;
2330         srq->rq.len = len;
2331         srq->rq.max_cnt = max_rqe_allocated;
2332
2333         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2334         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2335                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2336
2337         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2338                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2339         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2340                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2341                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2342         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2343
2344         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2345         if (status)
2346                 goto mbx_err;
2347         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2348         srq->id = rsp->id;
2349         srq->rq.dbid = rsp->id;
2350         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2351                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2352                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2353         max_rqe_allocated = (1 << max_rqe_allocated);
2354         srq->rq.max_cnt = max_rqe_allocated;
2355         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2356         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2357                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2358                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2359         goto ret;
2360 mbx_err:
2361         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2362 ret:
2363         kfree(cmd);
2364         return status;
2365 }
2366
2367 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2368 {
2369         int status = -ENOMEM;
2370         struct ocrdma_modify_srq *cmd;
2371         struct ocrdma_pd *pd = srq->pd;
2372         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2373
2374         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2375         if (!cmd)
2376                 return status;
2377         cmd->id = srq->id;
2378         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2379             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2380         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2381         kfree(cmd);
2382         return status;
2383 }
2384
2385 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2386 {
2387         int status = -ENOMEM;
2388         struct ocrdma_query_srq *cmd;
2389         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2390
2391         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2392         if (!cmd)
2393                 return status;
2394         cmd->id = srq->rq.dbid;
2395         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2396         if (status == 0) {
2397                 struct ocrdma_query_srq_rsp *rsp =
2398                     (struct ocrdma_query_srq_rsp *)cmd;
2399                 srq_attr->max_sge =
2400                     rsp->srq_lmt_max_sge &
2401                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2402                 srq_attr->max_wr =
2403                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2404                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2405                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2406         }
2407         kfree(cmd);
2408         return status;
2409 }
2410
2411 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2412 {
2413         int status = -ENOMEM;
2414         struct ocrdma_destroy_srq *cmd;
2415         struct pci_dev *pdev = dev->nic_info.pdev;
2416         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2417         if (!cmd)
2418                 return status;
2419         cmd->id = srq->id;
2420         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2421         if (srq->rq.va)
2422                 dma_free_coherent(&pdev->dev, srq->rq.len,
2423                                   srq->rq.va, srq->rq.pa);
2424         kfree(cmd);
2425         return status;
2426 }
2427
2428 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2429 {
2430         int i;
2431         int status = -EINVAL;
2432         struct ocrdma_av *av;
2433         unsigned long flags;
2434
2435         av = dev->av_tbl.va;
2436         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2437         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2438                 if (av->valid == 0) {
2439                         av->valid = OCRDMA_AV_VALID;
2440                         ah->av = av;
2441                         ah->id = i;
2442                         status = 0;
2443                         break;
2444                 }
2445                 av++;
2446         }
2447         if (i == dev->av_tbl.num_ah)
2448                 status = -EAGAIN;
2449         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2450         return status;
2451 }
2452
2453 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2454 {
2455         unsigned long flags;
2456         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2457         ah->av->valid = 0;
2458         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2459         return 0;
2460 }
2461
2462 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2463 {
2464         int num_eq, i, status = 0;
2465         int irq;
2466         unsigned long flags = 0;
2467
2468         num_eq = dev->nic_info.msix.num_vectors -
2469                         dev->nic_info.msix.start_vector;
2470         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2471                 num_eq = 1;
2472                 flags = IRQF_SHARED;
2473         } else {
2474                 num_eq = min_t(u32, num_eq, num_online_cpus());
2475         }
2476
2477         if (!num_eq)
2478                 return -EINVAL;
2479
2480         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2481         if (!dev->eq_tbl)
2482                 return -ENOMEM;
2483
2484         for (i = 0; i < num_eq; i++) {
2485                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2486                                           OCRDMA_EQ_LEN);
2487                 if (status) {
2488                         status = -EINVAL;
2489                         break;
2490                 }
2491                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2492                         dev->id, i);
2493                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2494                 status = request_irq(irq, ocrdma_irq_handler, flags,
2495                                      dev->eq_tbl[i].irq_name,
2496                                      &dev->eq_tbl[i]);
2497                 if (status)
2498                         goto done;
2499                 dev->eq_cnt += 1;
2500         }
2501         /* one eq is sufficient for data path to work */
2502         return 0;
2503 done:
2504         ocrdma_destroy_eqs(dev);
2505         return status;
2506 }
2507
2508 int ocrdma_init_hw(struct ocrdma_dev *dev)
2509 {
2510         int status;
2511
2512         /* create the eqs  */
2513         status = ocrdma_create_eqs(dev);
2514         if (status)
2515                 goto qpeq_err;
2516         status = ocrdma_create_mq(dev);
2517         if (status)
2518                 goto mq_err;
2519         status = ocrdma_mbx_query_fw_config(dev);
2520         if (status)
2521                 goto conf_err;
2522         status = ocrdma_mbx_query_dev(dev);
2523         if (status)
2524                 goto conf_err;
2525         status = ocrdma_mbx_query_fw_ver(dev);
2526         if (status)
2527                 goto conf_err;
2528         status = ocrdma_mbx_create_ah_tbl(dev);
2529         if (status)
2530                 goto conf_err;
2531         return 0;
2532
2533 conf_err:
2534         ocrdma_destroy_mq(dev);
2535 mq_err:
2536         ocrdma_destroy_eqs(dev);
2537 qpeq_err:
2538         pr_err("%s() status=%d\n", __func__, status);
2539         return status;
2540 }
2541
2542 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2543 {
2544         ocrdma_mbx_delete_ah_tbl(dev);
2545
2546         /* cleanup the eqs */
2547         ocrdma_destroy_eqs(dev);
2548
2549         /* cleanup the control path */
2550         ocrdma_destroy_mq(dev);
2551 }