2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the
36 * QLogic_IB 6120 PCIe chip.
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <rdma/ib_verbs.h>
45 #include "qib_6120_regs.h"
47 static void qib_6120_setup_setextled(struct qib_pportdata *, u32);
48 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op);
49 static u8 qib_6120_phys_portstate(u64);
50 static u32 qib_6120_iblink_state(u64);
53 * This file contains all the chip-specific register information and
54 * access functions for the QLogic QLogic_IB PCI-Express chip.
58 /* KREG_IDX uses machine-generated #defines */
59 #define KREG_IDX(regname) (QIB_6120_##regname##_OFFS / sizeof(u64))
61 /* Use defines to tie machine-generated names to lower-case names */
62 #define kr_extctrl KREG_IDX(EXTCtrl)
63 #define kr_extstatus KREG_IDX(EXTStatus)
64 #define kr_gpio_clear KREG_IDX(GPIOClear)
65 #define kr_gpio_mask KREG_IDX(GPIOMask)
66 #define kr_gpio_out KREG_IDX(GPIOOut)
67 #define kr_gpio_status KREG_IDX(GPIOStatus)
68 #define kr_rcvctrl KREG_IDX(RcvCtrl)
69 #define kr_sendctrl KREG_IDX(SendCtrl)
70 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
71 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
72 #define kr_ibcstatus KREG_IDX(IBCStatus)
73 #define kr_ibcctrl KREG_IDX(IBCCtrl)
74 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
75 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
76 #define kr_counterregbase KREG_IDX(CntrRegBase)
77 #define kr_palign KREG_IDX(PageAlign)
78 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
79 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
80 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
81 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
82 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
83 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
84 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
85 #define kr_scratch KREG_IDX(Scratch)
86 #define kr_sendctrl KREG_IDX(SendCtrl)
87 #define kr_sendpioavailaddr KREG_IDX(SendPIOAvailAddr)
88 #define kr_sendpiobufbase KREG_IDX(SendPIOBufBase)
89 #define kr_sendpiobufcnt KREG_IDX(SendPIOBufCnt)
90 #define kr_sendpiosize KREG_IDX(SendPIOSize)
91 #define kr_sendregbase KREG_IDX(SendRegBase)
92 #define kr_userregbase KREG_IDX(UserRegBase)
93 #define kr_control KREG_IDX(Control)
94 #define kr_intclear KREG_IDX(IntClear)
95 #define kr_intmask KREG_IDX(IntMask)
96 #define kr_intstatus KREG_IDX(IntStatus)
97 #define kr_errclear KREG_IDX(ErrClear)
98 #define kr_errmask KREG_IDX(ErrMask)
99 #define kr_errstatus KREG_IDX(ErrStatus)
100 #define kr_hwerrclear KREG_IDX(HwErrClear)
101 #define kr_hwerrmask KREG_IDX(HwErrMask)
102 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
103 #define kr_revision KREG_IDX(Revision)
104 #define kr_portcnt KREG_IDX(PortCnt)
105 #define kr_serdes_cfg0 KREG_IDX(SerdesCfg0)
106 #define kr_serdes_cfg1 (kr_serdes_cfg0 + 1)
107 #define kr_serdes_stat KREG_IDX(SerdesStat)
108 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
110 /* These must only be written via qib_write_kreg_ctxt() */
111 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
112 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
114 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
115 QIB_6120_LBIntCnt_OFFS) / sizeof(u64))
117 #define cr_badformat CREG_IDX(RxBadFormatCnt)
118 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
119 #define cr_errlink CREG_IDX(RxLinkProblemCnt)
120 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
121 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
122 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlErrCnt)
123 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
124 #define cr_errslen CREG_IDX(TxLenErrCnt)
125 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
126 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
127 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
128 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
129 #define cr_lbint CREG_IDX(LBIntCnt)
130 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
131 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
132 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
133 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
134 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
135 #define cr_pktsend CREG_IDX(TxDataPktCnt)
136 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
137 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
138 #define cr_rcvebp CREG_IDX(RxEBPCnt)
139 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
140 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
141 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
142 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
143 #define cr_wordrcv CREG_IDX(RxDwordCnt)
144 #define cr_wordsend CREG_IDX(TxDwordCnt)
145 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
146 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
147 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
148 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
149 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
151 #define SYM_RMASK(regname, fldname) ((u64) \
152 QIB_6120_##regname##_##fldname##_RMASK)
153 #define SYM_MASK(regname, fldname) ((u64) \
154 QIB_6120_##regname##_##fldname##_RMASK << \
155 QIB_6120_##regname##_##fldname##_LSB)
156 #define SYM_LSB(regname, fldname) (QIB_6120_##regname##_##fldname##_LSB)
158 #define SYM_FIELD(value, regname, fldname) ((u64) \
159 (((value) >> SYM_LSB(regname, fldname)) & \
160 SYM_RMASK(regname, fldname)))
161 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
162 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
164 /* link training states, from IBC */
165 #define IB_6120_LT_STATE_DISABLED 0x00
166 #define IB_6120_LT_STATE_LINKUP 0x01
167 #define IB_6120_LT_STATE_POLLACTIVE 0x02
168 #define IB_6120_LT_STATE_POLLQUIET 0x03
169 #define IB_6120_LT_STATE_SLEEPDELAY 0x04
170 #define IB_6120_LT_STATE_SLEEPQUIET 0x05
171 #define IB_6120_LT_STATE_CFGDEBOUNCE 0x08
172 #define IB_6120_LT_STATE_CFGRCVFCFG 0x09
173 #define IB_6120_LT_STATE_CFGWAITRMT 0x0a
174 #define IB_6120_LT_STATE_CFGIDLE 0x0b
175 #define IB_6120_LT_STATE_RECOVERRETRAIN 0x0c
176 #define IB_6120_LT_STATE_RECOVERWAITRMT 0x0e
177 #define IB_6120_LT_STATE_RECOVERIDLE 0x0f
179 /* link state machine states from IBC */
180 #define IB_6120_L_STATE_DOWN 0x0
181 #define IB_6120_L_STATE_INIT 0x1
182 #define IB_6120_L_STATE_ARM 0x2
183 #define IB_6120_L_STATE_ACTIVE 0x3
184 #define IB_6120_L_STATE_ACT_DEFER 0x4
186 static const u8 qib_6120_physportstate[0x20] = {
187 [IB_6120_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
188 [IB_6120_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
189 [IB_6120_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
190 [IB_6120_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
191 [IB_6120_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
192 [IB_6120_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
193 [IB_6120_LT_STATE_CFGDEBOUNCE] =
194 IB_PHYSPORTSTATE_CFG_TRAIN,
195 [IB_6120_LT_STATE_CFGRCVFCFG] =
196 IB_PHYSPORTSTATE_CFG_TRAIN,
197 [IB_6120_LT_STATE_CFGWAITRMT] =
198 IB_PHYSPORTSTATE_CFG_TRAIN,
199 [IB_6120_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
200 [IB_6120_LT_STATE_RECOVERRETRAIN] =
201 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
202 [IB_6120_LT_STATE_RECOVERWAITRMT] =
203 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
204 [IB_6120_LT_STATE_RECOVERIDLE] =
205 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
206 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
207 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
208 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
209 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
210 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
211 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
212 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
213 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
217 struct qib_chip_specific {
218 u64 __iomem *cregbase;
221 void *dummy_hdrq; /* used after ctxt close */
222 dma_addr_t dummy_hdrq_phys;
223 spinlock_t kernel_tid_lock; /* no back to back kernel TID writes */
224 spinlock_t user_tid_lock; /* no back to back user TID writes */
225 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
226 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
229 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
230 u64 gpio_mask; /* shadow the gpio mask register */
231 u64 extctrl; /* shadow the gpio output enable, etc... */
233 * these 5 fields are used to establish deltas for IB symbol
234 * errors and linkrecovery errors. They can be reported on
235 * some chips during link negotiation prior to INIT, and with
236 * DDR when faking DDR negotiations with non-IBTA switches.
237 * The chip counters are adjusted at driver unload if there is
245 u64 ibcctrl; /* shadow for kr_ibcctrl */
246 u32 lastlinkrecov; /* link recovery issue */
252 /* used with gpio interrupts to implement IB counters */
253 u32 rxfc_unsupvl_errs;
254 u32 overrun_thresh_errs;
256 * these count only cases where _successive_ LocalLinkIntegrity
257 * errors were seen in the receive headers of IB standard packets
262 u64 sword; /* total dwords sent (sample result) */
263 u64 rword; /* total dwords received (sample result) */
264 u64 spkts; /* total packets sent (sample result) */
265 u64 rpkts; /* total packets received (sample result) */
266 u64 xmit_wait; /* # of ticks no data sent (sample result) */
267 struct timer_list pma_timer;
270 u8 pma_sample_status;
274 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
275 /* cycle through TS1/TS2 till OK */
276 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
277 /* wait for TS1, then go on */
278 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
279 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
281 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
282 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
283 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
284 #define QLOGIC_IB_IBCC_LINKCMD_SHIFT 18
287 * We could have a single register get/put routine, that takes a group type,
288 * but this is somewhat clearer and cleaner. It also gives us some error
289 * checking. 64 bit register reads should always work, but are inefficient
290 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
291 * so we use kreg32 wherever possible. User register and counter register
292 * reads are always 32 bit reads, so only one form of those routines.
296 * qib_read_ureg32 - read 32-bit virtualized per-context register
298 * @regno: register number
299 * @ctxt: context number
301 * Return the contents of a register that is virtualized to be per context.
302 * Returns -1 on errors (not distinguishable from valid contents at
303 * runtime; we may add a separate error variable at some point).
305 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
306 enum qib_ureg regno, int ctxt)
308 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
312 return readl(regno + (u64 __iomem *)
313 ((char __iomem *)dd->userbase +
314 dd->ureg_align * ctxt));
316 return readl(regno + (u64 __iomem *)
318 (char __iomem *)dd->kregbase +
319 dd->ureg_align * ctxt));
323 * qib_write_ureg - write 32-bit virtualized per-context register
325 * @regno: register number
329 * Write the contents of a register that is virtualized to be per context.
331 static inline void qib_write_ureg(const struct qib_devdata *dd,
332 enum qib_ureg regno, u64 value, int ctxt)
336 ubase = (u64 __iomem *)
337 ((char __iomem *) dd->userbase +
338 dd->ureg_align * ctxt);
340 ubase = (u64 __iomem *)
342 (char __iomem *) dd->kregbase +
343 dd->ureg_align * ctxt);
345 if (dd->kregbase && (dd->flags & QIB_PRESENT))
346 writeq(value, &ubase[regno]);
349 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
352 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
354 return readl((u32 __iomem *)&dd->kregbase[regno]);
357 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
360 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
363 return readq(&dd->kregbase[regno]);
366 static inline void qib_write_kreg(const struct qib_devdata *dd,
367 const u16 regno, u64 value)
369 if (dd->kregbase && (dd->flags & QIB_PRESENT))
370 writeq(value, &dd->kregbase[regno]);
374 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
375 * @dd: the qlogic_ib device
376 * @regno: the register number to write
377 * @ctxt: the context containing the register
378 * @value: the value to write
380 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
381 const u16 regno, unsigned ctxt,
384 qib_write_kreg(dd, regno + ctxt, value);
387 static inline void write_6120_creg(const struct qib_devdata *dd,
388 u16 regno, u64 value)
390 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
391 writeq(value, &dd->cspec->cregbase[regno]);
394 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno)
396 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
398 return readq(&dd->cspec->cregbase[regno]);
401 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno)
403 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
405 return readl(&dd->cspec->cregbase[regno]);
408 /* kr_control bits */
409 #define QLOGIC_IB_C_RESET 1U
411 /* kr_intstatus, kr_intclear, kr_intmask bits */
412 #define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1)
413 #define QLOGIC_IB_I_RCVURG_SHIFT 0
414 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1)
415 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 12
417 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
418 #define QLOGIC_IB_C_LINKENABLE 0x00000004
419 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
420 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
421 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
422 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
423 #define QLOGIC_IB_I_BITSEXTANT \
424 ((QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
425 (QLOGIC_IB_I_RCVAVAIL_MASK << \
426 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
427 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
428 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO)
430 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
431 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
432 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
433 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
434 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
435 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
436 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
437 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
438 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
439 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
440 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
441 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
442 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
445 /* kr_extstatus bits */
446 #define QLOGIC_IB_EXTS_FREQSEL 0x2
447 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
448 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
449 #define QLOGIC_IB_EXTS_MEMBIST_FOUND 0x0000000000008000
451 /* kr_xgxsconfig bits */
452 #define QLOGIC_IB_XGXS_RESET 0x5ULL
454 #define _QIB_GPIO_SDA_NUM 1
455 #define _QIB_GPIO_SCL_NUM 0
457 /* Bits in GPIO for the added IB link interrupts */
458 #define GPIO_RXUVL_BIT 3
459 #define GPIO_OVRUN_BIT 4
460 #define GPIO_LLI_BIT 5
461 #define GPIO_ERRINTR_MASK 0x38
464 #define QLOGIC_IB_RT_BUFSIZE_MASK 0xe0000000ULL
465 #define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) \
466 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
467 #define QLOGIC_IB_RT_BUFSIZE(tid) (1 << QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid))
468 #define QLOGIC_IB_RT_IS_VALID(tid) \
469 (((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) && \
470 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) != QLOGIC_IB_RT_BUFSIZE_MASK)))
471 #define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
472 #define QLOGIC_IB_RT_ADDR_SHIFT 10
474 #define QLOGIC_IB_R_INTRAVAIL_SHIFT 16
475 #define QLOGIC_IB_R_TAILUPD_SHIFT 31
476 #define IBA6120_R_PKEY_DIS_SHIFT 30
478 #define PBC_6120_VL15_SEND_CTRL (1ULL << 31) /* pbc; VL15; link_buf only */
480 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
481 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
483 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
484 ((1ULL << (SYM_LSB(regname, fldname) + (bit)))))
486 #define TXEMEMPARITYERR_PIOBUF \
487 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
488 #define TXEMEMPARITYERR_PIOPBC \
489 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
490 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
491 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
493 #define RXEMEMPARITYERR_RCVBUF \
494 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
495 #define RXEMEMPARITYERR_LOOKUPQ \
496 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
497 #define RXEMEMPARITYERR_EXPTID \
498 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
499 #define RXEMEMPARITYERR_EAGERTID \
500 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
501 #define RXEMEMPARITYERR_FLAGBUF \
502 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
503 #define RXEMEMPARITYERR_DATAINFO \
504 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
505 #define RXEMEMPARITYERR_HDRINFO \
506 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
508 /* 6120 specific hardware errors... */
509 static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = {
510 /* generic hardware errors */
511 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
512 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
514 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
515 "TXE PIOBUF Memory Parity"),
516 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
517 "TXE PIOPBC Memory Parity"),
518 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
519 "TXE PIOLAUNCHFIFO Memory Parity"),
521 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
522 "RXE RCVBUF Memory Parity"),
523 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
524 "RXE LOOKUPQ Memory Parity"),
525 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
526 "RXE EAGERTID Memory Parity"),
527 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
528 "RXE EXPTID Memory Parity"),
529 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
530 "RXE FLAGBUF Memory Parity"),
531 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
532 "RXE DATAINFO Memory Parity"),
533 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
534 "RXE HDRINFO Memory Parity"),
536 /* chip-specific hardware errors */
537 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
538 "PCIe Poisoned TLP"),
539 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
540 "PCIe completion timeout"),
542 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
543 * parity or memory parity error failures, because most likely we
544 * won't be able to talk to the core of the chip. Nonetheless, we
545 * might see them, if they are in parts of the PCIe core that aren't
548 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
550 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
552 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
553 "PCIe XTLH core parity"),
554 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
555 "PCIe ADM TX core parity"),
556 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
557 "PCIe ADM RX core parity"),
558 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
562 #define TXE_PIO_PARITY (TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC)
563 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
564 QLOGIC_IB_HWE_COREPLL_RFSLIP)
566 /* variables for sanity checking interrupt and errors */
567 #define IB_HWE_BITSEXTANT \
568 (HWE_MASK(RXEMemParityErr) | \
569 HWE_MASK(TXEMemParityErr) | \
570 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
571 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
572 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
573 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
574 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
575 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
576 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
577 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
578 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
579 HWE_MASK(PowerOnBISTFailed) | \
580 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
581 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
582 QLOGIC_IB_HWE_SERDESPLLFAILED | \
583 HWE_MASK(IBCBusToSPCParityErr) | \
584 HWE_MASK(IBCBusFromSPCParityErr))
586 #define IB_E_BITSEXTANT \
587 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
588 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
589 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
590 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
591 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
592 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
593 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
594 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
595 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
596 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendMaxPktLenErr) | \
597 ERR_MASK(SendUnderRunErr) | ERR_MASK(SendPktLenErr) | \
598 ERR_MASK(SendDroppedSmpPktErr) | \
599 ERR_MASK(SendDroppedDataPktErr) | \
600 ERR_MASK(SendPioArmLaunchErr) | \
601 ERR_MASK(SendUnexpectedPktNumErr) | \
602 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(IBStatusChanged) | \
603 ERR_MASK(InvalidAddrErr) | ERR_MASK(ResetNegated) | \
604 ERR_MASK(HardwareErr))
606 #define QLOGIC_IB_E_PKTERRS ( \
607 ERR_MASK(SendPktLenErr) | \
608 ERR_MASK(SendDroppedDataPktErr) | \
609 ERR_MASK(RcvVCRCErr) | \
610 ERR_MASK(RcvICRCErr) | \
611 ERR_MASK(RcvShortPktLenErr) | \
614 /* These are all rcv-related errors which we want to count for stats */
615 #define E_SUM_PKTERRS \
616 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
617 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
618 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
619 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
620 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
621 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
623 /* These are all send-related errors which we want to count for stats */
625 (ERR_MASK(SendPioArmLaunchErr) | \
626 ERR_MASK(SendUnexpectedPktNumErr) | \
627 ERR_MASK(SendDroppedDataPktErr) | \
628 ERR_MASK(SendDroppedSmpPktErr) | \
629 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
630 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
631 ERR_MASK(InvalidAddrErr))
634 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
635 * errors not related to freeze and cancelling buffers. Can't ignore
636 * armlaunch because could get more while still cleaning up, and need
637 * to cancel those as they happen.
639 #define E_SPKT_ERRS_IGNORE \
640 (ERR_MASK(SendDroppedDataPktErr) | \
641 ERR_MASK(SendDroppedSmpPktErr) | \
642 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
643 ERR_MASK(SendPktLenErr))
646 * these are errors that can occur when the link changes state while
647 * a packet is being sent or received. This doesn't cover things
648 * like EBP or VCRC that can be the result of a sending having the
649 * link change state, so we receive a "known bad" packet.
651 #define E_SUM_LINK_PKTERRS \
652 (ERR_MASK(SendDroppedDataPktErr) | \
653 ERR_MASK(SendDroppedSmpPktErr) | \
654 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
655 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
656 ERR_MASK(RcvUnexpectedCharErr))
658 static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *,
662 * On platforms using this chip, and not having ordered WC stores, we
663 * can get TXE parity errors due to speculative reads to the PIO buffers,
664 * and this, due to a chip issue can result in (many) false parity error
665 * reports. So it's a debug print on those, and an info print on systems
666 * where the speculative reads don't occur.
668 static void qib_6120_txe_recover(struct qib_devdata *dd)
670 if (!qib_unordered_wc())
671 qib_devinfo(dd->pcidev,
672 "Recovering from TXE PIO parity error\n");
675 /* enable/disable chip from delivering interrupts */
676 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable)
679 if (dd->flags & QIB_BADINTR)
681 qib_write_kreg(dd, kr_intmask, ~0ULL);
682 /* force re-interrupt of any pending interrupts. */
683 qib_write_kreg(dd, kr_intclear, 0ULL);
685 qib_write_kreg(dd, kr_intmask, 0ULL);
689 * Try to cleanup as much as possible for anything that might have gone
690 * wrong while in freeze mode, such as pio buffers being written by user
691 * processes (causing armlaunch), send errors due to going into freeze mode,
692 * etc., and try to avoid causing extra interrupts while doing so.
693 * Forcibly update the in-memory pioavail register copies after cleanup
694 * because the chip won't do it while in freeze mode (the register values
695 * themselves are kept correct).
696 * Make sure that we don't lose any important interrupts by using the chip
697 * feature that says that writing 0 to a bit in *clear that is set in
698 * *status will cause an interrupt to be generated again (if allowed by
700 * This is in chip-specific code because of all of the register accesses,
701 * even though the details are similar on most chips
703 static void qib_6120_clear_freeze(struct qib_devdata *dd)
705 /* disable error interrupts, to avoid confusion */
706 qib_write_kreg(dd, kr_errmask, 0ULL);
708 /* also disable interrupts; errormask is sometimes overwriten */
709 qib_6120_set_intr_state(dd, 0);
711 qib_cancel_sends(dd->pport);
713 /* clear the freeze, and be sure chip saw it */
714 qib_write_kreg(dd, kr_control, dd->control);
715 qib_read_kreg32(dd, kr_scratch);
717 /* force in-memory update now we are out of freeze */
718 qib_force_pio_avail_update(dd);
721 * force new interrupt if any hwerr, error or interrupt bits are
722 * still set, and clear "safe" send packet errors related to freeze
723 * and cancelling sends. Re-enable error interrupts before possible
724 * force of re-interrupt on pending interrupts.
726 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
727 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
728 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
729 qib_6120_set_intr_state(dd, 1);
733 * qib_handle_6120_hwerrors - display hardware errors.
734 * @dd: the qlogic_ib device
735 * @msg: the output buffer
736 * @msgl: the size of the output buffer
738 * Use same msg buffer as regular errors to avoid excessive stack
739 * use. Most hardware errors are catastrophic, but for right now,
740 * we'll print them and continue. Reuse the same message buffer as
741 * handle_6120_errors() to avoid excessive stack usage.
743 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
752 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
755 if (hwerrs == ~0ULL) {
756 qib_dev_err(dd, "Read of hardware error status failed "
757 "(all bits set); ignoring\n");
760 qib_stats.sps_hwerrs++;
762 /* Always clear the error status register, except MEMBISTFAIL,
763 * regardless of whether we continue or stop using the chip.
764 * We want that set so we know it failed, even across driver reload.
765 * We'll still ignore it in the hwerrmask. We do this partly for
766 * diagnostics, but also for support */
767 qib_write_kreg(dd, kr_hwerrclear,
768 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
770 hwerrs &= dd->cspec->hwerrmask;
772 /* We log some errors to EEPROM, check if we have any of those. */
773 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
774 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
775 qib_inc_eeprom_err(dd, log_idx, 1);
778 * Make sure we get this much out, unless told to be quiet,
779 * or it's occurred within the last 5 seconds.
781 if (hwerrs & ~(TXE_PIO_PARITY | RXEMEMPARITYERR_EAGERTID))
782 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
783 "(cleared)\n", (unsigned long long) hwerrs);
785 if (hwerrs & ~IB_HWE_BITSEXTANT)
786 qib_dev_err(dd, "hwerror interrupt with unknown errors "
787 "%llx set\n", (unsigned long long)
788 (hwerrs & ~IB_HWE_BITSEXTANT));
790 ctrl = qib_read_kreg32(dd, kr_control);
791 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
793 * Parity errors in send memory are recoverable,
794 * just cancel the send (if indicated in * sendbuffererror),
795 * count the occurrence, unfreeze (if no other handled
796 * hardware error bits are set), and continue. They can
797 * occur if a processor speculative read is done to the PIO
798 * buffer while we are sending a packet, for example.
800 if (hwerrs & TXE_PIO_PARITY) {
801 qib_6120_txe_recover(dd);
802 hwerrs &= ~TXE_PIO_PARITY;
806 static u32 freeze_cnt;
809 qib_6120_clear_freeze(dd);
816 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
818 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware"
820 /* ignore from now on, so disable until driver reloaded */
821 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
822 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
825 qib_format_hwerrors(hwerrs, qib_6120_hwerror_msgs,
826 ARRAY_SIZE(qib_6120_hwerror_msgs), msg, msgl);
828 bitsmsg = dd->cspec->bitsmsgbuf;
829 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
830 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
831 bits = (u32) ((hwerrs >>
832 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
833 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
834 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
835 "[PCIe Mem Parity Errs %x] ", bits);
836 strlcat(msg, bitsmsg, msgl);
839 if (hwerrs & _QIB_PLL_FAIL) {
841 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
842 "[PLL failed (%llx), InfiniPath hardware unusable]",
843 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
844 strlcat(msg, bitsmsg, msgl);
845 /* ignore from now on, so disable until driver reloaded */
846 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
847 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
850 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
852 * If it occurs, it is left masked since the external
853 * interface is unused
855 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
856 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
861 * if any set that we aren't ignoring; only
862 * make the complaint once, in case it's stuck
863 * or recurring, and we get here multiple
866 qib_dev_err(dd, "%s hardware error\n", msg);
868 *msg = 0; /* recovered from all of them */
870 if (isfatal && !dd->diag_client) {
871 qib_dev_err(dd, "Fatal Hardware Error, no longer"
872 " usable, SN %.16s\n", dd->serial);
874 * for /sys status file and user programs to print; if no
875 * trailing brace is copied, we'll know it was truncated.
878 snprintf(dd->freezemsg, dd->freezelen,
880 qib_disable_after_error(dd);
885 * Decode the error status into strings, deciding whether to always
886 * print * it or not depending on "normal packet errors" vs everything
887 * else. Return 1 if "real" errors, otherwise 0 if only packet
888 * errors, so caller can decide what to print with the string.
890 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen,
896 if (err & QLOGIC_IB_E_PKTERRS) {
897 if (!(err & ~QLOGIC_IB_E_PKTERRS))
899 if ((err & ERR_MASK(RcvICRCErr)) &&
900 !(err&(ERR_MASK(RcvVCRCErr)|ERR_MASK(RcvEBPErr))))
901 strlcat(buf, "CRC ", blen);
905 if (err & ERR_MASK(RcvHdrLenErr))
906 strlcat(buf, "rhdrlen ", blen);
907 if (err & ERR_MASK(RcvBadTidErr))
908 strlcat(buf, "rbadtid ", blen);
909 if (err & ERR_MASK(RcvBadVersionErr))
910 strlcat(buf, "rbadversion ", blen);
911 if (err & ERR_MASK(RcvHdrErr))
912 strlcat(buf, "rhdr ", blen);
913 if (err & ERR_MASK(RcvLongPktLenErr))
914 strlcat(buf, "rlongpktlen ", blen);
915 if (err & ERR_MASK(RcvMaxPktLenErr))
916 strlcat(buf, "rmaxpktlen ", blen);
917 if (err & ERR_MASK(RcvMinPktLenErr))
918 strlcat(buf, "rminpktlen ", blen);
919 if (err & ERR_MASK(SendMinPktLenErr))
920 strlcat(buf, "sminpktlen ", blen);
921 if (err & ERR_MASK(RcvFormatErr))
922 strlcat(buf, "rformaterr ", blen);
923 if (err & ERR_MASK(RcvUnsupportedVLErr))
924 strlcat(buf, "runsupvl ", blen);
925 if (err & ERR_MASK(RcvUnexpectedCharErr))
926 strlcat(buf, "runexpchar ", blen);
927 if (err & ERR_MASK(RcvIBFlowErr))
928 strlcat(buf, "ribflow ", blen);
929 if (err & ERR_MASK(SendUnderRunErr))
930 strlcat(buf, "sunderrun ", blen);
931 if (err & ERR_MASK(SendPioArmLaunchErr))
932 strlcat(buf, "spioarmlaunch ", blen);
933 if (err & ERR_MASK(SendUnexpectedPktNumErr))
934 strlcat(buf, "sunexperrpktnum ", blen);
935 if (err & ERR_MASK(SendDroppedSmpPktErr))
936 strlcat(buf, "sdroppedsmppkt ", blen);
937 if (err & ERR_MASK(SendMaxPktLenErr))
938 strlcat(buf, "smaxpktlen ", blen);
939 if (err & ERR_MASK(SendUnsupportedVLErr))
940 strlcat(buf, "sunsupVL ", blen);
941 if (err & ERR_MASK(InvalidAddrErr))
942 strlcat(buf, "invalidaddr ", blen);
943 if (err & ERR_MASK(RcvEgrFullErr))
944 strlcat(buf, "rcvegrfull ", blen);
945 if (err & ERR_MASK(RcvHdrFullErr))
946 strlcat(buf, "rcvhdrfull ", blen);
947 if (err & ERR_MASK(IBStatusChanged))
948 strlcat(buf, "ibcstatuschg ", blen);
949 if (err & ERR_MASK(RcvIBLostLinkErr))
950 strlcat(buf, "riblostlink ", blen);
951 if (err & ERR_MASK(HardwareErr))
952 strlcat(buf, "hardware ", blen);
953 if (err & ERR_MASK(ResetNegated))
954 strlcat(buf, "reset ", blen);
960 * Called when we might have an error that is specific to a particular
961 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
963 static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd)
965 unsigned long sbuf[2];
966 struct qib_devdata *dd = ppd->dd;
969 * It's possible that sendbuffererror could have bits set; might
970 * have already done this as a result of hardware error handling.
972 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
973 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
975 if (sbuf[0] || sbuf[1])
976 qib_disarm_piobufs_set(dd, sbuf,
977 dd->piobcnt2k + dd->piobcnt4k);
980 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs)
983 u32 ibstate = qib_6120_iblink_state(ibcs);
984 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov);
986 if (linkrecov != dd->cspec->lastlinkrecov) {
987 /* and no more until active again */
988 dd->cspec->lastlinkrecov = 0;
989 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN);
992 if (ibstate == IB_PORT_ACTIVE)
993 dd->cspec->lastlinkrecov =
994 read_6120_creg32(dd, cr_iblinkerrrecov);
998 static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
1001 u64 ignore_this_time = 0;
1004 struct qib_pportdata *ppd = dd->pport;
1007 /* don't report errors that are masked */
1008 errs &= dd->cspec->errormask;
1009 msg = dd->cspec->emsgbuf;
1011 /* do these first, they are most important */
1012 if (errs & ERR_MASK(HardwareErr))
1013 qib_handle_6120_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1015 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1016 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1017 qib_inc_eeprom_err(dd, log_idx, 1);
1019 if (errs & ~IB_E_BITSEXTANT)
1020 qib_dev_err(dd, "error interrupt with unknown errors "
1022 (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1024 if (errs & E_SUM_ERRS) {
1025 qib_disarm_6120_senderrbufs(ppd);
1026 if ((errs & E_SUM_LINK_PKTERRS) &&
1027 !(ppd->lflags & QIBL_LINKACTIVE)) {
1029 * This can happen when trying to bring the link
1030 * up, but the IB link changes state at the "wrong"
1031 * time. The IB logic then complains that the packet
1032 * isn't valid. We don't want to confuse people, so
1033 * we just don't print them, except at debug
1035 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1037 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1038 !(ppd->lflags & QIBL_LINKACTIVE)) {
1040 * This can happen when SMA is trying to bring the link
1041 * up, but the IB link changes state at the "wrong" time.
1042 * The IB logic then complains that the packet isn't
1043 * valid. We don't want to confuse people, so we just
1044 * don't print them, except at debug
1046 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1049 qib_write_kreg(dd, kr_errclear, errs);
1051 errs &= ~ignore_this_time;
1056 * The ones we mask off are handled specially below
1059 mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) |
1060 ERR_MASK(RcvHdrFullErr) | ERR_MASK(HardwareErr);
1061 qib_decode_6120_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1063 if (errs & E_SUM_PKTERRS)
1064 qib_stats.sps_rcverrs++;
1065 if (errs & E_SUM_ERRS)
1066 qib_stats.sps_txerrs++;
1068 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS);
1070 if (errs & ERR_MASK(IBStatusChanged)) {
1071 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1072 u32 ibstate = qib_6120_iblink_state(ibcs);
1075 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov)
1076 handle = chk_6120_linkrecovery(dd, ibcs);
1078 * Since going into a recovery state causes the link state
1079 * to go down and since recovery is transitory, it is better
1080 * if we "miss" ever seeing the link training state go into
1081 * recovery (i.e., ignore this transition for link state
1082 * special handling purposes) without updating lastibcstat.
1084 if (handle && qib_6120_phys_portstate(ibcs) ==
1085 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1088 qib_handle_e_ibstatuschanged(ppd, ibcs);
1091 if (errs & ERR_MASK(ResetNegated)) {
1092 qib_dev_err(dd, "Got reset, requires re-init "
1093 "(unload and reload driver)\n");
1094 dd->flags &= ~QIB_INITTED; /* needs re-init */
1095 /* mark as having had error */
1096 *dd->devstatusp |= QIB_STATUS_HWERROR;
1097 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1101 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1103 if (ppd->state_wanted & ppd->lflags)
1104 wake_up_interruptible(&ppd->state_wait);
1107 * If there were hdrq or egrfull errors, wake up any processes
1108 * waiting in poll. We used to try to check which contexts had
1109 * the overflow, but given the cost of that and the chip reads
1110 * to support it, it's better to just wake everybody up if we
1111 * get an overflow; waiters can poll again if it's not them.
1113 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1114 qib_handle_urcv(dd, ~0U);
1115 if (errs & ERR_MASK(RcvEgrFullErr))
1116 qib_stats.sps_buffull++;
1118 qib_stats.sps_hdrfull++;
1125 * qib_6120_init_hwerrors - enable hardware errors
1126 * @dd: the qlogic_ib device
1128 * now that we have finished initializing everything that might reasonably
1129 * cause a hardware error, and cleared those errors bits as they occur,
1130 * we can enable hardware errors in the mask (potentially enabling
1131 * freeze mode), and enable hardware errors as errors (along with
1132 * everything else) in errormask
1134 static void qib_6120_init_hwerrors(struct qib_devdata *dd)
1139 extsval = qib_read_kreg64(dd, kr_extstatus);
1141 if (!(extsval & QLOGIC_IB_EXTS_MEMBIST_ENDTEST))
1142 qib_dev_err(dd, "MemBIST did not complete!\n");
1144 /* init so all hwerrors interrupt, and enter freeze, ajdust below */
1146 if (dd->minrev < 2) {
1148 * Avoid problem with internal interface bus parity
1149 * checking. Fixed in Rev2.
1151 val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM;
1153 /* avoid some intel cpu's speculative read freeze mode issue */
1154 val &= ~TXEMEMPARITYERR_PIOBUF;
1156 dd->cspec->hwerrmask = val;
1158 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1159 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1162 qib_write_kreg(dd, kr_errclear, ~0ULL);
1163 /* enable errors that are masked, at least this first time. */
1164 qib_write_kreg(dd, kr_errmask, ~0ULL);
1165 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1166 /* clear any interrupts up to this point (ints still not enabled) */
1167 qib_write_kreg(dd, kr_intclear, ~0ULL);
1169 qib_write_kreg(dd, kr_rcvbthqp,
1170 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) |
1175 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1176 * on chips that are count-based, rather than trigger-based. There is no
1177 * reference counting, but that's also fine, given the intended use.
1178 * Only chip-specific because it's all register accesses
1180 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable)
1183 qib_write_kreg(dd, kr_errclear,
1184 ERR_MASK(SendPioArmLaunchErr));
1185 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1187 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1188 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1192 * Formerly took parameter <which> in pre-shifted,
1193 * pre-merged form with LinkCmd and LinkInitCmd
1194 * together, and assuming the zero was NOP.
1196 static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1200 struct qib_devdata *dd = ppd->dd;
1201 unsigned long flags;
1203 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1205 * If we are told to disable, note that so link-recovery
1206 * code does not attempt to bring us back up.
1208 spin_lock_irqsave(&ppd->lflags_lock, flags);
1209 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1210 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1211 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1213 * Any other linkinitcmd will lead to LINKDOWN and then
1214 * to INIT (if all is well), so clear flag to let
1215 * link-recovery code attempt to bring us back up.
1217 spin_lock_irqsave(&ppd->lflags_lock, flags);
1218 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1219 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1222 mod_wd = (linkcmd << QLOGIC_IB_IBCC_LINKCMD_SHIFT) |
1223 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1225 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd);
1226 /* write to chip to prevent back-to-back writes of control reg */
1227 qib_write_kreg(dd, kr_scratch, 0);
1231 * qib_6120_bringup_serdes - bring up the serdes
1232 * @dd: the qlogic_ib device
1234 static int qib_6120_bringup_serdes(struct qib_pportdata *ppd)
1236 struct qib_devdata *dd = ppd->dd;
1237 u64 val, config1, prev_val, hwstat, ibc;
1239 /* Put IBC in reset, sends disabled */
1240 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1241 qib_write_kreg(dd, kr_control, 0ULL);
1243 dd->cspec->ibdeltainprog = 1;
1244 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr);
1245 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov);
1247 /* flowcontrolwatermark is in units of KBytes */
1248 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1250 * How often flowctrl sent. More or less in usecs; balance against
1251 * watermark value, so that in theory senders always get a flow
1252 * control update in time to not let the IB link go idle.
1254 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1255 /* max error tolerance */
1256 dd->cspec->lli_thresh = 0xf;
1257 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold);
1258 /* use "real" buffer space for */
1259 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1260 /* IB credit flow control. */
1261 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1263 * set initial max size pkt IBC will send, including ICRC; it's the
1264 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1266 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1267 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1269 /* initially come up waiting for TS1, without sending anything. */
1270 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1271 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1272 qib_write_kreg(dd, kr_ibcctrl, val);
1274 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1275 config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1278 * Force reset on, also set rxdetect enable. Must do before reading
1279 * serdesstatus at least for simulation, or some of the bits in
1280 * serdes status will come back as undefined and cause simulation
1283 val |= SYM_MASK(SerdesCfg0, ResetPLL) |
1284 SYM_MASK(SerdesCfg0, RxDetEnX) |
1285 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1286 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1287 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1288 SYM_MASK(SerdesCfg0, L1PwrDnD));
1289 qib_write_kreg(dd, kr_serdes_cfg0, val);
1290 /* be sure chip saw it */
1291 qib_read_kreg64(dd, kr_scratch);
1292 udelay(5); /* need pll reset set at least for a bit */
1294 * after PLL is reset, set the per-lane Resets and TxIdle and
1295 * clear the PLL reset and rxdetect (to get falling edge).
1296 * Leave L1PWR bits set (permanently)
1298 val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) |
1299 SYM_MASK(SerdesCfg0, ResetPLL) |
1300 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1301 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1302 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1303 SYM_MASK(SerdesCfg0, L1PwrDnD)));
1304 val |= (SYM_MASK(SerdesCfg0, ResetA) |
1305 SYM_MASK(SerdesCfg0, ResetB) |
1306 SYM_MASK(SerdesCfg0, ResetC) |
1307 SYM_MASK(SerdesCfg0, ResetD)) |
1308 SYM_MASK(SerdesCfg0, TxIdeEnX);
1309 qib_write_kreg(dd, kr_serdes_cfg0, val);
1310 /* be sure chip saw it */
1311 (void) qib_read_kreg64(dd, kr_scratch);
1312 /* need PLL reset clear for at least 11 usec before lane
1313 * resets cleared; give it a few more to be sure */
1315 val &= ~((SYM_MASK(SerdesCfg0, ResetA) |
1316 SYM_MASK(SerdesCfg0, ResetB) |
1317 SYM_MASK(SerdesCfg0, ResetC) |
1318 SYM_MASK(SerdesCfg0, ResetD)) |
1319 SYM_MASK(SerdesCfg0, TxIdeEnX));
1321 qib_write_kreg(dd, kr_serdes_cfg0, val);
1322 /* be sure chip saw it */
1323 (void) qib_read_kreg64(dd, kr_scratch);
1325 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1327 if (val & QLOGIC_IB_XGXS_RESET)
1328 val &= ~QLOGIC_IB_XGXS_RESET;
1329 if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) {
1330 /* need to compensate for Tx inversion in partner */
1331 val &= ~SYM_MASK(XGXSCfg, polarity_inv);
1332 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv);
1334 if (val != prev_val)
1335 qib_write_kreg(dd, kr_xgxs_cfg, val);
1337 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1339 /* clear current and de-emphasis bits */
1340 config1 &= ~0x0ffffffff00ULL;
1341 /* set current to 20ma */
1342 config1 |= 0x00000000000ULL;
1343 /* set de-emphasis to -5.68dB */
1344 config1 |= 0x0cccc000000ULL;
1345 qib_write_kreg(dd, kr_serdes_cfg1, config1);
1347 /* base and port guid same for single port */
1348 ppd->guid = dd->base_guid;
1351 * the process of setting and un-resetting the serdes normally
1352 * causes a serdes PLL error, so check for that and clear it
1353 * here. Also clearr hwerr bit in errstatus, but not others.
1355 hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1357 /* should just have PLL, clear all set, in an case */
1358 if (hwstat & ~QLOGIC_IB_HWE_SERDESPLLFAILED)
1359 qib_write_kreg(dd, kr_hwerrclear, hwstat);
1360 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr));
1363 dd->control |= QLOGIC_IB_C_LINKENABLE;
1364 dd->control &= ~QLOGIC_IB_C_FREEZEMODE;
1365 qib_write_kreg(dd, kr_control, dd->control);
1371 * qib_6120_quiet_serdes - set serdes to txidle
1372 * @ppd: physical port of the qlogic_ib device
1373 * Called when driver is being unloaded
1375 static void qib_6120_quiet_serdes(struct qib_pportdata *ppd)
1377 struct qib_devdata *dd = ppd->dd;
1380 qib_set_ib_6120_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1383 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1384 qib_write_kreg(dd, kr_control,
1385 dd->control | QLOGIC_IB_C_FREEZEMODE);
1387 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta ||
1388 dd->cspec->ibdeltainprog) {
1391 /* enable counter writes */
1392 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1393 qib_write_kreg(dd, kr_hwdiagctrl,
1394 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1396 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) {
1397 val = read_6120_creg32(dd, cr_ibsymbolerr);
1398 if (dd->cspec->ibdeltainprog)
1399 val -= val - dd->cspec->ibsymsnap;
1400 val -= dd->cspec->ibsymdelta;
1401 write_6120_creg(dd, cr_ibsymbolerr, val);
1403 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) {
1404 val = read_6120_creg32(dd, cr_iblinkerrrecov);
1405 if (dd->cspec->ibdeltainprog)
1406 val -= val - dd->cspec->iblnkerrsnap;
1407 val -= dd->cspec->iblnkerrdelta;
1408 write_6120_creg(dd, cr_iblinkerrrecov, val);
1411 /* and disable counter writes */
1412 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1415 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1416 val |= SYM_MASK(SerdesCfg0, TxIdeEnX);
1417 qib_write_kreg(dd, kr_serdes_cfg0, val);
1421 * qib_6120_setup_setextled - set the state of the two external LEDs
1422 * @dd: the qlogic_ib device
1423 * @on: whether the link is up or not
1425 * The exact combo of LEDs if on is true is determined by looking
1428 * These LEDs indicate the physical and logical state of IB link.
1429 * For this chip (at least with recommended board pinouts), LED1
1430 * is Yellow (logical state) and LED2 is Green (physical state),
1432 * Note: We try to match the Mellanox HCA LED behavior as best
1433 * we can. Green indicates physical link state is OK (something is
1434 * plugged in, and we can train).
1435 * Amber indicates the link is logically up (ACTIVE).
1436 * Mellanox further blinks the amber LED to indicate data packet
1437 * activity, but we have no hardware support for that, so it would
1438 * require waking up every 10-20 msecs and checking the counters
1439 * on the chip, and then turning the LED off if appropriate. That's
1440 * visible overhead, so not something we will do.
1443 static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on)
1445 u64 extctl, val, lst, ltst;
1446 unsigned long flags;
1447 struct qib_devdata *dd = ppd->dd;
1450 * The diags use the LED to indicate diag info, so we leave
1451 * the external LED alone when the diags are running.
1453 if (dd->diag_client)
1456 /* Allow override of LED display for, e.g. Locating system in rack */
1457 if (ppd->led_override) {
1458 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1459 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1460 lst = (ppd->led_override & QIB_LED_LOG) ?
1461 IB_PORT_ACTIVE : IB_PORT_DOWN;
1463 val = qib_read_kreg64(dd, kr_ibcstatus);
1464 ltst = qib_6120_phys_portstate(val);
1465 lst = qib_6120_iblink_state(val);
1471 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1472 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1473 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1475 if (ltst == IB_PHYSPORTSTATE_LINKUP)
1476 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1477 if (lst == IB_PORT_ACTIVE)
1478 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1479 dd->cspec->extctrl = extctl;
1480 qib_write_kreg(dd, kr_extctrl, extctl);
1481 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1484 static void qib_6120_free_irq(struct qib_devdata *dd)
1486 if (dd->cspec->irq) {
1487 free_irq(dd->cspec->irq, dd);
1494 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1495 * @dd: the qlogic_ib device
1497 * This is called during driver unload.
1499 static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1501 qib_6120_free_irq(dd);
1502 kfree(dd->cspec->cntrs);
1503 kfree(dd->cspec->portcntrs);
1504 if (dd->cspec->dummy_hdrq) {
1505 dma_free_coherent(&dd->pcidev->dev,
1506 ALIGN(dd->rcvhdrcnt *
1508 sizeof(u32), PAGE_SIZE),
1509 dd->cspec->dummy_hdrq,
1510 dd->cspec->dummy_hdrq_phys);
1511 dd->cspec->dummy_hdrq = NULL;
1515 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint)
1517 unsigned long flags;
1519 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1521 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail);
1523 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail);
1524 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1525 qib_write_kreg(dd, kr_scratch, 0ULL);
1526 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1530 * handle errors and unusual events first, separate function
1531 * to improve cache hits for fast path interrupt handling
1533 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat)
1535 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1536 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n",
1537 istat & ~QLOGIC_IB_I_BITSEXTANT);
1539 if (istat & QLOGIC_IB_I_ERROR) {
1542 qib_stats.sps_errints++;
1543 estat = qib_read_kreg64(dd, kr_errstatus);
1545 qib_devinfo(dd->pcidev, "error interrupt (%Lx), "
1546 "but no error bits set!\n", istat);
1547 handle_6120_errors(dd, estat);
1550 if (istat & QLOGIC_IB_I_GPIO) {
1555 * GPIO_3..5 on IBA6120 Rev2 chips indicate
1556 * errors that we need to count.
1558 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1559 /* First the error-counter case. */
1560 if (gpiostatus & GPIO_ERRINTR_MASK) {
1561 /* want to clear the bits we see asserted. */
1562 to_clear |= (gpiostatus & GPIO_ERRINTR_MASK);
1565 * Count appropriately, clear bits out of our copy,
1566 * as they have been "handled".
1568 if (gpiostatus & (1 << GPIO_RXUVL_BIT))
1569 dd->cspec->rxfc_unsupvl_errs++;
1570 if (gpiostatus & (1 << GPIO_OVRUN_BIT))
1571 dd->cspec->overrun_thresh_errs++;
1572 if (gpiostatus & (1 << GPIO_LLI_BIT))
1573 dd->cspec->lli_errs++;
1574 gpiostatus &= ~GPIO_ERRINTR_MASK;
1578 * Some unexpected bits remain. If they could have
1579 * caused the interrupt, complain and clear.
1580 * To avoid repetition of this condition, also clear
1581 * the mask. It is almost certainly due to error.
1583 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1586 * Also check that the chip reflects our shadow,
1587 * and report issues, If they caused the interrupt.
1588 * we will suppress by refreshing from the shadow.
1590 if (mask & gpiostatus) {
1591 to_clear |= (gpiostatus & mask);
1592 dd->cspec->gpio_mask &= ~(gpiostatus & mask);
1593 qib_write_kreg(dd, kr_gpio_mask,
1594 dd->cspec->gpio_mask);
1598 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear);
1602 static irqreturn_t qib_6120intr(int irq, void *data)
1604 struct qib_devdata *dd = data;
1606 u32 istat, ctxtrbits, rmask, crcs = 0;
1609 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1611 * This return value is not great, but we do not want the
1612 * interrupt core code to remove our interrupt handler
1613 * because we don't appear to be handling an interrupt
1614 * during a chip reset.
1620 istat = qib_read_kreg32(dd, kr_intstatus);
1622 if (unlikely(!istat)) {
1623 ret = IRQ_NONE; /* not our interrupt, or already handled */
1626 if (unlikely(istat == -1)) {
1627 qib_bad_intrstatus(dd);
1628 /* don't know if it was our interrupt or not */
1633 qib_stats.sps_ints++;
1634 if (dd->int_counter != (u32) -1)
1637 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1638 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1639 unlikely_6120_intr(dd, istat);
1642 * Clear the interrupt bits we found set, relatively early, so we
1643 * "know" know the chip will have seen this by the time we process
1644 * the queue, and will re-interrupt if necessary. The processor
1645 * itself won't take the interrupt again until we return.
1647 qib_write_kreg(dd, kr_intclear, istat);
1650 * Handle kernel receive queues before checking for pio buffers
1651 * available since receives can overflow; piobuf waiters can afford
1652 * a few extra cycles, since they were waiting anyway.
1655 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1656 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1658 rmask = (1U << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1659 (1U << QLOGIC_IB_I_RCVURG_SHIFT);
1660 for (i = 0; i < dd->first_user_ctxt; i++) {
1661 if (ctxtrbits & rmask) {
1662 ctxtrbits &= ~rmask;
1663 crcs += qib_kreceive(dd->rcd[i],
1664 &dd->cspec->lli_counter,
1670 u32 cntr = dd->cspec->lli_counter;
1673 if (cntr > dd->cspec->lli_thresh) {
1674 dd->cspec->lli_counter = 0;
1675 dd->cspec->lli_errs++;
1677 dd->cspec->lli_counter += cntr;
1684 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1685 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
1686 qib_handle_urcv(dd, ctxtrbits);
1690 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
1691 qib_ib_piobufavail(dd);
1699 * Set up our chip-specific interrupt handler
1700 * The interrupt type has already been setup, so
1701 * we just need to do the registration and error checking.
1703 static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1706 * If the chip supports added error indication via GPIO pins,
1707 * enable interrupts on those bits so the interrupt routine
1708 * can count the events. Also set flag so interrupt routine
1709 * can know they are expected.
1711 if (SYM_FIELD(dd->revision, Revision_R,
1712 ChipRevMinor) > 1) {
1713 /* Rev2+ reports extra errors via internal GPIO pins */
1714 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK;
1715 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1718 if (!dd->cspec->irq)
1719 qib_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
1723 ret = request_irq(dd->cspec->irq, qib_6120intr, 0,
1726 qib_dev_err(dd, "Couldn't setup interrupt "
1727 "(irq=%d): %d\n", dd->cspec->irq,
1733 * pe_boardname - fill in the board name
1734 * @dd: the qlogic_ib device
1736 * info is based on the board revision register
1738 static void pe_boardname(struct qib_devdata *dd)
1741 u32 boardid, namelen;
1743 boardid = SYM_FIELD(dd->revision, Revision,
1748 n = "InfiniPath_QLE7140";
1751 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid);
1752 n = "Unknown_InfiniPath_6120";
1755 namelen = strlen(n) + 1;
1756 dd->boardname = kmalloc(namelen, GFP_KERNEL);
1758 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
1760 snprintf(dd->boardname, namelen, "%s", n);
1762 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
1763 qib_dev_err(dd, "Unsupported InfiniPath hardware revision "
1764 "%u.%u!\n", dd->majrev, dd->minrev);
1766 snprintf(dd->boardversion, sizeof(dd->boardversion),
1767 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
1768 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
1769 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
1770 dd->majrev, dd->minrev,
1771 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
1776 * This routine sleeps, so it can only be called from user context, not
1777 * from interrupt context. If we need interrupt context, we can split
1778 * it into two routines.
1780 static int qib_6120_setup_reset(struct qib_devdata *dd)
1786 u8 int_line, clinesz;
1788 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
1790 /* Use ERROR so it shows up in logs, etc. */
1791 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
1793 /* no interrupts till re-initted */
1794 qib_6120_set_intr_state(dd, 0);
1796 dd->cspec->ibdeltainprog = 0;
1797 dd->cspec->ibsymdelta = 0;
1798 dd->cspec->iblnkerrdelta = 0;
1801 * Keep chip from being accessed until we are ready. Use
1802 * writeq() directly, to allow the write even though QIB_PRESENT
1805 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1806 dd->int_counter = 0; /* so we check interrupts work again */
1807 val = dd->control | QLOGIC_IB_C_RESET;
1808 writeq(val, &dd->kregbase[kr_control]);
1809 mb(); /* prevent compiler re-ordering around actual reset */
1811 for (i = 1; i <= 5; i++) {
1813 * Allow MBIST, etc. to complete; longer on each retry.
1814 * We sometimes get machine checks from bus timeout if no
1815 * response, so for now, make it *really* long.
1817 msleep(1000 + (1 + i) * 2000);
1819 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
1822 * Use readq directly, so we don't need to mark it as PRESENT
1823 * until we get a successful indication that all is well.
1825 val = readq(&dd->kregbase[kr_revision]);
1826 if (val == dd->revision) {
1827 dd->flags |= QIB_PRESENT; /* it's back */
1828 ret = qib_reinit_intr(dd);
1832 ret = 0; /* failed */
1836 if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
1837 qib_dev_err(dd, "Reset failed to setup PCIe or "
1838 "interrupts; continuing anyway\n");
1839 /* clear the reset error, init error/hwerror mask */
1840 qib_6120_init_hwerrors(dd);
1841 /* for Rev2 error interrupts; nop for rev 1 */
1842 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1843 /* clear the reset error, init error/hwerror mask */
1844 qib_6120_init_hwerrors(dd);
1850 * qib_6120_put_tid - write a TID in chip
1851 * @dd: the qlogic_ib device
1852 * @tidptr: pointer to the expected TID (in chip) to update
1853 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1855 * @pa: physical address of in memory buffer; tidinvalid if freeing
1857 * This exists as a separate routine to allow for special locking etc.
1858 * It's used for both the full cleanup on exit, as well as the normal
1859 * setup and teardown.
1861 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
1862 u32 type, unsigned long pa)
1864 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1865 unsigned long flags;
1867 spinlock_t *tidlockp; /* select appropriate spinlock */
1872 if (pa != dd->tidinvalid) {
1873 if (pa & ((1U << 11) - 1)) {
1874 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1879 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1880 qib_dev_err(dd, "Physical page address 0x%lx "
1881 "larger than supported\n", pa);
1885 if (type == RCVHQ_RCV_TYPE_EAGER)
1886 pa |= dd->tidtemplate;
1887 else /* for now, always full 4KB page */
1892 * Avoid chip issue by writing the scratch register
1893 * before and after the TID, and with an io write barrier.
1894 * We use a spinlock around the writes, so they can't intermix
1895 * with other TID (eager or expected) writes (the chip problem
1896 * is triggered by back to back TID writes). Unfortunately, this
1897 * call can be done from interrupt level for the ctxt 0 eager TIDs,
1898 * so we have to use irqsave locks.
1901 * Assumes tidptr always > egrtidbase
1902 * if type == RCVHQ_RCV_TYPE_EAGER.
1904 tidx = tidptr - dd->egrtidbase;
1906 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt)
1907 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock;
1908 spin_lock_irqsave(tidlockp, flags);
1909 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf);
1911 qib_write_kreg(dd, kr_scratch, 0xdeadbeef);
1913 spin_unlock_irqrestore(tidlockp, flags);
1917 * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher
1918 * @dd: the qlogic_ib device
1919 * @tidptr: pointer to the expected TID (in chip) to update
1920 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1922 * @pa: physical address of in memory buffer; tidinvalid if freeing
1924 * This exists as a separate routine to allow for selection of the
1925 * appropriate "flavor". The static calls in cleanup just use the
1926 * revision-agnostic form, as they are not performance critical.
1928 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1929 u32 type, unsigned long pa)
1931 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1937 if (pa != dd->tidinvalid) {
1938 if (pa & ((1U << 11) - 1)) {
1939 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1944 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1945 qib_dev_err(dd, "Physical page address 0x%lx "
1946 "larger than supported\n", pa);
1950 if (type == RCVHQ_RCV_TYPE_EAGER)
1951 pa |= dd->tidtemplate;
1952 else /* for now, always full 4KB page */
1955 tidx = tidptr - dd->egrtidbase;
1962 * qib_6120_clear_tids - clear all TID entries for a context, expected and eager
1963 * @dd: the qlogic_ib device
1964 * @ctxt: the context
1966 * clear all TID entries for a context, expected and eager.
1967 * Used from qib_close(). On this chip, TIDs are only 32 bits,
1968 * not 64, but they are still on 64 bit boundaries, so tidbase
1969 * is declared as u64 * for the pointer math, even though we write 32 bits
1971 static void qib_6120_clear_tids(struct qib_devdata *dd,
1972 struct qib_ctxtdata *rcd)
1974 u64 __iomem *tidbase;
1975 unsigned long tidinv;
1979 if (!dd->kregbase || !rcd)
1984 tidinv = dd->tidinvalid;
1985 tidbase = (u64 __iomem *)
1986 ((char __iomem *)(dd->kregbase) +
1988 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
1990 for (i = 0; i < dd->rcvtidcnt; i++)
1991 /* use func pointer because could be one of two funcs */
1992 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1995 tidbase = (u64 __iomem *)
1996 ((char __iomem *)(dd->kregbase) +
1998 rcd->rcvegr_tid_base * sizeof(*tidbase));
2000 for (i = 0; i < rcd->rcvegrcnt; i++)
2001 /* use func pointer because could be one of two funcs */
2002 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2007 * qib_6120_tidtemplate - setup constants for TID updates
2008 * @dd: the qlogic_ib device
2010 * We setup stuff that we use a lot, to avoid calculating each time
2012 static void qib_6120_tidtemplate(struct qib_devdata *dd)
2014 u32 egrsize = dd->rcvegrbufsize;
2017 * For now, we always allocate 4KB buffers (at init) so we can
2018 * receive max size packets. We may want a module parameter to
2019 * specify 2KB or 4KB and/or make be per ctxt instead of per device
2020 * for those who want to reduce memory footprint. Note that the
2021 * rcvhdrentsize size must be large enough to hold the largest
2022 * IB header (currently 96 bytes) that we expect to handle (plus of
2023 * course the 2 dwords of RHF).
2025 if (egrsize == 2048)
2026 dd->tidtemplate = 1U << 29;
2027 else if (egrsize == 4096)
2028 dd->tidtemplate = 2U << 29;
2032 int __attribute__((weak)) qib_unordered_wc(void)
2038 * qib_6120_get_base_info - set chip-specific flags for user code
2039 * @rcd: the qlogic_ib ctxt
2040 * @kbase: qib_base_info pointer
2042 * We set the PCIE flag because the lower bandwidth on PCIe vs
2043 * HyperTransport can affect some user packet algorithms.
2045 static int qib_6120_get_base_info(struct qib_ctxtdata *rcd,
2046 struct qib_base_info *kinfo)
2048 if (qib_unordered_wc())
2049 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER;
2051 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2052 QIB_RUNTIME_FORCE_PIOAVAIL | QIB_RUNTIME_PIO_REGSWAPPED;
2057 static struct qib_message_header *
2058 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2060 return (struct qib_message_header *)
2061 &rhf_addr[sizeof(u64) / sizeof(u32)];
2064 static void qib_6120_config_ctxts(struct qib_devdata *dd)
2066 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt);
2067 if (qib_n_krcv_queues > 1) {
2068 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2069 if (dd->first_user_ctxt > dd->ctxtcnt)
2070 dd->first_user_ctxt = dd->ctxtcnt;
2071 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6;
2073 dd->first_user_ctxt = dd->num_pports;
2074 dd->n_krcv_queues = dd->first_user_ctxt;
2077 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2078 u32 updegr, u32 egrhd)
2080 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2082 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2085 static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd)
2089 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2090 if (rcd->rcvhdrtail_kvaddr)
2091 tail = qib_get_rcvhdrtail(rcd);
2093 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2094 return head == tail;
2098 * Used when we close any ctxt, for DMA already in flight
2099 * at close. Can't be done until we know hdrq size, so not
2100 * early in chip init.
2102 static void alloc_dummy_hdrq(struct qib_devdata *dd)
2104 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev,
2105 dd->rcd[0]->rcvhdrq_size,
2106 &dd->cspec->dummy_hdrq_phys,
2107 GFP_KERNEL | __GFP_COMP);
2108 if (!dd->cspec->dummy_hdrq) {
2109 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n");
2110 /* fallback to just 0'ing */
2111 dd->cspec->dummy_hdrq_phys = 0UL;
2116 * Modify the RCVCTRL register in chip-specific way. This
2117 * is a function because bit positions and (future) register
2118 * location is chip-specific, but the needed operations are
2119 * generic. <op> is a bit-mask because we often want to
2120 * do multiple modifications.
2122 static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op,
2125 struct qib_devdata *dd = ppd->dd;
2127 unsigned long flags;
2129 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2131 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2132 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2133 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2134 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2135 if (op & QIB_RCVCTRL_PKEY_ENB)
2136 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2137 if (op & QIB_RCVCTRL_PKEY_DIS)
2138 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2140 mask = (1ULL << dd->ctxtcnt) - 1;
2142 mask = (1ULL << ctxt);
2143 if (op & QIB_RCVCTRL_CTXT_ENB) {
2144 /* always done for specific ctxt */
2145 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2146 if (!(dd->flags & QIB_NODMA_RTAIL))
2147 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT;
2148 /* Write these registers before the context is enabled. */
2149 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2150 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2151 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2152 dd->rcd[ctxt]->rcvhdrq_phys);
2154 if (ctxt == 0 && !dd->cspec->dummy_hdrq)
2155 alloc_dummy_hdrq(dd);
2157 if (op & QIB_RCVCTRL_CTXT_DIS)
2158 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2159 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2160 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2161 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2162 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2163 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2164 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2165 /* arm rcv interrupt */
2166 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2167 dd->rhdrhead_intr_off;
2168 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2170 if (op & QIB_RCVCTRL_CTXT_ENB) {
2172 * Init the context registers also; if we were
2173 * disabled, tail and head should both be zero
2174 * already from the enable, but since we don't
2175 * know, we have to do it explictly.
2177 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2178 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2180 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2181 dd->rcd[ctxt]->head = val;
2182 /* If kctxt, interrupt on next receive. */
2183 if (ctxt < dd->first_user_ctxt)
2184 val |= dd->rhdrhead_intr_off;
2185 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2187 if (op & QIB_RCVCTRL_CTXT_DIS) {
2189 * Be paranoid, and never write 0's to these, just use an
2190 * unused page. Of course,
2191 * rcvhdraddr points to a large chunk of memory, so this
2192 * could still trash things, but at least it won't trash
2193 * page 0, and by disabling the ctxt, it should stop "soon",
2194 * even if a packet or two is in already in flight after we
2195 * disabled the ctxt. Only 6120 has this issue.
2198 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2199 dd->cspec->dummy_hdrq_phys);
2200 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2201 dd->cspec->dummy_hdrq_phys);
2205 for (i = 0; i < dd->cfgctxts; i++) {
2206 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2207 i, dd->cspec->dummy_hdrq_phys);
2208 qib_write_kreg_ctxt(dd, kr_rcvhdraddr,
2209 i, dd->cspec->dummy_hdrq_phys);
2213 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2217 * Modify the SENDCTRL register in chip-specific way. This
2218 * is a function there may be multiple such registers with
2219 * slightly different layouts. Only operations actually used
2220 * are implemented yet.
2221 * Chip requires no back-back sendctrl writes, so write
2222 * scratch register after writing sendctrl
2224 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op)
2226 struct qib_devdata *dd = ppd->dd;
2227 u64 tmp_dd_sendctrl;
2228 unsigned long flags;
2230 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2232 /* First the ones that are "sticky", saved in shadow */
2233 if (op & QIB_SENDCTRL_CLEAR)
2235 if (op & QIB_SENDCTRL_SEND_DIS)
2236 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable);
2237 else if (op & QIB_SENDCTRL_SEND_ENB)
2238 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable);
2239 if (op & QIB_SENDCTRL_AVAIL_DIS)
2240 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2241 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2242 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd);
2244 if (op & QIB_SENDCTRL_DISARM_ALL) {
2247 tmp_dd_sendctrl = dd->sendctrl;
2249 * disarm any that are not yet launched, disabling sends
2250 * and updates until done.
2252 last = dd->piobcnt2k + dd->piobcnt4k;
2254 ~(SYM_MASK(SendCtrl, PIOEnable) |
2255 SYM_MASK(SendCtrl, PIOBufAvailUpd));
2256 for (i = 0; i < last; i++) {
2257 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl |
2258 SYM_MASK(SendCtrl, Disarm) | i);
2259 qib_write_kreg(dd, kr_scratch, 0);
2263 tmp_dd_sendctrl = dd->sendctrl;
2265 if (op & QIB_SENDCTRL_FLUSH)
2266 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2267 if (op & QIB_SENDCTRL_DISARM)
2268 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2269 ((op & QIB_6120_SendCtrl_DisarmPIOBuf_RMASK) <<
2270 SYM_LSB(SendCtrl, DisarmPIOBuf));
2271 if (op & QIB_SENDCTRL_AVAIL_BLIP)
2272 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2274 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2275 qib_write_kreg(dd, kr_scratch, 0);
2277 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2278 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2279 qib_write_kreg(dd, kr_scratch, 0);
2282 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2284 if (op & QIB_SENDCTRL_FLUSH) {
2287 * ensure writes have hit chip, then do a few
2288 * more reads, to allow DMA of pioavail registers
2289 * to occur, so in-memory copy is in sync with
2290 * the chip. Not always safe to sleep.
2292 v = qib_read_kreg32(dd, kr_scratch);
2293 qib_write_kreg(dd, kr_scratch, v);
2294 v = qib_read_kreg32(dd, kr_scratch);
2295 qib_write_kreg(dd, kr_scratch, v);
2296 qib_read_kreg32(dd, kr_scratch);
2301 * qib_portcntr_6120 - read a per-port counter
2302 * @dd: the qlogic_ib device
2303 * @creg: the counter to snapshot
2305 static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg)
2308 struct qib_devdata *dd = ppd->dd;
2310 /* 0xffff for unimplemented or synthesized counters */
2311 static const u16 xlator[] = {
2312 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2313 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2314 [QIBPORTCNTR_PSXMITDATA] = 0xffff,
2315 [QIBPORTCNTR_PSXMITPKTS] = 0xffff,
2316 [QIBPORTCNTR_PSXMITWAIT] = 0xffff,
2317 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2318 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2319 [QIBPORTCNTR_PSRCVDATA] = 0xffff,
2320 [QIBPORTCNTR_PSRCVPKTS] = 0xffff,
2321 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2322 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2323 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2324 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2325 [QIBPORTCNTR_RXLOCALPHYERR] = 0xffff,
2326 [QIBPORTCNTR_RXVLERR] = 0xffff,
2327 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2328 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2329 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2330 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2331 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2332 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2333 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2334 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2335 [QIBPORTCNTR_EXCESSBUFOVFL] = 0xffff,
2336 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2337 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2338 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2339 [QIBPORTCNTR_LLI] = 0xffff,
2340 [QIBPORTCNTR_PSINTERVAL] = 0xffff,
2341 [QIBPORTCNTR_PSSTART] = 0xffff,
2342 [QIBPORTCNTR_PSSTAT] = 0xffff,
2343 [QIBPORTCNTR_VL15PKTDROP] = 0xffff,
2344 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2345 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2348 if (reg >= ARRAY_SIZE(xlator)) {
2349 qib_devinfo(ppd->dd->pcidev,
2350 "Unimplemented portcounter %u\n", reg);
2355 /* handle counters requests not implemented as chip counters */
2356 if (reg == QIBPORTCNTR_LLI)
2357 ret = dd->cspec->lli_errs;
2358 else if (reg == QIBPORTCNTR_EXCESSBUFOVFL)
2359 ret = dd->cspec->overrun_thresh_errs;
2360 else if (reg == QIBPORTCNTR_KHDROVFL) {
2363 /* sum over all kernel contexts */
2364 for (i = 0; i < dd->first_user_ctxt; i++)
2365 ret += read_6120_creg32(dd, cr_portovfl + i);
2366 } else if (reg == QIBPORTCNTR_PSSTAT)
2367 ret = dd->cspec->pma_sample_status;
2372 * only fast incrementing counters are 64bit; use 32 bit reads to
2373 * avoid two independent reads when on opteron
2375 if (creg == cr_wordsend || creg == cr_wordrcv ||
2376 creg == cr_pktsend || creg == cr_pktrcv)
2377 ret = read_6120_creg(dd, creg);
2379 ret = read_6120_creg32(dd, creg);
2380 if (creg == cr_ibsymbolerr) {
2381 if (dd->cspec->ibdeltainprog)
2382 ret -= ret - dd->cspec->ibsymsnap;
2383 ret -= dd->cspec->ibsymdelta;
2384 } else if (creg == cr_iblinkerrrecov) {
2385 if (dd->cspec->ibdeltainprog)
2386 ret -= ret - dd->cspec->iblnkerrsnap;
2387 ret -= dd->cspec->iblnkerrdelta;
2389 if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */
2390 ret += dd->cspec->rxfc_unsupvl_errs;
2397 * Device counter names (not port-specific), one line per stat,
2398 * single string. Used by utilities like ipathstats to print the stats
2399 * in a way which works for different versions of drivers, without changing
2400 * the utility. Names need to be 12 chars or less (w/o newline), for proper
2401 * display by utility.
2402 * Non-error counters are first.
2403 * Start of "error" conters is indicated by a leading "E " on the first
2404 * "error" counter, and doesn't count in label length.
2405 * The EgrOvfl list needs to be last so we truncate them at the configured
2406 * context count for the device.
2407 * cntr6120indices contains the corresponding register indices.
2409 static const char cntr6120names[] =
2420 static const size_t cntr6120indices[] = {
2433 * same as cntr6120names and cntr6120indices, but for port-specific counters.
2434 * portcntr6120indices is somewhat complicated by some registers needing
2435 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
2437 static const char portcntr6120names[] =
2469 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
2470 static const size_t portcntr6120indices[] = {
2471 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
2473 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
2474 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
2476 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
2477 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
2479 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
2480 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
2481 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
2482 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
2483 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
2484 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
2485 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
2486 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
2487 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
2489 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
2490 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
2491 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
2492 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
2493 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
2494 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
2502 /* do all the setup to make the counter reads efficient later */
2503 static void init_6120_cntrnames(struct qib_devdata *dd)
2508 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts;
2510 /* we always have at least one counter before the egrovfl */
2511 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
2513 s = strchr(s + 1, '\n');
2517 dd->cspec->ncntrs = i;
2519 /* full list; size is without terminating null */
2520 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1;
2522 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2523 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
2524 * sizeof(u64), GFP_KERNEL);
2525 if (!dd->cspec->cntrs)
2526 qib_dev_err(dd, "Failed allocation for counters\n");
2528 for (i = 0, s = (char *)portcntr6120names; s; i++)
2529 s = strchr(s + 1, '\n');
2530 dd->cspec->nportcntrs = i - 1;
2531 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2532 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
2533 * sizeof(u64), GFP_KERNEL);
2534 if (!dd->cspec->portcntrs)
2535 qib_dev_err(dd, "Failed allocation for portcounters\n");
2538 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
2544 ret = dd->cspec->cntrnamelen;
2546 ret = 0; /* final read after getting everything */
2548 *namep = (char *)cntr6120names;
2550 u64 *cntr = dd->cspec->cntrs;
2553 ret = dd->cspec->ncntrs * sizeof(u64);
2554 if (!cntr || pos >= ret) {
2555 /* everything read, or couldn't get memory */
2560 ret = 0; /* final read after getting everything */
2564 for (i = 0; i < dd->cspec->ncntrs; i++)
2565 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]);
2571 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
2572 char **namep, u64 **cntrp)
2577 ret = dd->cspec->portcntrnamelen;
2579 ret = 0; /* final read after getting everything */
2581 *namep = (char *)portcntr6120names;
2583 u64 *cntr = dd->cspec->portcntrs;
2584 struct qib_pportdata *ppd = &dd->pport[port];
2587 ret = dd->cspec->nportcntrs * sizeof(u64);
2588 if (!cntr || pos >= ret) {
2589 /* everything read, or couldn't get memory */
2594 for (i = 0; i < dd->cspec->nportcntrs; i++) {
2595 if (portcntr6120indices[i] & _PORT_VIRT_FLAG)
2596 *cntr++ = qib_portcntr_6120(ppd,
2597 portcntr6120indices[i] &
2600 *cntr++ = read_6120_creg32(dd,
2601 portcntr6120indices[i]);
2608 static void qib_chk_6120_errormask(struct qib_devdata *dd)
2612 unsigned long errormask;
2613 unsigned long hwerrs;
2615 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED))
2618 errormask = qib_read_kreg64(dd, kr_errmask);
2620 if (errormask == dd->cspec->errormask)
2624 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2625 ctrl = qib_read_kreg32(dd, kr_control);
2627 qib_write_kreg(dd, kr_errmask,
2628 dd->cspec->errormask);
2630 if ((hwerrs & dd->cspec->hwerrmask) ||
2631 (ctrl & QLOGIC_IB_C_FREEZEMODE)) {
2632 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2633 qib_write_kreg(dd, kr_errclear, 0ULL);
2634 /* force re-interrupt of pending events, just in case */
2635 qib_write_kreg(dd, kr_intclear, 0ULL);
2636 qib_devinfo(dd->pcidev,
2637 "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n",
2638 fixed, errormask, (unsigned long)dd->cspec->errormask,
2644 * qib_get_faststats - get word counters from chip before they overflow
2645 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
2647 * This needs more work; in particular, decision on whether we really
2648 * need traffic_wds done the way it is
2649 * called from add_timer
2651 static void qib_get_6120_faststats(unsigned long opaque)
2653 struct qib_devdata *dd = (struct qib_devdata *) opaque;
2654 struct qib_pportdata *ppd = dd->pport;
2655 unsigned long flags;
2659 * don't access the chip while running diags, or memory diags can
2662 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
2663 /* but re-arm the timer, for diags case; won't hurt other */
2667 * We now try to maintain an activity timer, based on traffic
2668 * exceeding a threshold, so we need to check the word-counts
2669 * even if they are 64-bit.
2671 traffic_wds = qib_portcntr_6120(ppd, cr_wordsend) +
2672 qib_portcntr_6120(ppd, cr_wordrcv);
2673 spin_lock_irqsave(&dd->eep_st_lock, flags);
2674 traffic_wds -= dd->traffic_wds;
2675 dd->traffic_wds += traffic_wds;
2676 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
2677 atomic_add(5, &dd->active_time); /* S/B #define */
2678 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
2680 qib_chk_6120_errormask(dd);
2682 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
2685 /* no interrupt fallback for these chips */
2686 static int qib_6120_nointr_fallback(struct qib_devdata *dd)
2692 * reset the XGXS (between serdes and IBC). Slightly less intrusive
2693 * than resetting the IBC or external link state, and useful in some
2694 * cases to cause some retraining. To do this right, we reset IBC
2697 static void qib_6120_xgxs_reset(struct qib_pportdata *ppd)
2700 struct qib_devdata *dd = ppd->dd;
2702 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
2703 val = prev_val | QLOGIC_IB_XGXS_RESET;
2704 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
2705 qib_write_kreg(dd, kr_control,
2706 dd->control & ~QLOGIC_IB_C_LINKENABLE);
2707 qib_write_kreg(dd, kr_xgxs_cfg, val);
2708 qib_read_kreg32(dd, kr_scratch);
2709 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
2710 qib_write_kreg(dd, kr_control, dd->control);
2713 static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which)
2718 case QIB_IB_CFG_LWID:
2719 ret = ppd->link_width_active;
2722 case QIB_IB_CFG_SPD:
2723 ret = ppd->link_speed_active;
2726 case QIB_IB_CFG_LWID_ENB:
2727 ret = ppd->link_width_enabled;
2730 case QIB_IB_CFG_SPD_ENB:
2731 ret = ppd->link_speed_enabled;
2734 case QIB_IB_CFG_OP_VLS:
2735 ret = ppd->vls_operational;
2738 case QIB_IB_CFG_VL_HIGH_CAP:
2742 case QIB_IB_CFG_VL_LOW_CAP:
2746 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2747 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2751 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2752 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2756 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2757 /* will only take effect when the link state changes */
2758 ret = (ppd->dd->cspec->ibcctrl &
2759 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2760 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2763 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2764 ret = 0; /* no heartbeat on this chip */
2767 case QIB_IB_CFG_PMA_TICKS:
2768 ret = 250; /* 1 usec. */
2779 * We assume range checking is already done, if needed.
2781 static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2783 struct qib_devdata *dd = ppd->dd;
2789 case QIB_IB_CFG_LWID_ENB:
2790 ppd->link_width_enabled = val;
2793 case QIB_IB_CFG_SPD_ENB:
2794 ppd->link_speed_enabled = val;
2797 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2798 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2801 dd->cspec->ibcctrl &=
2802 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2803 dd->cspec->ibcctrl |= (u64) val <<
2804 SYM_LSB(IBCCtrl, OverrunThreshold);
2805 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2806 qib_write_kreg(dd, kr_scratch, 0);
2810 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2811 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2814 dd->cspec->ibcctrl &=
2815 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2816 dd->cspec->ibcctrl |= (u64) val <<
2817 SYM_LSB(IBCCtrl, PhyerrThreshold);
2818 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2819 qib_write_kreg(dd, kr_scratch, 0);
2823 case QIB_IB_CFG_PKEYS: /* update pkeys */
2824 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2825 ((u64) ppd->pkeys[2] << 32) |
2826 ((u64) ppd->pkeys[3] << 48);
2827 qib_write_kreg(dd, kr_partitionkey, val64);
2830 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2831 /* will only take effect when the link state changes */
2832 if (val == IB_LINKINITCMD_POLL)
2833 dd->cspec->ibcctrl &=
2834 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2836 dd->cspec->ibcctrl |=
2837 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2838 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2839 qib_write_kreg(dd, kr_scratch, 0);
2842 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2844 * Update our housekeeping variables, and set IBC max
2845 * size, same as init code; max IBC is max we allow in
2846 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2847 * Set even if it's unchanged, print debug message only
2850 val = (ppd->ibmaxlen >> 2) + 1;
2851 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2852 dd->cspec->ibcctrl |= (u64)val <<
2853 SYM_LSB(IBCCtrl, MaxPktLen);
2854 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2855 qib_write_kreg(dd, kr_scratch, 0);
2858 case QIB_IB_CFG_LSTATE: /* set the IB link state */
2859 switch (val & 0xffff0000) {
2860 case IB_LINKCMD_DOWN:
2861 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2862 if (!dd->cspec->ibdeltainprog) {
2863 dd->cspec->ibdeltainprog = 1;
2864 dd->cspec->ibsymsnap =
2865 read_6120_creg32(dd, cr_ibsymbolerr);
2866 dd->cspec->iblnkerrsnap =
2867 read_6120_creg32(dd, cr_iblinkerrrecov);
2871 case IB_LINKCMD_ARMED:
2872 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2875 case IB_LINKCMD_ACTIVE:
2876 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2881 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2884 switch (val & 0xffff) {
2885 case IB_LINKINITCMD_NOP:
2889 case IB_LINKINITCMD_POLL:
2890 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2893 case IB_LINKINITCMD_SLEEP:
2894 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2897 case IB_LINKINITCMD_DISABLE:
2898 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2903 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2907 qib_set_ib_6120_lstate(ppd, lcmd, licmd);
2910 case QIB_IB_CFG_HRTBT:
2921 static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what)
2924 if (!strncmp(what, "ibc", 3)) {
2925 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2926 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2927 ppd->dd->unit, ppd->port);
2928 } else if (!strncmp(what, "off", 3)) {
2929 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2930 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
2931 "(normal)\n", ppd->dd->unit, ppd->port);
2935 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl);
2936 qib_write_kreg(ppd->dd, kr_scratch, 0);
2941 static void pma_6120_timer(unsigned long data)
2943 struct qib_pportdata *ppd = (struct qib_pportdata *)data;
2944 struct qib_chip_specific *cs = ppd->dd->cspec;
2945 struct qib_ibport *ibp = &ppd->ibport_data;
2946 unsigned long flags;
2948 spin_lock_irqsave(&ibp->lock, flags);
2949 if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) {
2950 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2951 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2952 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2953 mod_timer(&cs->pma_timer,
2954 jiffies + usecs_to_jiffies(ibp->pma_sample_interval));
2955 } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) {
2956 u64 ta, tb, tc, td, te;
2958 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2959 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te);
2961 cs->sword = ta - cs->sword;
2962 cs->rword = tb - cs->rword;
2963 cs->spkts = tc - cs->spkts;
2964 cs->rpkts = td - cs->rpkts;
2965 cs->xmit_wait = te - cs->xmit_wait;
2967 spin_unlock_irqrestore(&ibp->lock, flags);
2971 * Note that the caller has the ibp->lock held.
2973 static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv,
2976 struct qib_chip_specific *cs = ppd->dd->cspec;
2978 if (start && intv) {
2979 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED;
2980 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start));
2982 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2983 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2984 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2985 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv));
2987 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2996 static u32 qib_6120_iblink_state(u64 ibcs)
2998 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
3001 case IB_6120_L_STATE_INIT:
3002 state = IB_PORT_INIT;
3004 case IB_6120_L_STATE_ARM:
3005 state = IB_PORT_ARMED;
3007 case IB_6120_L_STATE_ACTIVE:
3009 case IB_6120_L_STATE_ACT_DEFER:
3010 state = IB_PORT_ACTIVE;
3012 default: /* fall through */
3013 case IB_6120_L_STATE_DOWN:
3014 state = IB_PORT_DOWN;
3020 /* returns the IBTA port state, rather than the IBC link training state */
3021 static u8 qib_6120_phys_portstate(u64 ibcs)
3023 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3024 return qib_6120_physportstate[state];
3027 static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3029 unsigned long flags;
3031 spin_lock_irqsave(&ppd->lflags_lock, flags);
3032 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3033 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3036 if (ppd->dd->cspec->ibdeltainprog) {
3037 ppd->dd->cspec->ibdeltainprog = 0;
3038 ppd->dd->cspec->ibsymdelta +=
3039 read_6120_creg32(ppd->dd, cr_ibsymbolerr) -
3040 ppd->dd->cspec->ibsymsnap;
3041 ppd->dd->cspec->iblnkerrdelta +=
3042 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) -
3043 ppd->dd->cspec->iblnkerrsnap;
3047 ppd->dd->cspec->lli_counter = 0;
3048 if (!ppd->dd->cspec->ibdeltainprog) {
3049 ppd->dd->cspec->ibdeltainprog = 1;
3050 ppd->dd->cspec->ibsymsnap =
3051 read_6120_creg32(ppd->dd, cr_ibsymbolerr);
3052 ppd->dd->cspec->iblnkerrsnap =
3053 read_6120_creg32(ppd->dd, cr_iblinkerrrecov);
3058 qib_6120_setup_setextled(ppd, ibup);
3063 /* Does read/modify/write to appropriate registers to
3064 * set output and direction bits selected by mask.
3065 * these are in their canonical postions (e.g. lsb of
3066 * dir will end up in D48 of extctrl on existing chips).
3067 * returns contents of GP Inputs.
3069 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3071 u64 read_val, new_out;
3072 unsigned long flags;
3075 /* some bits being written, lock access to GPIO */
3078 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3079 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3080 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3081 new_out = (dd->cspec->gpio_out & ~mask) | out;
3083 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3084 qib_write_kreg(dd, kr_gpio_out, new_out);
3085 dd->cspec->gpio_out = new_out;
3086 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3089 * It is unlikely that a read at this time would get valid
3090 * data on a pin whose direction line was set in the same
3091 * call to this function. We include the read here because
3092 * that allows us to potentially combine a change on one pin with
3093 * a read on another, and because the old code did something like
3096 read_val = qib_read_kreg64(dd, kr_extstatus);
3097 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3101 * Read fundamental info we need to use the chip. These are
3102 * the registers that describe chip capabilities, and are
3103 * saved in shadow registers.
3105 static void get_6120_chip_params(struct qib_devdata *dd)
3111 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3113 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3114 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3115 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3116 dd->palign = qib_read_kreg32(dd, kr_palign);
3117 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3118 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3120 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3122 val = qib_read_kreg64(dd, kr_sendpiosize);
3123 dd->piosize2k = val & ~0U;
3124 dd->piosize4k = val >> 32;
3126 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3128 mtu = QIB_DEFAULT_MTU;
3129 dd->pport->ibmtu = (u32)mtu;
3131 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3132 dd->piobcnt2k = val & ~0U;
3133 dd->piobcnt4k = val >> 32;
3134 /* these may be adjusted in init_chip_wc_pat() */
3135 dd->pio2kbase = (u32 __iomem *)
3136 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase);
3137 if (dd->piobcnt4k) {
3138 dd->pio4kbase = (u32 __iomem *)
3139 (((char __iomem *) dd->kregbase) +
3140 (dd->piobufbase >> 32));
3142 * 4K buffers take 2 pages; we use roundup just to be
3143 * paranoid; we calculate it once here, rather than on
3146 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3149 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3151 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3152 (sizeof(u64) * BITS_PER_BYTE / 2);
3156 * The chip base addresses in cspec and cpspec have to be set
3157 * after possible init_chip_wc_pat(), rather than in
3158 * get_6120_chip_params(), so split out as separate function
3160 static void set_6120_baseaddrs(struct qib_devdata *dd)
3163 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3164 dd->cspec->cregbase = (u64 __iomem *)
3165 ((char __iomem *) dd->kregbase + cregbase);
3167 dd->egrtidbase = (u64 __iomem *)
3168 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3172 * Write the final few registers that depend on some of the
3173 * init setup. Done late in init, just before bringing up
3176 static int qib_late_6120_initreg(struct qib_devdata *dd)
3181 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3182 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3183 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3184 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3185 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3186 if (val != dd->pioavailregs_phys) {
3187 qib_dev_err(dd, "Catastrophic software error, "
3188 "SendPIOAvailAddr written as %lx, "
3189 "read back as %llx\n",
3190 (unsigned long) dd->pioavailregs_phys,
3191 (unsigned long long) val);
3197 static int init_6120_variables(struct qib_devdata *dd)
3200 struct qib_pportdata *ppd;
3203 ppd = (struct qib_pportdata *)(dd + 1);
3207 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3208 ppd->cpspec = NULL; /* not used in this chip */
3210 spin_lock_init(&dd->cspec->kernel_tid_lock);
3211 spin_lock_init(&dd->cspec->user_tid_lock);
3212 spin_lock_init(&dd->cspec->rcvmod_lock);
3213 spin_lock_init(&dd->cspec->gpio_lock);
3215 /* we haven't yet set QIB_PRESENT, so use read directly */
3216 dd->revision = readq(&dd->kregbase[kr_revision]);
3218 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
3219 qib_dev_err(dd, "Revision register read failure, "
3220 "giving up initialization\n");
3224 dd->flags |= QIB_PRESENT; /* now register routines work */
3226 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3228 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3231 get_6120_chip_params(dd);
3232 pe_boardname(dd); /* fill in boardname */
3235 * GPIO bits for TWSI data and clock,
3236 * used for serial EEPROM.
3238 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
3239 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
3240 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV;
3242 if (qib_unordered_wc())
3243 dd->flags |= QIB_PIO_FLUSH_WC;
3246 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
3247 * 2 is Some Misc, 3 is reserved for future.
3249 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
3251 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
3252 if (qib_unordered_wc())
3253 dd->eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
3255 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
3257 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
3259 qib_init_pportdata(ppd, dd, 0, 1);
3260 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
3261 ppd->link_speed_supported = QIB_IB_SDR;
3262 ppd->link_width_enabled = IB_WIDTH_4X;
3263 ppd->link_speed_enabled = ppd->link_speed_supported;
3264 /* these can't change for this chip, so set once */
3265 ppd->link_width_active = ppd->link_width_enabled;
3266 ppd->link_speed_active = ppd->link_speed_enabled;
3267 ppd->vls_supported = IB_VL_VL0;
3268 ppd->vls_operational = ppd->vls_supported;
3270 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
3271 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
3274 /* we always allocate at least 2048 bytes for eager buffers */
3275 ret = ib_mtu_enum_to_int(qib_ibmtu);
3276 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
3278 qib_6120_tidtemplate(dd);
3281 * We can request a receive interrupt for 1 or
3282 * more packets from current offset. For now, we set this
3283 * up for a single packet.
3285 dd->rhdrhead_intr_off = 1ULL << 32;
3287 /* setup the stats timer; the add_timer is done at end of init */
3288 init_timer(&dd->stats_timer);
3289 dd->stats_timer.function = qib_get_6120_faststats;
3290 dd->stats_timer.data = (unsigned long) dd;
3292 init_timer(&dd->cspec->pma_timer);
3293 dd->cspec->pma_timer.function = pma_6120_timer;
3294 dd->cspec->pma_timer.data = (unsigned long) ppd;
3296 dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3298 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
3299 qib_6120_config_ctxts(dd);
3300 qib_set_ctxtcnt(dd);
3303 ret = init_chip_wc_pat(dd, 0);
3307 set_6120_baseaddrs(dd); /* set chip access pointers now */
3313 qib_num_cfg_vls = 1; /* if any 6120's, only one VL */
3315 ret = qib_create_ctxts(dd);
3316 init_6120_cntrnames(dd);
3318 /* use all of 4KB buffers for the kernel, otherwise 16 */
3319 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16;
3321 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs;
3322 dd->pbufsctxt = dd->lastctxt_piobuf /
3323 (dd->cfgctxts - dd->first_user_ctxt);
3332 * For this chip, we want to use the same buffer every time
3333 * when we are trying to bring the link up (they are always VL15
3334 * packets). At that link state the packet should always go out immediately
3335 * (or at least be discarded at the tx interface if the link is down).
3336 * If it doesn't, and the buffer isn't available, that means some other
3337 * sender has gotten ahead of us, and is preventing our packet from going
3338 * out. In that case, we flush all packets, and try again. If that still
3339 * fails, we fail the request, and hope things work the next time around.
3341 * We don't need very complicated heuristics on whether the packet had
3342 * time to go out or not, since even at SDR 1X, it goes out in very short
3343 * time periods, covered by the chip reads done here and as part of the
3346 static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3349 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1;
3352 * always blip to get avail list updated, since it's almost
3353 * always needed, and is fairly cheap.
3355 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3356 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3357 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3361 sendctrl_6120_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
3362 QIB_SENDCTRL_AVAIL_BLIP);
3363 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
3364 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3365 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3370 static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
3373 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
3374 struct qib_devdata *dd = ppd->dd;
3377 if (((pbc >> 32) & PBC_6120_VL15_SEND_CTRL) &&
3378 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
3379 buf = get_6120_link_buf(ppd, pbufnum);
3382 if ((plen + 1) > dd->piosize2kmax_dwords)
3383 first = dd->piobcnt2k;
3386 /* try 4k if all 2k busy, so same last for both sizes */
3387 last = dd->piobcnt2k + dd->piobcnt4k - 1;
3388 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
3393 static int init_sdma_6120_regs(struct qib_pportdata *ppd)
3398 static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd)
3403 static int qib_sdma_6120_busy(struct qib_pportdata *ppd)
3408 static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail)
3412 static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
3416 static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
3421 * the pbc doesn't need a VL15 indicator, but we need it for link_buf.
3422 * The chip ignores the bit if set.
3424 static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen,
3427 return vl == 15 ? PBC_6120_VL15_SEND_CTRL : 0;
3430 static void qib_6120_initvl15_bufs(struct qib_devdata *dd)
3434 static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd)
3436 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt;
3437 rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt;
3440 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start,
3441 u32 len, u32 avail, struct qib_ctxtdata *rcd)
3445 static void writescratch(struct qib_devdata *dd, u32 val)
3447 (void) qib_write_kreg(dd, kr_scratch, val);
3450 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum)
3455 /* Dummy function, as 6120 boards never disable EEPROM Write */
3456 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen)
3462 * qib_init_iba6120_funcs - set up the chip-specific function pointers
3463 * @pdev: pci_dev of the qlogic_ib device
3464 * @ent: pci_device_id matching this chip
3466 * This is global, and is called directly at init to set up the
3467 * chip-specific function pointers for later use.
3469 * It also allocates/partially-inits the qib_devdata struct for
3472 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3473 const struct pci_device_id *ent)
3475 struct qib_devdata *dd;
3478 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) +
3479 sizeof(struct qib_chip_specific));
3483 dd->f_bringup_serdes = qib_6120_bringup_serdes;
3484 dd->f_cleanup = qib_6120_setup_cleanup;
3485 dd->f_clear_tids = qib_6120_clear_tids;
3486 dd->f_free_irq = qib_6120_free_irq;
3487 dd->f_get_base_info = qib_6120_get_base_info;
3488 dd->f_get_msgheader = qib_6120_get_msgheader;
3489 dd->f_getsendbuf = qib_6120_getsendbuf;
3490 dd->f_gpio_mod = gpio_6120_mod;
3491 dd->f_eeprom_wen = qib_6120_eeprom_wen;
3492 dd->f_hdrqempty = qib_6120_hdrqempty;
3493 dd->f_ib_updown = qib_6120_ib_updown;
3494 dd->f_init_ctxt = qib_6120_init_ctxt;
3495 dd->f_initvl15_bufs = qib_6120_initvl15_bufs;
3496 dd->f_intr_fallback = qib_6120_nointr_fallback;
3497 dd->f_late_initreg = qib_late_6120_initreg;
3498 dd->f_setpbc_control = qib_6120_setpbc_control;
3499 dd->f_portcntr = qib_portcntr_6120;
3500 dd->f_put_tid = (dd->minrev >= 2) ?
3501 qib_6120_put_tid_2 :
3503 dd->f_quiet_serdes = qib_6120_quiet_serdes;
3504 dd->f_rcvctrl = rcvctrl_6120_mod;
3505 dd->f_read_cntrs = qib_read_6120cntrs;
3506 dd->f_read_portcntrs = qib_read_6120portcntrs;
3507 dd->f_reset = qib_6120_setup_reset;
3508 dd->f_init_sdma_regs = init_sdma_6120_regs;
3509 dd->f_sdma_busy = qib_sdma_6120_busy;
3510 dd->f_sdma_gethead = qib_sdma_6120_gethead;
3511 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl;
3512 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt;
3513 dd->f_sdma_update_tail = qib_sdma_update_6120_tail;
3514 dd->f_sendctrl = sendctrl_6120_mod;
3515 dd->f_set_armlaunch = qib_set_6120_armlaunch;
3516 dd->f_set_cntr_sample = qib_set_cntr_6120_sample;
3517 dd->f_iblink_state = qib_6120_iblink_state;
3518 dd->f_ibphys_portstate = qib_6120_phys_portstate;
3519 dd->f_get_ib_cfg = qib_6120_get_ib_cfg;
3520 dd->f_set_ib_cfg = qib_6120_set_ib_cfg;
3521 dd->f_set_ib_loopback = qib_6120_set_loopback;
3522 dd->f_set_intr_state = qib_6120_set_intr_state;
3523 dd->f_setextled = qib_6120_setup_setextled;
3524 dd->f_txchk_change = qib_6120_txchk_change;
3525 dd->f_update_usrhead = qib_update_6120_usrhead;
3526 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr;
3527 dd->f_xgxs_reset = qib_6120_xgxs_reset;
3528 dd->f_writescratch = writescratch;
3529 dd->f_tempsense_rd = qib_6120_tempsense_rd;
3531 * Do remaining pcie setup and save pcie values in dd.
3532 * Any error printing is already done by the init code.
3533 * On return, we have the chip mapped and accessible,
3534 * but chip registers are not set up until start of
3535 * init_6120_variables.
3537 ret = qib_pcie_ddinit(dd, pdev, ent);
3541 /* initialize chip-specific variables */
3542 ret = init_6120_variables(dd);
3549 if (qib_pcie_params(dd, 8, NULL, NULL))
3550 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
3551 "continuing anyway\n");
3552 dd->cspec->irq = pdev->irq; /* save IRQ */
3554 /* clear diagctrl register, in case diags were running and crashed */
3555 qib_write_kreg(dd, kr_hwdiagctrl, 0);
3557 if (qib_read_kreg64(dd, kr_hwerrstatus) &
3558 QLOGIC_IB_HWE_SERDESPLLFAILED)
3559 qib_write_kreg(dd, kr_hwerrclear,
3560 QLOGIC_IB_HWE_SERDESPLLFAILED);
3562 /* setup interrupt handler (interrupt type handled above) */
3563 qib_setup_6120_interrupt(dd);
3564 /* Note that qpn_mask is set by qib_6120_config_ctxts() first */
3565 qib_6120_init_hwerrors(dd);
3570 qib_pcie_ddcleanup(dd);
3572 qib_free_devdata(dd);