2 * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * This file contains all of the code that is specific to the SerDes
35 * on the QLogic_IB 7220 chip.
38 #include <linux/pci.h>
39 #include <linux/delay.h>
45 * Same as in qib_iba7220.c, but just the registers needed here.
46 * Could move whole set to qib_7220.h, but decided better to keep
49 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
50 #define kr_hwerrclear KREG_IDX(HwErrClear)
51 #define kr_hwerrmask KREG_IDX(HwErrMask)
52 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
53 #define kr_ibcstatus KREG_IDX(IBCStatus)
54 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
55 #define kr_scratch KREG_IDX(Scratch)
56 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
57 /* these are used only here, not in qib_iba7220.c */
58 #define kr_ibsd_epb_access_ctrl KREG_IDX(ibsd_epb_access_ctrl)
59 #define kr_ibsd_epb_transaction_reg KREG_IDX(ibsd_epb_transaction_reg)
60 #define kr_pciesd_epb_transaction_reg KREG_IDX(pciesd_epb_transaction_reg)
61 #define kr_pciesd_epb_access_ctrl KREG_IDX(pciesd_epb_access_ctrl)
62 #define kr_serdes_ddsrxeq0 KREG_IDX(SerDes_DDSRXEQ0)
65 * The IBSerDesMappTable is a memory that holds values to be stored in
66 * various SerDes registers by IBC.
68 #define kr_serdes_maptable KREG_IDX(IBSerDesMappTable)
71 * Below used for sdnum parameter, selecting one of the two sections
72 * used for PCIe, or the single SerDes used for IB.
74 #define PCIE_SERDES0 0
75 #define PCIE_SERDES1 1
78 * The EPB requires addressing in a particular form. EPB_LOC() is intended
79 * to make #definitions a little more readable.
81 #define EPB_ADDR_SHF 8
82 #define EPB_LOC(chn, elt, reg) \
83 (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \
85 #define EPB_IB_QUAD0_CS_SHF (25)
86 #define EPB_IB_QUAD0_CS (1U << EPB_IB_QUAD0_CS_SHF)
87 #define EPB_IB_UC_CS_SHF (26)
88 #define EPB_PCIE_UC_CS_SHF (27)
89 #define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8))
91 /* Forward declarations. */
92 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
94 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
96 static int qib_sd_trimdone_poll(struct qib_devdata *dd);
97 static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where);
98 static int qib_sd_setvals(struct qib_devdata *dd);
99 static int qib_sd_early(struct qib_devdata *dd);
100 static int qib_sd_dactrim(struct qib_devdata *dd);
101 static int qib_internal_presets(struct qib_devdata *dd);
102 /* Tweak the register (CMUCTRL5) that contains the TRIMSELF controls */
103 static int qib_sd_trimself(struct qib_devdata *dd, int val);
104 static int epb_access(struct qib_devdata *dd, int sdnum, int claim);
107 * Below keeps track of whether the "once per power-on" initialization has
108 * been done, because uC code Version 1.32.17 or higher allows the uC to
109 * be reset at will, and Automatic Equalization may require it. So the
110 * state of the reset "pin", is no longer valid. Instead, we check for the
111 * actual uC code having been loaded.
113 static int qib_ibsd_ucode_loaded(struct qib_pportdata *ppd)
115 struct qib_devdata *dd = ppd->dd;
116 if (!dd->cspec->serdes_first_init_done && (qib_sd7220_ib_vfy(dd) > 0))
117 dd->cspec->serdes_first_init_done = 1;
118 return dd->cspec->serdes_first_init_done;
121 /* repeat #define for local use. "Real" #define is in qib_iba7220.c */
122 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
123 #define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF))
124 #define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF))
125 #define UC_PAR_CLR_D 8
126 #define UC_PAR_CLR_M 0xC
127 #define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS)
128 #define START_EQ1(chan) EPB_LOC(chan, 7, 0x27)
130 void qib_sd7220_clr_ibpar(struct qib_devdata *dd)
134 /* clear, then re-enable parity errs */
135 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6,
136 UC_PAR_CLR_D, UC_PAR_CLR_M);
138 qib_dev_err(dd, "Failed clearing IBSerDes Parity err\n");
141 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0,
144 qib_read_kreg32(dd, kr_scratch);
146 qib_write_kreg(dd, kr_hwerrclear,
147 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
148 qib_read_kreg32(dd, kr_scratch);
154 * After a reset or other unusual event, the epb interface may need
155 * to be re-synchronized, between the host and the uC.
156 * returns <0 for failure to resync within IBSD_RESYNC_TRIES (not expected)
158 #define IBSD_RESYNC_TRIES 3
159 #define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS)
160 #define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS)
162 static int qib_resync_ibepb(struct qib_devdata *dd)
164 int ret, pat, tries, chn;
169 for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) {
171 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
173 qib_dev_err(dd, "Failed read in resync\n");
176 if (ret != 0xF0 && ret != 0x55 && tries == 0)
177 qib_dev_err(dd, "unexpected pattern in resync\n");
178 pat = ret ^ 0xA5; /* alternate F0 and 55 */
179 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF);
181 qib_dev_err(dd, "Failed write in resync\n");
184 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
186 qib_dev_err(dd, "Failed re-read in resync\n");
190 qib_dev_err(dd, "Failed compare1 in resync\n");
193 loc = IB_CMUDONE(chn);
194 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
196 qib_dev_err(dd, "Failed CMUDONE rd in resync\n");
199 if ((ret & 0x70) != ((chn << 4) | 0x40)) {
200 qib_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n",
207 return (ret > 0) ? 0 : ret;
211 * Localize the stuff that should be done to change IB uC reset
212 * returns <0 for errors.
214 static int qib_ibsd_reset(struct qib_devdata *dd, int assert_rst)
220 rst_val = qib_read_kreg64(dd, kr_ibserdesctrl);
223 * Vendor recommends "interrupting" uC before reset, to
224 * minimize possible glitches.
226 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
227 epb_access(dd, IB_7220_SERDES, 1);
229 /* Squelch possible parity error from _asserting_ reset */
230 qib_write_kreg(dd, kr_hwerrmask,
231 dd->cspec->hwerrmask &
232 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
233 qib_write_kreg(dd, kr_ibserdesctrl, rst_val);
234 /* flush write, delay to ensure it took effect */
235 qib_read_kreg32(dd, kr_scratch);
237 /* once it's reset, can remove interrupt */
238 epb_access(dd, IB_7220_SERDES, -1);
239 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
242 * Before we de-assert reset, we need to deal with
243 * possible glitch on the Parity-error line.
244 * Suppress it around the reset, both in chip-level
245 * hwerrmask and in IB uC control reg. uC will allow
246 * it again during startup.
250 qib_write_kreg(dd, kr_hwerrmask,
251 dd->cspec->hwerrmask &
252 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
254 ret = qib_resync_ibepb(dd);
256 qib_dev_err(dd, "unable to re-sync IB EPB\n");
258 /* set uC control regs to suppress parity errs */
259 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1);
262 /* IB uC code past Version 1.32.17 allow suppression of wdog */
263 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80,
266 qib_dev_err(dd, "Failed to set WDOG disable\n");
269 qib_write_kreg(dd, kr_ibserdesctrl, rst_val);
270 /* flush write, delay for startup */
271 qib_read_kreg32(dd, kr_scratch);
273 /* clear, then re-enable parity errs */
274 qib_sd7220_clr_ibpar(dd);
275 val = qib_read_kreg64(dd, kr_hwerrstatus);
276 if (val & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR) {
277 qib_dev_err(dd, "IBUC Parity still set after RST\n");
278 dd->cspec->hwerrmask &=
279 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
281 qib_write_kreg(dd, kr_hwerrmask,
282 dd->cspec->hwerrmask);
289 static void qib_sd_trimdone_monitor(struct qib_devdata *dd,
292 int ret, chn, baduns;
298 /* give time for reset to settle out in EPB */
301 ret = qib_resync_ibepb(dd);
303 qib_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where);
305 /* Do "sacrificial read" to get EPB in sane state after reset */
306 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0);
308 qib_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where);
310 /* Check/show "summary" Trim-done bit in IBCStatus */
311 val = qib_read_kreg64(dd, kr_ibcstatus);
312 if (!(val & (1ULL << 11)))
313 qib_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where);
315 * Do "dummy read/mod/wr" to get EPB in sane state after reset
316 * The default value for MPREG6 is 0.
320 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80);
322 qib_dev_err(dd, "Failed Dummy RMW, (%s)\n", where);
327 for (chn = 3; chn >= 0; --chn) {
328 /* Read CTRL reg for each channel to check TRIMDONE */
329 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
330 IB_CTRL2(chn), 0, 0);
332 qib_dev_err(dd, "Failed checking TRIMDONE, chn %d"
333 " (%s)\n", chn, where);
338 baduns |= (1 << chn);
339 qib_dev_err(dd, "TRIMDONE cleared on chn %d (%02X)."
340 " (%s)\n", chn, ret, where);
341 probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
343 qib_dev_err(dd, "probe is %d (%02X)\n",
345 probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
346 IB_CTRL2(chn), 0, 0);
347 qib_dev_err(dd, "re-read: %d (%02X)\n",
349 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
350 IB_CTRL2(chn), 0x10, 0x10);
353 "Err on TRIMDONE rewrite1\n");
356 for (chn = 3; chn >= 0; --chn) {
357 /* Read CTRL reg for each channel to check TRIMDONE */
358 if (baduns & (1 << chn)) {
360 "Reseting TRIMDONE on chn %d (%s)\n",
362 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
363 IB_CTRL2(chn), 0x10, 0x10);
365 qib_dev_err(dd, "Failed re-setting "
366 "TRIMDONE, chn %d (%s)\n",
373 * Below is portion of IBA7220-specific bringup_serdes() that actually
374 * deals with registers and memory within the SerDes itself.
375 * Post IB uC code version 1.32.17, was_reset being 1 is not really
376 * informative, so we double-check.
378 int qib_sd7220_init(struct qib_devdata *dd)
380 int ret = 1; /* default to failure */
381 int first_reset, was_reset;
383 /* SERDES MPU reset recorded in D0 */
384 was_reset = (qib_read_kreg64(dd, kr_ibserdesctrl) & 1);
386 /* entered with reset not asserted, we need to do it */
387 qib_ibsd_reset(dd, 1);
388 qib_sd_trimdone_monitor(dd, "Driver-reload");
390 /* Substitute our deduced value for was_reset */
391 ret = qib_ibsd_ucode_loaded(dd->pport);
395 first_reset = !ret; /* First reset if IBSD uCode not yet loaded */
397 * Alter some regs per vendor latest doc, reset-defaults
398 * are not right for IB.
400 ret = qib_sd_early(dd);
402 qib_dev_err(dd, "Failed to set IB SERDES early defaults\n");
406 * Set DAC manual trim IB.
407 * We only do this once after chip has been reset (usually
408 * same as once per system boot).
411 ret = qib_sd_dactrim(dd);
413 qib_dev_err(dd, "Failed IB SERDES DAC trim\n");
418 * Set various registers (DDS and RXEQ) that will be
419 * controlled by IBC (in 1.2 mode) to reasonable preset values
420 * Calling the "internal" version avoids the "check for needed"
421 * and "trimdone monitor" that might be counter-productive.
423 ret = qib_internal_presets(dd);
425 qib_dev_err(dd, "Failed to set IB SERDES presets\n");
428 ret = qib_sd_trimself(dd, 0x80);
430 qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n");
434 /* Load image, then try to verify */
435 ret = 0; /* Assume success */
440 ret = qib_sd7220_ib_load(dd);
442 qib_dev_err(dd, "Failed to load IB SERDES image\n");
445 /* Loaded image, try to verify */
446 vfy = qib_sd7220_ib_vfy(dd);
448 qib_dev_err(dd, "SERDES PRAM VFY failed\n");
450 } /* end if verified */
451 } /* end if loaded */
454 * Loaded and verified. Almost good...
455 * hold "success" in ret
459 * Prev steps all worked, continue bringup
460 * De-assert RESET to uC, only in first reset, to allow
463 * Since our default setup sets START_EQ1 to
464 * PRESET, we need to clear that for this very first run.
466 ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38);
468 qib_dev_err(dd, "Failed clearing START_EQ1\n");
472 qib_ibsd_reset(dd, 0);
474 * If this is not the first reset, trimdone should be set
475 * already. We may need to check about this.
477 trim_done = qib_sd_trimdone_poll(dd);
479 * Whether or not trimdone succeeded, we need to put the
480 * uC back into reset to avoid a possible fight with the
483 qib_ibsd_reset(dd, 1);
486 qib_dev_err(dd, "No TRIMDONE seen\n");
490 * DEBUG: check each time we reset if trimdone bits have
491 * gotten cleared, and re-set them.
493 qib_sd_trimdone_monitor(dd, "First-reset");
494 /* Remember so we do not re-do the load, dactrim, etc. */
495 dd->cspec->serdes_first_init_done = 1;
498 * setup for channel training and load values for
499 * RxEq and DDS in tables used by IBC in IB1.2 mode
502 if (qib_sd_setvals(dd) >= 0)
507 /* start relock timer regardless, but start at 1 second */
508 set_7220_relock_poll(dd, -1);
512 #define EPB_ACC_REQ 1
513 #define EPB_ACC_GNT 0x100
514 #define EPB_DATA_MASK 0xFF
515 #define EPB_RD (1ULL << 24)
516 #define EPB_TRANS_RDY (1ULL << 31)
517 #define EPB_TRANS_ERR (1ULL << 30)
518 #define EPB_TRANS_TRIES 5
521 * query, claim, release ownership of the EPB (External Parallel Bus)
522 * for a specified SERDES.
523 * the "claim" parameter is >0 to claim, <0 to release, 0 to query.
524 * Returns <0 for errors, >0 if we had ownership, else 0.
526 static int epb_access(struct qib_devdata *dd, int sdnum, int claim)
536 * The IB SERDES "ownership" is fairly simple. A single each
539 acc = kr_ibsd_epb_access_ctrl;
544 /* PCIe SERDES has two "octants", need to select which */
545 acc = kr_pciesd_epb_access_ctrl;
546 oct_sel = (2 << (sdnum - PCIE_SERDES0));
553 /* Make sure any outstanding transaction was seen */
554 qib_read_kreg32(dd, kr_scratch);
557 accval = qib_read_kreg32(dd, acc);
559 owned = !!(accval & EPB_ACC_GNT);
561 /* Need to release */
564 * The only writeable bits are the request and CS.
565 * Both should be clear
568 qib_write_kreg(dd, acc, newval);
569 /* First read after write is not trustworthy */
570 pollval = qib_read_kreg32(dd, acc);
572 pollval = qib_read_kreg32(dd, acc);
573 if (pollval & EPB_ACC_GNT)
575 } else if (claim > 0) {
578 u64 newval = EPB_ACC_REQ | oct_sel;
579 qib_write_kreg(dd, acc, newval);
580 /* First read after write is not trustworthy */
581 pollval = qib_read_kreg32(dd, acc);
583 pollval = qib_read_kreg32(dd, acc);
584 if (!(pollval & EPB_ACC_GNT))
591 * Lemma to deal with race condition of write..read to epb regs
593 static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp)
598 qib_write_kreg(dd, reg, i_val);
599 /* Throw away first read, as RDY bit may be stale */
600 transval = qib_read_kreg64(dd, reg);
602 for (tries = EPB_TRANS_TRIES; tries; --tries) {
603 transval = qib_read_kreg32(dd, reg);
604 if (transval & EPB_TRANS_RDY)
608 if (transval & EPB_TRANS_ERR)
610 if (tries > 0 && o_vp)
616 * qib_sd7220_reg_mod - modify SERDES register
617 * @dd: the qlogic_ib device
618 * @sdnum: which SERDES to access
619 * @loc: location - channel, element, register, as packed by EPB_LOC() macro.
620 * @wd: Write Data - value to set in register
621 * @mask: ones where data should be spliced into reg.
623 * Basic register read/modify/write, with un-needed acesses elided. That is,
624 * a mask of zero will prevent write, while a mask of 0xFF will prevent read.
625 * returns current (presumed, if a write was done) contents of selected
626 * register, or <0 if errors.
628 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
639 trans = kr_ibsd_epb_transaction_reg;
644 trans = kr_pciesd_epb_transaction_reg;
652 * All access is locked in software (vs other host threads) and
653 * hardware (vs uC access).
655 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
657 owned = epb_access(dd, sdnum, 1);
659 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
663 for (tries = EPB_TRANS_TRIES; tries; --tries) {
664 transval = qib_read_kreg32(dd, trans);
665 if (transval & EPB_TRANS_RDY)
671 tries = 1; /* to make read-skip work */
674 * Not a pure write, so need to read.
675 * loc encodes chip-select as well as address
677 transval = loc | EPB_RD;
678 tries = epb_trans(dd, trans, transval, &transval);
680 if (tries > 0 && mask != 0) {
682 * Not a pure read, so need to write.
684 wd = (wd & mask) | (transval & ~mask);
685 transval = loc | (wd & EPB_DATA_MASK);
686 tries = epb_trans(dd, trans, transval, &transval);
689 /* else, failed to see ready, what error-handling? */
692 * Release bus. Failure is an error.
694 if (epb_access(dd, sdnum, -1) < 0)
697 ret = transval & EPB_DATA_MASK;
699 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
705 #define EPB_ROM_R (2)
706 #define EPB_ROM_W (1)
708 * Below, all uC-related, use appropriate UC_CS, depending
709 * on which SerDes is used.
711 #define EPB_UC_CTL EPB_LOC(6, 0, 0)
712 #define EPB_MADDRL EPB_LOC(6, 0, 2)
713 #define EPB_MADDRH EPB_LOC(6, 0, 3)
714 #define EPB_ROMDATA EPB_LOC(6, 0, 4)
715 #define EPB_RAMDATA EPB_LOC(6, 0, 5)
717 /* Transfer date to/from uC Program RAM of IB or PCIe SerDes */
718 static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc,
719 u8 *buf, int cnt, int rd_notwr)
732 /* Pick appropriate transaction reg and "Chip select" for this serdes */
735 csbit = 1ULL << EPB_IB_UC_CS_SHF;
736 trans = kr_ibsd_epb_transaction_reg;
741 /* PCIe SERDES has uC "chip select" in different bit, too */
742 csbit = 1ULL << EPB_PCIE_UC_CS_SHF;
743 trans = kr_pciesd_epb_transaction_reg;
750 op = rd_notwr ? "Rd" : "Wr";
751 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
753 owned = epb_access(dd, sdnum, 1);
755 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
760 * In future code, we may need to distinguish several address ranges,
761 * and select various memories based on this. For now, just trim
762 * "loc" (location including address and memory select) to
763 * "addr" (address within memory). we will only support PRAM
767 for (tries = EPB_TRANS_TRIES; tries; --tries) {
768 transval = qib_read_kreg32(dd, trans);
769 if (transval & EPB_TRANS_RDY)
777 * Every "memory" access is doubly-indirect.
778 * We set two bytes of address, then read/write
779 * one or mores bytes of data.
782 /* First, we set control to "Read" or "Write" */
783 transval = csbit | EPB_UC_CTL |
784 (rd_notwr ? EPB_ROM_R : EPB_ROM_W);
785 tries = epb_trans(dd, trans, transval, &transval);
786 while (tries > 0 && sofar < cnt) {
788 /* Only set address at start of chunk */
789 int addrbyte = (addr + sofar) >> 8;
790 transval = csbit | EPB_MADDRH | addrbyte;
791 tries = epb_trans(dd, trans, transval,
795 addrbyte = (addr + sofar) & 0xFF;
796 transval = csbit | EPB_MADDRL | addrbyte;
797 tries = epb_trans(dd, trans, transval,
804 transval = csbit | EPB_ROMDATA | EPB_RD;
806 transval = csbit | EPB_ROMDATA | buf[sofar];
807 tries = epb_trans(dd, trans, transval, &transval);
811 buf[sofar] = transval & EPB_DATA_MASK;
814 /* Finally, clear control-bit for Read or Write */
815 transval = csbit | EPB_UC_CTL;
816 tries = epb_trans(dd, trans, transval, &transval);
820 /* Release bus. Failure is an error */
821 if (epb_access(dd, sdnum, -1) < 0)
824 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
830 #define PROG_CHUNK 64
832 int qib_sd7220_prog_ld(struct qib_devdata *dd, int sdnum,
833 u8 *img, int len, int offset)
838 while (sofar < len) {
840 if (req > PROG_CHUNK)
842 cnt = qib_sd7220_ram_xfer(dd, sdnum, offset + sofar,
843 img + sofar, req, 0);
854 #define SD_PRAM_ERROR_LIMIT 42
856 int qib_sd7220_prog_vfy(struct qib_devdata *dd, int sdnum,
857 const u8 *img, int len, int offset)
859 int cnt, sofar, req, idx, errors;
860 unsigned char readback[VFY_CHUNK];
864 while (sofar < len) {
868 cnt = qib_sd7220_ram_xfer(dd, sdnum, sofar + offset,
871 /* failed in read itself */
875 for (idx = 0; idx < cnt; ++idx) {
876 if (readback[idx] != img[idx+sofar])
881 return errors ? -errors : sofar;
885 * IRQ not set up at this point in init, so we poll.
887 #define IB_SERDES_TRIM_DONE (1ULL << 11)
888 #define TRIM_TMO (30)
890 static int qib_sd_trimdone_poll(struct qib_devdata *dd)
896 * Default to failure, so IBC will not start
897 * without IB_SERDES_TRIM_DONE.
900 for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) {
901 val = qib_read_kreg64(dd, kr_ibcstatus);
902 if (val & IB_SERDES_TRIM_DONE) {
908 if (trim_tmo >= TRIM_TMO) {
909 qib_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo);
915 #define TX_FAST_ELT (9)
918 * Set the "negotiation" values for SERDES. These are used by the IB1.2
919 * link negotiation. Macros below are attempt to keep the values a
920 * little more human-editable.
921 * First, values related to Drive De-emphasis Settings.
924 #define NUM_DDS_REGS 6
925 #define DDS_REG_MAP 0x76A910 /* LSB-first list of regs (in elt 9) to mod */
927 #define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \
928 { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \
929 (main_d << 3) | 4 | (ipre_d >> 2), \
930 (main_s << 3) | 4 | (ipre_s >> 2), \
931 ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \
932 ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } }
934 static struct dds_init {
935 uint8_t reg_vals[NUM_DDS_REGS];
936 } dds_init_vals[] = {
937 /* DDR(FDR) SDR(HDR) */
938 /* Vendor recommends below for 3m cable */
940 DDS_VAL(31, 19, 12, 0, 29, 22, 9, 0),
941 DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1),
942 DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0),
943 DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0),
944 DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0),
945 DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0),
946 DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0),
947 DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0),
948 DDS_VAL(31, 20, 11, 0, 28, 23, 8, 0),
949 DDS_VAL(31, 21, 10, 0, 27, 24, 7, 0),
950 DDS_VAL(31, 22, 9, 0, 26, 25, 6, 0),
951 DDS_VAL(30, 23, 8, 0, 25, 26, 5, 0),
952 DDS_VAL(29, 24, 7, 0, 23, 27, 4, 0),
953 /* Vendor recommends below for 1m cable */
955 DDS_VAL(28, 25, 6, 0, 21, 28, 3, 0),
956 DDS_VAL(27, 26, 5, 0, 19, 29, 2, 0),
957 DDS_VAL(25, 27, 4, 0, 17, 30, 1, 0)
961 * Now the RXEQ section of the table.
963 /* Hardware packs an element number and register address thus: */
964 #define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4))
965 #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \
966 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
968 #define RXEQ_VAL_ALL(elt, adr, val) \
969 {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} }
971 #define RXEQ_SDR_DFELTH 0
972 #define RXEQ_SDR_TLTH 0
973 #define RXEQ_SDR_G1CNT_Z1CNT 0x11
974 #define RXEQ_SDR_ZCNT 23
976 static struct rxeq_init {
977 u16 rdesc; /* in form used in SerDesDDSRXEQ */
979 } rxeq_init_vals[] = {
980 /* Set Rcv Eq. to Preset node */
981 RXEQ_VAL_ALL(7, 0x27, 0x10),
982 /* Set DFELTHFDR/HDR thresholds */
983 RXEQ_VAL(7, 8, 0, 0, 0, 0), /* FDR, was 0, 1, 2, 3 */
984 RXEQ_VAL(7, 0x21, 0, 0, 0, 0), /* HDR */
985 /* Set TLTHFDR/HDR theshold */
986 RXEQ_VAL(7, 9, 2, 2, 2, 2), /* FDR, was 0, 2, 4, 6 */
987 RXEQ_VAL(7, 0x23, 2, 2, 2, 2), /* HDR, was 0, 1, 2, 3 */
988 /* Set Preamp setting 2 (ZFR/ZCNT) */
989 RXEQ_VAL(7, 0x1B, 12, 12, 12, 12), /* FDR, was 12, 16, 20, 24 */
990 RXEQ_VAL(7, 0x1C, 12, 12, 12, 12), /* HDR, was 12, 16, 20, 24 */
991 /* Set Preamp DC gain and Setting 1 (GFR/GHR) */
992 RXEQ_VAL(7, 0x1E, 16, 16, 16, 16), /* FDR, was 16, 17, 18, 20 */
993 RXEQ_VAL(7, 0x1F, 16, 16, 16, 16), /* HDR, was 16, 17, 18, 20 */
994 /* Toggle RELOCK (in VCDL_CTRL0) to lock to data */
995 RXEQ_VAL_ALL(6, 6, 0x20), /* Set D5 High */
996 RXEQ_VAL_ALL(6, 6, 0), /* Set D5 Low */
999 /* There are 17 values from vendor, but IBC only accesses the first 16 */
1000 #define DDS_ROWS (16)
1001 #define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals)
1003 static int qib_sd_setvals(struct qib_devdata *dd)
1006 int min_idx; /* Minimum index for this portion of table */
1007 uint32_t dds_reg_map;
1008 u64 __iomem *taddr, *iaddr;
1012 taddr = dd->kregbase + kr_serdes_maptable;
1013 iaddr = dd->kregbase + kr_serdes_ddsrxeq0;
1016 * Init the DDS section of the table.
1017 * Each "row" of the table provokes NUM_DDS_REG writes, to the
1018 * registers indicated in DDS_REG_MAP.
1020 sdctl = qib_read_kreg64(dd, kr_ibserdesctrl);
1021 sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8);
1022 sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13);
1023 qib_write_kreg(dd, kr_ibserdesctrl, sdctl);
1026 * Iterate down table within loop for each register to store.
1028 dds_reg_map = DDS_REG_MAP;
1029 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1030 data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT;
1031 writeq(data, iaddr + idx);
1033 qib_read_kreg32(dd, kr_scratch);
1035 for (midx = 0; midx < DDS_ROWS; ++midx) {
1036 u64 __iomem *daddr = taddr + ((midx << 4) + idx);
1037 data = dds_init_vals[midx].reg_vals[idx];
1038 writeq(data, daddr);
1040 qib_read_kreg32(dd, kr_scratch);
1041 } /* End inner for (vals for this reg, each row) */
1042 } /* end outer for (regs to be stored) */
1045 * Init the RXEQ section of the table.
1046 * This runs in a different order, as the pattern of
1047 * register references is more complex, but there are only
1048 * four "data" values per register.
1050 min_idx = idx; /* RXEQ indices pick up where DDS left off */
1051 taddr += 0x100; /* RXEQ data is in second half of table */
1052 /* Iterate through RXEQ register addresses */
1053 for (idx = 0; idx < RXEQ_ROWS; ++idx) {
1054 int didx; /* "destination" */
1057 /* didx is offset by min_idx to address RXEQ range of regs */
1058 didx = idx + min_idx;
1059 /* Store the next RXEQ register address */
1060 writeq(rxeq_init_vals[idx].rdesc, iaddr + didx);
1062 qib_read_kreg32(dd, kr_scratch);
1063 /* Iterate through RXEQ values */
1064 for (vidx = 0; vidx < 4; vidx++) {
1065 data = rxeq_init_vals[idx].rdata[vidx];
1066 writeq(data, taddr + (vidx << 6) + idx);
1068 qib_read_kreg32(dd, kr_scratch);
1070 } /* end outer for (Reg-writes for RXEQ) */
1074 #define CMUCTRL5 EPB_LOC(7, 0, 0x15)
1075 #define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0)
1076 #define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5)
1077 #define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6)
1078 #define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8)
1079 #define START_EQ2(chan) EPB_LOC(chan, 7, 0x28)
1082 * Repeat a "store" across all channels of the IB SerDes.
1083 * Although nominally it inherits the "read value" of the last
1084 * channel it modified, the only really useful return is <0 for
1085 * failure, >= 0 for success. The parameter 'loc' is assumed to
1086 * be the location in some channel of the register to be modified
1087 * The caller can specify use of the "gang write" option of EPB,
1088 * in which case we use the specified channel data for any fields
1089 * not explicitely written.
1091 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
1097 if (loc & EPB_GLOBAL_WR) {
1099 * Our caller has assured us that we can set all four
1100 * channels at once. Trust that. If mask is not 0xFF,
1101 * we will read the _specified_ channel for our starting
1104 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1105 chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7;
1107 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
1108 loc & ~EPB_GLOBAL_WR, 0, 0);
1110 int sloc = loc >> EPB_ADDR_SHF;
1112 qib_dev_err(dd, "pre-read failed: elt %d,"
1113 " addr 0x%X, chnl %d\n",
1115 (sloc >> 9) & 0x3f, chnl);
1118 val = (ret & ~mask) | (val & mask);
1120 loc &= ~(7 << (4+EPB_ADDR_SHF));
1121 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1123 int sloc = loc >> EPB_ADDR_SHF;
1125 qib_dev_err(dd, "Global WR failed: elt %d,"
1126 " addr 0x%X, val %02X\n",
1127 (sloc & 0xF), (sloc >> 9) & 0x3f, val);
1131 /* Clear "channel" and set CS so we can simply iterate */
1132 loc &= ~(7 << (4+EPB_ADDR_SHF));
1133 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1134 for (chnl = 0; chnl < 4; ++chnl) {
1135 int cloc = loc | (chnl << (4+EPB_ADDR_SHF));
1137 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask);
1139 int sloc = loc >> EPB_ADDR_SHF;
1141 qib_dev_err(dd, "Write failed: elt %d,"
1142 " addr 0x%X, chnl %d, val 0x%02X,"
1144 (sloc & 0xF), (sloc >> 9) & 0x3f, chnl,
1145 val & 0xFF, mask & 0xFF);
1153 * Set the Tx values normally modified by IBC in IB1.2 mode to default
1154 * values, as gotten from first row of init table.
1156 static int set_dds_vals(struct qib_devdata *dd, struct dds_init *ddi)
1162 regmap = DDS_REG_MAP;
1163 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1164 reg = (regmap & 0xF);
1166 data = ddi->reg_vals[idx];
1167 /* Vendor says RMW not needed for these regs, use 0xFF mask */
1168 ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF);
1176 * Set the Rx values normally modified by IBC in IB1.2 mode to default
1177 * values, as gotten from selected column of init table.
1179 static int set_rxeq_vals(struct qib_devdata *dd, int vsel)
1183 int cnt = ARRAY_SIZE(rxeq_init_vals);
1185 for (ridx = 0; ridx < cnt; ++ridx) {
1186 int elt, reg, val, loc;
1188 elt = rxeq_init_vals[ridx].rdesc & 0xF;
1189 reg = rxeq_init_vals[ridx].rdesc >> 4;
1190 loc = EPB_LOC(0, elt, reg);
1191 val = rxeq_init_vals[ridx].rdata[vsel];
1192 /* mask of 0xFF, because hardware does full-byte store. */
1193 ret = ibsd_mod_allchnls(dd, loc, val, 0xFF);
1201 * Set the default values (row 0) for DDR Driver Demphasis.
1202 * we do this initially and whenever we turn off IB-1.2
1204 * The "default" values for Rx equalization are also stored to
1205 * SerDes registers. Formerly (and still default), we used set 2.
1206 * For experimenting with cables and link-partners, we allow changing
1207 * that via a module parameter.
1209 static unsigned qib_rxeq_set = 2;
1210 module_param_named(rxeq_default_set, qib_rxeq_set, uint,
1212 MODULE_PARM_DESC(rxeq_default_set,
1213 "Which set [0..3] of Rx Equalization values is default");
1215 static int qib_internal_presets(struct qib_devdata *dd)
1219 ret = set_dds_vals(dd, dds_init_vals + DDS_3M);
1222 qib_dev_err(dd, "Failed to set default DDS values\n");
1223 ret = set_rxeq_vals(dd, qib_rxeq_set & 3);
1225 qib_dev_err(dd, "Failed to set default RXEQ values\n");
1229 int qib_sd7220_presets(struct qib_devdata *dd)
1233 if (!dd->cspec->presets_needed)
1235 dd->cspec->presets_needed = 0;
1236 /* Assert uC reset, so we don't clash with it. */
1237 qib_ibsd_reset(dd, 1);
1239 qib_sd_trimdone_monitor(dd, "link-down");
1241 ret = qib_internal_presets(dd);
1245 static int qib_sd_trimself(struct qib_devdata *dd, int val)
1247 int loc = CMUCTRL5 | (1U << EPB_IB_QUAD0_CS_SHF);
1249 return qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1252 static int qib_sd_early(struct qib_devdata *dd)
1256 ret = ibsd_mod_allchnls(dd, RXHSCTRL0(0) | EPB_GLOBAL_WR, 0xD4, 0xFF);
1259 ret = ibsd_mod_allchnls(dd, START_EQ1(0) | EPB_GLOBAL_WR, 0x10, 0xFF);
1262 ret = ibsd_mod_allchnls(dd, START_EQ2(0) | EPB_GLOBAL_WR, 0x30, 0xFF);
1267 #define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E)
1268 #define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6)
1269 #define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF)
1271 static int qib_sd_dactrim(struct qib_devdata *dd)
1275 ret = ibsd_mod_allchnls(dd, VCDL_DAC2(0) | EPB_GLOBAL_WR, 0x2D, 0xFF);
1279 /* more fine-tuning of what will be default */
1280 ret = ibsd_mod_allchnls(dd, VCDL_CTRL2(0), 3, 0xF);
1284 ret = ibsd_mod_allchnls(dd, BACTRL(0) | EPB_GLOBAL_WR, 0x40, 0xFF);
1288 ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x04, 0xFF);
1292 ret = ibsd_mod_allchnls(dd, RXHSSTATUS(0) | EPB_GLOBAL_WR, 0x04, 0xFF);
1297 * Delay for max possible number of steps, with slop.
1298 * Each step is about 4usec.
1302 ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x00, 0xFF);
1308 #define RELOCK_FIRST_MS 3
1309 #define RXLSPPM(chan) EPB_LOC(chan, 0, 2)
1310 void toggle_7220_rclkrls(struct qib_devdata *dd)
1312 int loc = RXLSPPM(0) | EPB_GLOBAL_WR;
1315 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1317 qib_dev_err(dd, "RCLKRLS failed to clear D7\n");
1320 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1322 /* And again for good measure */
1324 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1326 qib_dev_err(dd, "RCLKRLS failed to clear D7\n");
1329 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1331 /* Now reset xgxs and IBC to complete the recovery */
1332 dd->f_xgxs_reset(dd->pport);
1336 * Shut down the timer that polls for relock occasions, if needed
1337 * this is "hooked" from qib_7220_quiet_serdes(), which is called
1338 * just before qib_shutdown_device() in qib_driver.c shuts down all
1341 void shutdown_7220_relock_poll(struct qib_devdata *dd)
1343 if (dd->cspec->relock_timer_active)
1344 del_timer_sync(&dd->cspec->relock_timer);
1347 static unsigned qib_relock_by_timer = 1;
1348 module_param_named(relock_by_timer, qib_relock_by_timer, uint,
1350 MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up");
1352 static void qib_run_relock(unsigned long opaque)
1354 struct qib_devdata *dd = (struct qib_devdata *)opaque;
1355 struct qib_pportdata *ppd = dd->pport;
1356 struct qib_chip_specific *cs = dd->cspec;
1360 * Check link-training state for "stuck" state, when down.
1361 * if found, try relock and schedule another try at
1362 * exponentially growing delay, maxed at one second.
1363 * if not stuck, our work is done.
1365 if ((dd->flags & QIB_INITTED) && !(ppd->lflags &
1366 (QIBL_IB_AUTONEG_INPROG | QIBL_LINKINIT | QIBL_LINKARMED |
1367 QIBL_LINKACTIVE))) {
1368 if (qib_relock_by_timer) {
1369 if (!(ppd->lflags & QIBL_IB_LINK_DISABLED))
1370 toggle_7220_rclkrls(dd);
1372 /* re-set timer for next check */
1373 timeoff = cs->relock_interval << 1;
1376 cs->relock_interval = timeoff;
1379 mod_timer(&cs->relock_timer, jiffies + timeoff);
1382 void set_7220_relock_poll(struct qib_devdata *dd, int ibup)
1384 struct qib_chip_specific *cs = dd->cspec;
1387 /* We are now up, relax timer to 1 second interval */
1388 if (cs->relock_timer_active) {
1389 cs->relock_interval = HZ;
1390 mod_timer(&cs->relock_timer, jiffies + HZ);
1393 /* Transition to down, (re-)set timer to short interval. */
1394 unsigned int timeout;
1396 timeout = msecs_to_jiffies(RELOCK_FIRST_MS);
1399 /* If timer has not yet been started, do so. */
1400 if (!cs->relock_timer_active) {
1401 cs->relock_timer_active = 1;
1402 init_timer(&cs->relock_timer);
1403 cs->relock_timer.function = qib_run_relock;
1404 cs->relock_timer.data = (unsigned long) dd;
1405 cs->relock_interval = timeout;
1406 cs->relock_timer.expires = jiffies + timeout;
1407 add_timer(&cs->relock_timer);
1409 cs->relock_interval = timeout;
1410 mod_timer(&cs->relock_timer, jiffies + timeout);