2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/module.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/slab.h>
33 #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
35 /* KBC row scan time and delay for beginning the row scan. */
36 #define KBC_ROW_SCAN_TIME 16
37 #define KBC_ROW_SCAN_DLY 5
39 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
40 #define KBC_CYCLE_USEC 32
44 /* KBC Control Register */
45 #define KBC_CONTROL_0 0x0
46 #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
47 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
48 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
49 #define KBC_CONTROL_KBC_EN (1 << 0)
51 /* KBC Interrupt Register */
53 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
55 #define KBC_ROW_CFG0_0 0x8
56 #define KBC_COL_CFG0_0 0x18
57 #define KBC_INIT_DLY_0 0x28
58 #define KBC_RPT_DLY_0 0x2c
59 #define KBC_KP_ENT0_0 0x30
60 #define KBC_KP_ENT1_0 0x34
61 #define KBC_ROW0_MASK_0 0x38
63 #define KBC_ROW_SHIFT 3
67 struct input_dev *idev;
69 unsigned int wake_enable_rows;
70 unsigned int wake_enable_cols;
72 unsigned int repoll_dly;
73 unsigned long cp_dly_jiffies;
75 const struct tegra_kbc_platform_data *pdata;
76 unsigned short keycode[KBC_MAX_KEY * 2];
77 unsigned short current_keys[KBC_MAX_KPENT];
78 unsigned int num_pressed_keys;
79 struct timer_list timer;
83 static const u32 tegra_kbc_default_keymap[] = {
90 KEY(1, 7, KEY_LEFTMETA),
92 KEY(2, 6, KEY_RIGHTALT),
93 KEY(2, 7, KEY_LEFTALT),
110 KEY(4, 7, KEY_SPACE),
119 KEY(5, 7, KEY_BACKSLASH),
121 KEY(6, 0, KEY_MINUS),
127 KEY(6, 6, KEY_COMMA),
130 KEY(7, 1, KEY_EQUAL),
131 KEY(7, 2, KEY_RIGHTBRACE),
132 KEY(7, 3, KEY_ENTER),
135 KEY(8, 4, KEY_RIGHTSHIFT),
136 KEY(8, 5, KEY_LEFTSHIFT),
138 KEY(9, 5, KEY_RIGHTCTRL),
139 KEY(9, 7, KEY_LEFTCTRL),
141 KEY(11, 0, KEY_LEFTBRACE),
143 KEY(11, 2, KEY_APOSTROPHE),
144 KEY(11, 3, KEY_SEMICOLON),
145 KEY(11, 4, KEY_SLASH),
150 KEY(12, 2, KEY_BACKSPACE),
154 KEY(12, 6, KEY_PRINT),
155 KEY(12, 7, KEY_PAUSE),
157 KEY(13, 0, KEY_INSERT),
158 KEY(13, 1, KEY_DELETE),
159 KEY(13, 3, KEY_PAGEUP),
160 KEY(13, 4, KEY_PAGEDOWN),
161 KEY(13, 5, KEY_RIGHT),
162 KEY(13, 6, KEY_DOWN),
163 KEY(13, 7, KEY_LEFT),
175 KEY(15, 1, KEY_GRAVE),
180 KEY(15, 6, KEY_CAPSLOCK),
183 /* Software Handled Function Keys */
191 KEY(22, 1, KEY_KPSLASH),
198 KEY(27, 1, KEY_KPASTERISK),
199 KEY(27, 3, KEY_KPMINUS),
200 KEY(27, 4, KEY_KPPLUS),
201 KEY(27, 5, KEY_KPDOT),
203 KEY(28, 5, KEY_VOLUMEUP),
205 KEY(29, 3, KEY_HOME),
207 KEY(29, 5, KEY_BRIGHTNESSDOWN),
208 KEY(29, 6, KEY_VOLUMEDOWN),
209 KEY(29, 7, KEY_BRIGHTNESSUP),
211 KEY(30, 0, KEY_NUMLOCK),
212 KEY(30, 1, KEY_SCROLLLOCK),
213 KEY(30, 2, KEY_MUTE),
215 KEY(31, 4, KEY_HELP),
218 static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
219 .keymap = tegra_kbc_default_keymap,
220 .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
223 static void tegra_kbc_report_released_keys(struct input_dev *input,
224 unsigned short old_keycodes[],
225 unsigned int old_num_keys,
226 unsigned short new_keycodes[],
227 unsigned int new_num_keys)
231 for (i = 0; i < old_num_keys; i++) {
232 for (j = 0; j < new_num_keys; j++)
233 if (old_keycodes[i] == new_keycodes[j])
236 if (j == new_num_keys)
237 input_report_key(input, old_keycodes[i], 0);
241 static void tegra_kbc_report_pressed_keys(struct input_dev *input,
242 unsigned char scancodes[],
243 unsigned short keycodes[],
244 unsigned int num_pressed_keys)
248 for (i = 0; i < num_pressed_keys; i++) {
249 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
250 input_report_key(input, keycodes[i], 1);
254 static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
256 unsigned char scancodes[KBC_MAX_KPENT];
257 unsigned short keycodes[KBC_MAX_KPENT];
260 unsigned int num_down = 0;
262 bool fn_keypress = false;
264 spin_lock_irqsave(&kbc->lock, flags);
265 for (i = 0; i < KBC_MAX_KPENT; i++) {
267 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
270 unsigned int col = val & 0x07;
271 unsigned int row = (val >> 3) & 0x0f;
272 unsigned char scancode =
273 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
275 scancodes[num_down] = scancode;
276 keycodes[num_down] = kbc->keycode[scancode];
277 /* If driver uses Fn map, do not report the Fn key. */
278 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
288 * If the platform uses Fn keymaps, translate keys on a Fn keypress.
289 * Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
292 for (i = 0; i < num_down; i++) {
293 scancodes[i] += KBC_MAX_KEY;
294 keycodes[i] = kbc->keycode[scancodes[i]];
298 spin_unlock_irqrestore(&kbc->lock, flags);
300 tegra_kbc_report_released_keys(kbc->idev,
301 kbc->current_keys, kbc->num_pressed_keys,
303 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
304 input_sync(kbc->idev);
306 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
307 kbc->num_pressed_keys = num_down;
310 static void tegra_kbc_keypress_timer(unsigned long data)
312 struct tegra_kbc *kbc = (struct tegra_kbc *)data;
317 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
321 tegra_kbc_report_keys(kbc);
324 * If more than one keys are pressed we need not wait
325 * for the repoll delay.
327 dly = (val == 1) ? kbc->repoll_dly : 1;
328 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
330 /* Release any pressed keys and exit the polling loop */
331 for (i = 0; i < kbc->num_pressed_keys; i++)
332 input_report_key(kbc->idev, kbc->current_keys[i], 0);
333 input_sync(kbc->idev);
335 kbc->num_pressed_keys = 0;
337 /* All keys are released so enable the keypress interrupt */
338 spin_lock_irqsave(&kbc->lock, flags);
339 val = readl(kbc->mmio + KBC_CONTROL_0);
340 val |= KBC_CONTROL_FIFO_CNT_INT_EN;
341 writel(val, kbc->mmio + KBC_CONTROL_0);
342 spin_unlock_irqrestore(&kbc->lock, flags);
346 static irqreturn_t tegra_kbc_isr(int irq, void *args)
348 struct tegra_kbc *kbc = args;
352 * Until all keys are released, defer further processing to
353 * the polling loop in tegra_kbc_keypress_timer
355 ctl = readl(kbc->mmio + KBC_CONTROL_0);
356 ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
357 writel(ctl, kbc->mmio + KBC_CONTROL_0);
360 * Quickly bail out & reenable interrupts if the fifo threshold
361 * count interrupt wasn't the interrupt source
363 val = readl(kbc->mmio + KBC_INT_0);
364 writel(val, kbc->mmio + KBC_INT_0);
366 if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
368 * Schedule timer to run when hardware is in continuous
371 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
373 ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
374 writel(ctl, kbc->mmio + KBC_CONTROL_0);
380 static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
382 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
384 unsigned int rst_val;
386 BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
387 rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;
389 for (i = 0; i < KBC_MAX_ROW; i++)
390 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
393 for (i = 0; i < pdata->wake_cnt; i++) {
395 addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
396 val = readl(kbc->mmio + addr);
397 val &= ~(1 << pdata->wake_cfg[i].col);
398 writel(val, kbc->mmio + addr);
403 static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
405 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
408 for (i = 0; i < KBC_MAX_GPIO; i++) {
409 u32 r_shft = 5 * (i % 6);
410 u32 c_shft = 4 * (i % 8);
411 u32 r_mask = 0x1f << r_shft;
412 u32 c_mask = 0x0f << c_shft;
413 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
414 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
415 u32 row_cfg = readl(kbc->mmio + r_offs);
416 u32 col_cfg = readl(kbc->mmio + c_offs);
421 if (pdata->pin_cfg[i].is_row)
422 row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
424 col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
426 writel(row_cfg, kbc->mmio + r_offs);
427 writel(col_cfg, kbc->mmio + c_offs);
431 static int tegra_kbc_start(struct tegra_kbc *kbc)
433 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
435 unsigned int debounce_cnt;
438 clk_enable(kbc->clk);
440 /* Reset the KBC controller to clear all previous status.*/
441 tegra_periph_reset_assert(kbc->clk);
443 tegra_periph_reset_deassert(kbc->clk);
446 tegra_kbc_config_pins(kbc);
447 tegra_kbc_setup_wakekeys(kbc, false);
449 writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
451 /* Keyboard debounce count is maximum of 12 bits. */
452 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
453 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
454 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
455 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
456 val |= KBC_CONTROL_KBC_EN; /* enable */
457 writel(val, kbc->mmio + KBC_CONTROL_0);
460 * Compute the delay(ns) from interrupt mode to continuous polling
461 * mode so the timer routine is scheduled appropriately.
463 val = readl(kbc->mmio + KBC_INIT_DLY_0);
464 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
466 kbc->num_pressed_keys = 0;
469 * Atomically clear out any remaining entries in the key FIFO
470 * and enable keyboard interrupts.
472 spin_lock_irqsave(&kbc->lock, flags);
474 val = readl(kbc->mmio + KBC_INT_0);
479 val = readl(kbc->mmio + KBC_KP_ENT0_0);
480 val = readl(kbc->mmio + KBC_KP_ENT1_0);
482 writel(0x7, kbc->mmio + KBC_INT_0);
483 spin_unlock_irqrestore(&kbc->lock, flags);
485 enable_irq(kbc->irq);
490 static void tegra_kbc_stop(struct tegra_kbc *kbc)
495 spin_lock_irqsave(&kbc->lock, flags);
496 val = readl(kbc->mmio + KBC_CONTROL_0);
498 writel(val, kbc->mmio + KBC_CONTROL_0);
499 spin_unlock_irqrestore(&kbc->lock, flags);
501 disable_irq(kbc->irq);
502 del_timer_sync(&kbc->timer);
504 clk_disable(kbc->clk);
507 static int tegra_kbc_open(struct input_dev *dev)
509 struct tegra_kbc *kbc = input_get_drvdata(dev);
511 return tegra_kbc_start(kbc);
514 static void tegra_kbc_close(struct input_dev *dev)
516 struct tegra_kbc *kbc = input_get_drvdata(dev);
518 return tegra_kbc_stop(kbc);
521 static bool __devinit
522 tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
523 struct device *dev, unsigned int *num_rows)
529 for (i = 0; i < KBC_MAX_GPIO; i++) {
530 const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
532 if (pin_cfg->is_row) {
533 if (pin_cfg->num >= KBC_MAX_ROW) {
535 "pin_cfg[%d]: invalid row number %d\n",
541 if (pin_cfg->num >= KBC_MAX_COL) {
543 "pin_cfg[%d]: invalid column number %d\n",
553 static int __devinit tegra_kbc_probe(struct platform_device *pdev)
555 const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
556 const struct matrix_keymap_data *keymap_data;
557 struct tegra_kbc *kbc;
558 struct input_dev *input_dev;
559 struct resource *res;
564 unsigned int debounce_cnt;
565 unsigned int scan_time_rows;
570 if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
573 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
575 dev_err(&pdev->dev, "failed to get I/O memory\n");
579 irq = platform_get_irq(pdev, 0);
581 dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
585 kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
586 input_dev = input_allocate_device();
587 if (!kbc || !input_dev) {
593 kbc->idev = input_dev;
595 spin_lock_init(&kbc->lock);
596 setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
598 res = request_mem_region(res->start, resource_size(res), pdev->name);
600 dev_err(&pdev->dev, "failed to request I/O memory\n");
605 kbc->mmio = ioremap(res->start, resource_size(res));
607 dev_err(&pdev->dev, "failed to remap I/O memory\n");
609 goto err_free_mem_region;
612 kbc->clk = clk_get(&pdev->dev, NULL);
613 if (IS_ERR(kbc->clk)) {
614 dev_err(&pdev->dev, "failed to get keyboard clock\n");
615 err = PTR_ERR(kbc->clk);
619 kbc->wake_enable_rows = 0;
620 kbc->wake_enable_cols = 0;
621 for (i = 0; i < pdata->wake_cnt; i++) {
622 kbc->wake_enable_rows |= (1 << pdata->wake_cfg[i].row);
623 kbc->wake_enable_cols |= (1 << pdata->wake_cfg[i].col);
627 * The time delay between two consecutive reads of the FIFO is
628 * the sum of the repeat time and the time taken for scanning
629 * the rows. There is an additional delay before the row scanning
630 * starts. The repoll delay is computed in milliseconds.
632 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
633 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
634 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
635 kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;
637 input_dev->name = pdev->name;
638 input_dev->id.bustype = BUS_HOST;
639 input_dev->dev.parent = &pdev->dev;
640 input_dev->open = tegra_kbc_open;
641 input_dev->close = tegra_kbc_close;
643 input_set_drvdata(input_dev, kbc);
645 input_dev->evbit[0] = BIT_MASK(EV_KEY);
646 input_set_capability(input_dev, EV_MSC, MSC_SCAN);
648 input_dev->keycode = kbc->keycode;
649 input_dev->keycodesize = sizeof(kbc->keycode[0]);
650 input_dev->keycodemax = KBC_MAX_KEY;
651 if (pdata->use_fn_map)
652 input_dev->keycodemax *= 2;
654 kbc->use_fn_map = pdata->use_fn_map;
655 keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
656 matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
657 input_dev->keycode, input_dev->keybit);
659 err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
662 dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
666 disable_irq(kbc->irq);
668 err = input_register_device(kbc->idev);
670 dev_err(&pdev->dev, "failed to register input device\n");
674 platform_set_drvdata(pdev, kbc);
675 device_init_wakeup(&pdev->dev, pdata->wakeup);
680 free_irq(kbc->irq, pdev);
686 release_mem_region(res->start, resource_size(res));
688 input_free_device(kbc->idev);
694 static int __devexit tegra_kbc_remove(struct platform_device *pdev)
696 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
697 struct resource *res;
699 free_irq(kbc->irq, pdev);
702 input_unregister_device(kbc->idev);
704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 release_mem_region(res->start, resource_size(res));
709 platform_set_drvdata(pdev, NULL);
714 #ifdef CONFIG_PM_SLEEP
715 static int tegra_kbc_suspend(struct device *dev)
717 struct platform_device *pdev = to_platform_device(dev);
718 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
720 if (device_may_wakeup(&pdev->dev)) {
721 tegra_kbc_setup_wakekeys(kbc, true);
722 enable_irq_wake(kbc->irq);
723 /* Forcefully clear the interrupt status */
724 writel(0x7, kbc->mmio + KBC_INT_0);
727 mutex_lock(&kbc->idev->mutex);
728 if (kbc->idev->users)
730 mutex_unlock(&kbc->idev->mutex);
736 static int tegra_kbc_resume(struct device *dev)
738 struct platform_device *pdev = to_platform_device(dev);
739 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
742 if (device_may_wakeup(&pdev->dev)) {
743 disable_irq_wake(kbc->irq);
744 tegra_kbc_setup_wakekeys(kbc, false);
746 mutex_lock(&kbc->idev->mutex);
747 if (kbc->idev->users)
748 err = tegra_kbc_start(kbc);
749 mutex_unlock(&kbc->idev->mutex);
756 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
758 static struct platform_driver tegra_kbc_driver = {
759 .probe = tegra_kbc_probe,
760 .remove = __devexit_p(tegra_kbc_remove),
763 .owner = THIS_MODULE,
764 .pm = &tegra_kbc_pm_ops,
768 static void __exit tegra_kbc_exit(void)
770 platform_driver_unregister(&tegra_kbc_driver);
772 module_exit(tegra_kbc_exit);
774 static int __init tegra_kbc_init(void)
776 return platform_driver_register(&tegra_kbc_driver);
778 module_init(tegra_kbc_init);
780 MODULE_LICENSE("GPL");
781 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
782 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
783 MODULE_ALIAS("platform:tegra-kbc");