2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/init.h>
19 #include <linux/serio.h>
20 #include <linux/err.h>
21 #include <linux/rcupdate.h>
22 #include <linux/platform_device.h>
23 #include <linux/i8042.h>
24 #include <linux/slab.h>
28 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
29 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
30 MODULE_LICENSE("GPL");
32 static bool i8042_nokbd;
33 module_param_named(nokbd, i8042_nokbd, bool, 0);
34 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
36 static bool i8042_noaux;
37 module_param_named(noaux, i8042_noaux, bool, 0);
38 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
40 static bool i8042_nomux;
41 module_param_named(nomux, i8042_nomux, bool, 0);
42 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
44 static bool i8042_unlock;
45 module_param_named(unlock, i8042_unlock, bool, 0);
46 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
48 static bool i8042_reset;
49 module_param_named(reset, i8042_reset, bool, 0);
50 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
52 static bool i8042_direct;
53 module_param_named(direct, i8042_direct, bool, 0);
54 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
56 static bool i8042_dumbkbd;
57 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
58 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
60 static bool i8042_noloop;
61 module_param_named(noloop, i8042_noloop, bool, 0);
62 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
64 static unsigned int i8042_blink_frequency = 500;
65 module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
66 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
69 static bool i8042_dritek;
70 module_param_named(dritek, i8042_dritek, bool, 0);
71 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
75 static bool i8042_nopnp;
76 module_param_named(nopnp, i8042_nopnp, bool, 0);
77 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
82 static bool i8042_debug;
83 module_param_named(debug, i8042_debug, bool, 0600);
84 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
87 static bool i8042_bypass_aux_irq_test;
92 * i8042_lock protects serialization between i8042_command and
93 * the interrupt handler.
95 static DEFINE_SPINLOCK(i8042_lock);
98 * Writers to AUX and KBD ports as well as users issuing i8042_command
99 * directly should acquire i8042_mutex (by means of calling
100 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
101 * they do not disturb each other (unfortunately in many i8042
102 * implementations write to one of the ports will immediately abort
103 * command that is being processed by another port).
105 static DEFINE_MUTEX(i8042_mutex);
114 #define I8042_KBD_PORT_NO 0
115 #define I8042_AUX_PORT_NO 1
116 #define I8042_MUX_PORT_NO 2
117 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
119 static struct i8042_port i8042_ports[I8042_NUM_PORTS];
121 static unsigned char i8042_initial_ctr;
122 static unsigned char i8042_ctr;
123 static bool i8042_mux_present;
124 static bool i8042_kbd_irq_registered;
125 static bool i8042_aux_irq_registered;
126 static unsigned char i8042_suppress_kbd_ack;
127 static struct platform_device *i8042_platform_device;
129 static irqreturn_t i8042_interrupt(int irq, void *dev_id);
130 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
131 struct serio *serio);
133 void i8042_lock_chip(void)
135 mutex_lock(&i8042_mutex);
137 EXPORT_SYMBOL(i8042_lock_chip);
139 void i8042_unlock_chip(void)
141 mutex_unlock(&i8042_mutex);
143 EXPORT_SYMBOL(i8042_unlock_chip);
145 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
146 struct serio *serio))
151 spin_lock_irqsave(&i8042_lock, flags);
153 if (i8042_platform_filter) {
158 i8042_platform_filter = filter;
161 spin_unlock_irqrestore(&i8042_lock, flags);
164 EXPORT_SYMBOL(i8042_install_filter);
166 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
172 spin_lock_irqsave(&i8042_lock, flags);
174 if (i8042_platform_filter != filter) {
179 i8042_platform_filter = NULL;
182 spin_unlock_irqrestore(&i8042_lock, flags);
185 EXPORT_SYMBOL(i8042_remove_filter);
188 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
189 * be ready for reading values from it / writing values to it.
190 * Called always with i8042_lock held.
193 static int i8042_wait_read(void)
197 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
201 return -(i == I8042_CTL_TIMEOUT);
204 static int i8042_wait_write(void)
208 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
212 return -(i == I8042_CTL_TIMEOUT);
216 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
217 * of the i8042 down the toilet.
220 static int i8042_flush(void)
223 unsigned char data, str;
226 spin_lock_irqsave(&i8042_lock, flags);
228 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
230 data = i8042_read_data();
232 dbg("%02x <- i8042 (flush, %s)", data,
233 str & I8042_STR_AUXDATA ? "aux" : "kbd");
236 spin_unlock_irqrestore(&i8042_lock, flags);
242 * i8042_command() executes a command on the i8042. It also sends the input
243 * parameter(s) of the commands to it, and receives the output value(s). The
244 * parameters are to be stored in the param array, and the output is placed
245 * into the same array. The number of the parameters and output values is
246 * encoded in bits 8-11 of the command number.
249 static int __i8042_command(unsigned char *param, int command)
253 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
256 error = i8042_wait_write();
260 dbg("%02x -> i8042 (command)", command & 0xff);
261 i8042_write_command(command & 0xff);
263 for (i = 0; i < ((command >> 12) & 0xf); i++) {
264 error = i8042_wait_write();
267 dbg("%02x -> i8042 (parameter)", param[i]);
268 i8042_write_data(param[i]);
271 for (i = 0; i < ((command >> 8) & 0xf); i++) {
272 error = i8042_wait_read();
274 dbg(" -- i8042 (timeout)");
278 if (command == I8042_CMD_AUX_LOOP &&
279 !(i8042_read_status() & I8042_STR_AUXDATA)) {
280 dbg(" -- i8042 (auxerr)");
284 param[i] = i8042_read_data();
285 dbg("%02x <- i8042 (return)", param[i]);
291 int i8042_command(unsigned char *param, int command)
296 spin_lock_irqsave(&i8042_lock, flags);
297 retval = __i8042_command(param, command);
298 spin_unlock_irqrestore(&i8042_lock, flags);
302 EXPORT_SYMBOL(i8042_command);
305 * i8042_kbd_write() sends a byte out through the keyboard interface.
308 static int i8042_kbd_write(struct serio *port, unsigned char c)
313 spin_lock_irqsave(&i8042_lock, flags);
315 if (!(retval = i8042_wait_write())) {
316 dbg("%02x -> i8042 (kbd-data)", c);
320 spin_unlock_irqrestore(&i8042_lock, flags);
326 * i8042_aux_write() sends a byte out through the aux interface.
329 static int i8042_aux_write(struct serio *serio, unsigned char c)
331 struct i8042_port *port = serio->port_data;
333 return i8042_command(&c, port->mux == -1 ?
335 I8042_CMD_MUX_SEND + port->mux);
340 * i8042_aux_close attempts to clear AUX or KBD port state by disabling
341 * and then re-enabling it.
344 static void i8042_port_close(struct serio *serio)
348 const char *port_name;
350 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
351 irq_bit = I8042_CTR_AUXINT;
352 disable_bit = I8042_CTR_AUXDIS;
355 irq_bit = I8042_CTR_KBDINT;
356 disable_bit = I8042_CTR_KBDDIS;
360 i8042_ctr &= ~irq_bit;
361 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
363 "i8042.c: Can't write CTR while closing %s port.\n",
368 i8042_ctr &= ~disable_bit;
369 i8042_ctr |= irq_bit;
370 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
371 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n",
375 * See if there is any data appeared while we were messing with
378 i8042_interrupt(0, NULL);
382 * i8042_start() is called by serio core when port is about to finish
383 * registering. It will mark port as existing so i8042_interrupt can
384 * start sending data through it.
386 static int i8042_start(struct serio *serio)
388 struct i8042_port *port = serio->port_data;
396 * i8042_stop() marks serio port as non-existing so i8042_interrupt
397 * will not try to send data to the port that is about to go away.
398 * The function is called by serio core as part of unregister procedure.
400 static void i8042_stop(struct serio *serio)
402 struct i8042_port *port = serio->port_data;
404 port->exists = false;
407 * We synchronize with both AUX and KBD IRQs because there is
408 * a (very unlikely) chance that AUX IRQ is raised for KBD port
411 synchronize_irq(I8042_AUX_IRQ);
412 synchronize_irq(I8042_KBD_IRQ);
417 * i8042_filter() filters out unwanted bytes from the input data stream.
418 * It is called from i8042_interrupt and thus is running with interrupts
419 * off and i8042_lock held.
421 static bool i8042_filter(unsigned char data, unsigned char str,
424 if (unlikely(i8042_suppress_kbd_ack)) {
425 if ((~str & I8042_STR_AUXDATA) &&
426 (data == 0xfa || data == 0xfe)) {
427 i8042_suppress_kbd_ack--;
428 dbg("Extra keyboard ACK - filtered out\n");
433 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
434 dbg("Filtered out by platform filter\n");
442 * i8042_interrupt() is the most important function in this driver -
443 * it handles the interrupts from the i8042, and sends incoming bytes
444 * to the upper layers.
447 static irqreturn_t i8042_interrupt(int irq, void *dev_id)
449 struct i8042_port *port;
452 unsigned char str, data;
454 unsigned int port_no;
458 spin_lock_irqsave(&i8042_lock, flags);
460 str = i8042_read_status();
461 if (unlikely(~str & I8042_STR_OBF)) {
462 spin_unlock_irqrestore(&i8042_lock, flags);
463 if (irq) dbg("Interrupt %d, without any data", irq);
468 data = i8042_read_data();
470 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
471 static unsigned long last_transmit;
472 static unsigned char last_str;
475 if (str & I8042_STR_MUXERR) {
476 dbg("MUX error, status is %02x, data is %02x", str, data);
478 * When MUXERR condition is signalled the data register can only contain
479 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
480 * it is not always the case. Some KBCs also report 0xfc when there is
481 * nothing connected to the port while others sometimes get confused which
482 * port the data came from and signal error leaving the data intact. They
483 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
484 * to legacy mode yet, when we see one we'll add proper handling).
485 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
486 * rest assume that the data came from the same serio last byte
487 * was transmitted (if transmission happened not too long ago).
492 if (time_before(jiffies, last_transmit + HZ/10)) {
496 /* fall through - report timeout */
499 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
500 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
504 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
506 last_transmit = jiffies;
509 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
510 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
512 port_no = (str & I8042_STR_AUXDATA) ?
513 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
516 port = &i8042_ports[port_no];
517 serio = port->exists ? port->serio : NULL;
519 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)",
521 dfl & SERIO_PARITY ? ", bad parity" : "",
522 dfl & SERIO_TIMEOUT ? ", timeout" : "");
524 filtered = i8042_filter(data, str, serio);
526 spin_unlock_irqrestore(&i8042_lock, flags);
528 if (likely(port->exists && !filtered))
529 serio_interrupt(serio, data, dfl);
532 return IRQ_RETVAL(ret);
536 * i8042_enable_kbd_port enables keyboard port on chip
539 static int i8042_enable_kbd_port(void)
541 i8042_ctr &= ~I8042_CTR_KBDDIS;
542 i8042_ctr |= I8042_CTR_KBDINT;
544 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
545 i8042_ctr &= ~I8042_CTR_KBDINT;
546 i8042_ctr |= I8042_CTR_KBDDIS;
547 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n");
555 * i8042_enable_aux_port enables AUX (mouse) port on chip
558 static int i8042_enable_aux_port(void)
560 i8042_ctr &= ~I8042_CTR_AUXDIS;
561 i8042_ctr |= I8042_CTR_AUXINT;
563 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
564 i8042_ctr &= ~I8042_CTR_AUXINT;
565 i8042_ctr |= I8042_CTR_AUXDIS;
566 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n");
574 * i8042_enable_mux_ports enables 4 individual AUX ports after
575 * the controller has been switched into Multiplexed mode
578 static int i8042_enable_mux_ports(void)
583 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
584 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
585 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
588 return i8042_enable_aux_port();
592 * i8042_set_mux_mode checks whether the controller has an
593 * active multiplexor and puts the chip into Multiplexed (true)
594 * or Legacy (false) mode.
597 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
600 unsigned char param, val;
602 * Get rid of bytes in the queue.
608 * Internal loopback test - send three bytes, they should come back from the
609 * mouse interface, the last should be version.
613 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
615 param = val = multiplex ? 0x56 : 0xf6;
616 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
618 param = val = multiplex ? 0xa4 : 0xa5;
619 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
623 * Workaround for interference with USB Legacy emulation
624 * that causes a v10.12 MUX to be found.
630 *mux_version = param;
636 * i8042_check_mux() checks whether the controller supports the PS/2 Active
637 * Multiplexing specification by Synaptics, Phoenix, Insyde and
641 static int __init i8042_check_mux(void)
643 unsigned char mux_version;
645 if (i8042_set_mux_mode(true, &mux_version))
648 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
649 (mux_version >> 4) & 0xf, mux_version & 0xf);
652 * Disable all muxed ports by disabling AUX.
654 i8042_ctr |= I8042_CTR_AUXDIS;
655 i8042_ctr &= ~I8042_CTR_AUXINT;
657 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
658 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
662 i8042_mux_present = true;
668 * The following is used to test AUX IRQ delivery.
670 static struct completion i8042_aux_irq_delivered __initdata;
671 static bool i8042_irq_being_tested __initdata;
673 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
676 unsigned char str, data;
679 spin_lock_irqsave(&i8042_lock, flags);
680 str = i8042_read_status();
681 if (str & I8042_STR_OBF) {
682 data = i8042_read_data();
683 dbg("%02x <- i8042 (aux_test_irq, %s)",
684 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
685 if (i8042_irq_being_tested &&
686 data == 0xa5 && (str & I8042_STR_AUXDATA))
687 complete(&i8042_aux_irq_delivered);
690 spin_unlock_irqrestore(&i8042_lock, flags);
692 return IRQ_RETVAL(ret);
696 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
697 * verifies success by readinng CTR. Used when testing for presence of AUX
700 static int __init i8042_toggle_aux(bool on)
705 if (i8042_command(¶m,
706 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
709 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
710 for (i = 0; i < 100; i++) {
713 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
716 if (!(param & I8042_CTR_AUXDIS) == on)
724 * i8042_check_aux() applies as much paranoia as it can at detecting
725 * the presence of an AUX interface.
728 static int __init i8042_check_aux(void)
731 bool irq_registered = false;
732 bool aux_loop_broken = false;
737 * Get rid of bytes in the queue.
743 * Internal loopback test - filters out AT-type i8042's. Unfortunately
744 * SiS screwed up and their 5597 doesn't support the LOOP command even
745 * though it has an AUX port.
749 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
750 if (retval || param != 0x5a) {
753 * External connection test - filters out AT-soldered PS/2 i8042's
754 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
755 * 0xfa - no error on some notebooks which ignore the spec
756 * Because it's common for chipsets to return error on perfectly functioning
757 * AUX ports, we test for this only when the LOOP command failed.
760 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
761 (param && param != 0xfa && param != 0xff))
765 * If AUX_LOOP completed without error but returned unexpected data
769 aux_loop_broken = true;
773 * Bit assignment test - filters out PS/2 i8042's in AT mode
776 if (i8042_toggle_aux(false)) {
777 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
778 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
781 if (i8042_toggle_aux(true))
785 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
786 * used it for a PCI card or somethig else.
789 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
791 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
792 * is working and hope we are right.
798 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
799 "i8042", i8042_platform_device))
802 irq_registered = true;
804 if (i8042_enable_aux_port())
807 spin_lock_irqsave(&i8042_lock, flags);
809 init_completion(&i8042_aux_irq_delivered);
810 i8042_irq_being_tested = true;
813 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
815 spin_unlock_irqrestore(&i8042_lock, flags);
820 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
821 msecs_to_jiffies(250)) == 0) {
823 * AUX IRQ was never delivered so we need to flush the controller to
824 * get rid of the byte we put there; otherwise keyboard may not work.
826 dbg(" -- i8042 (aux irq test timeout)");
834 * Disable the interface.
837 i8042_ctr |= I8042_CTR_AUXDIS;
838 i8042_ctr &= ~I8042_CTR_AUXINT;
840 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
844 free_irq(I8042_AUX_IRQ, i8042_platform_device);
849 static int i8042_controller_check(void)
851 if (i8042_flush() == I8042_BUFFER_SIZE) {
852 printk(KERN_ERR "i8042.c: No controller found.\n");
859 static int i8042_controller_selftest(void)
865 * We try this 5 times; on some really fragile systems this does not
866 * take the first time...
870 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
871 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
875 if (param == I8042_RET_CTL_TEST)
878 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
879 param, I8042_RET_CTL_TEST);
885 * On x86, we don't fail entire i8042 initialization if controller
886 * reset fails in hopes that keyboard port will still be functional
887 * and user will still get a working keyboard. This is especially
888 * important on netbooks. On other arches we trust hardware more.
891 "i8042: giving up on controller selftest, continuing anyway...\n");
899 * i8042_controller init initializes the i8042 controller, and,
900 * most importantly, sets it into non-xlated mode if that's
904 static int i8042_controller_init(void)
908 unsigned char ctr[2];
911 * Save the CTR for restore on unload / reboot.
917 "i8042.c: Unable to get stable CTR read.\n");
924 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
926 "i8042.c: Can't read CTR while initializing i8042.\n");
930 } while (n < 2 || ctr[0] != ctr[1]);
932 i8042_initial_ctr = i8042_ctr = ctr[0];
935 * Disable the keyboard interface and interrupt.
938 i8042_ctr |= I8042_CTR_KBDDIS;
939 i8042_ctr &= ~I8042_CTR_KBDINT;
945 spin_lock_irqsave(&i8042_lock, flags);
946 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
948 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
950 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
952 spin_unlock_irqrestore(&i8042_lock, flags);
955 * If the chip is configured into nontranslated mode by the BIOS, don't
956 * bother enabling translating and be happy.
959 if (~i8042_ctr & I8042_CTR_XLATE)
963 * Set nontranslated mode for the kbd interface if requested by an option.
964 * After this the kbd interface becomes a simple serial in/out, like the aux
965 * interface is. We don't do this by default, since it can confuse notebook
970 i8042_ctr &= ~I8042_CTR_XLATE;
976 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
977 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
982 * Flush whatever accumulated while we were disabling keyboard port.
992 * Reset the controller and reset CRT to the original value set by BIOS.
995 static void i8042_controller_reset(void)
1000 * Disable both KBD and AUX interfaces so they don't get in the way
1003 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1004 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1006 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1007 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n");
1010 * Disable MUX mode if present.
1013 if (i8042_mux_present)
1014 i8042_set_mux_mode(false, NULL);
1017 * Reset the controller if requested.
1021 i8042_controller_selftest();
1024 * Restore the original control register setting.
1027 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1028 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
1033 * i8042_panic_blink() will flash the keyboard LEDs and is called when
1034 * kernel panics. Flashing LEDs is useful for users running X who may
1035 * not see the console and will help distingushing panics from "real"
1038 * Note that DELAY has a limit of 10ms so we will not get stuck here
1039 * waiting for KBC to free up even if KBD interrupt is off
1042 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1044 static long i8042_panic_blink(long count)
1047 static long last_blink;
1051 * We expect frequency to be about 1/2s. KDB uses about 1s.
1052 * Make sure they are different.
1054 if (!i8042_blink_frequency)
1056 if (count - last_blink < i8042_blink_frequency)
1060 while (i8042_read_status() & I8042_STR_IBF)
1062 dbg("%02x -> i8042 (panic blink)", 0xed);
1063 i8042_suppress_kbd_ack = 2;
1064 i8042_write_data(0xed); /* set leds */
1066 while (i8042_read_status() & I8042_STR_IBF)
1069 dbg("%02x -> i8042 (panic blink)", led);
1070 i8042_write_data(led);
1079 static void i8042_dritek_enable(void)
1084 error = i8042_command(¶m, 0x1059);
1087 "Failed to enable DRITEK extension: %d\n",
1095 * Here we try to reset everything back to a state we had
1096 * before suspending.
1099 static int i8042_controller_resume(bool force_reset)
1103 error = i8042_controller_check();
1107 if (i8042_reset || force_reset) {
1108 error = i8042_controller_selftest();
1114 * Restore original CTR value and disable all ports
1117 i8042_ctr = i8042_initial_ctr;
1119 i8042_ctr &= ~I8042_CTR_XLATE;
1120 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1121 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1122 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1123 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n");
1125 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1126 printk(KERN_ERR "i8042: CTR write retry failed\n");
1134 i8042_dritek_enable();
1137 if (i8042_mux_present) {
1138 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1140 "i8042: failed to resume active multiplexor, "
1141 "mouse won't work.\n");
1142 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1143 i8042_enable_aux_port();
1145 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1146 i8042_enable_kbd_port();
1148 i8042_interrupt(0, NULL);
1154 * Here we try to restore the original BIOS settings to avoid
1158 static int i8042_pm_reset(struct device *dev)
1160 i8042_controller_reset();
1165 static int i8042_pm_resume(struct device *dev)
1168 * On resume from S2R we always try to reset the controller
1169 * to bring it in a sane state. (In case of S2D we expect
1170 * BIOS to reset the controller for us.)
1172 return i8042_controller_resume(true);
1175 static int i8042_pm_thaw(struct device *dev)
1177 i8042_interrupt(0, NULL);
1182 static int i8042_pm_restore(struct device *dev)
1184 return i8042_controller_resume(false);
1187 static const struct dev_pm_ops i8042_pm_ops = {
1188 .suspend = i8042_pm_reset,
1189 .resume = i8042_pm_resume,
1190 .thaw = i8042_pm_thaw,
1191 .poweroff = i8042_pm_reset,
1192 .restore = i8042_pm_restore,
1195 #endif /* CONFIG_PM */
1198 * We need to reset the 8042 back to original mode on system shutdown,
1199 * because otherwise BIOSes will be confused.
1202 static void i8042_shutdown(struct platform_device *dev)
1204 i8042_controller_reset();
1207 static int __init i8042_create_kbd_port(void)
1209 struct serio *serio;
1210 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1212 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1216 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1217 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1218 serio->start = i8042_start;
1219 serio->stop = i8042_stop;
1220 serio->close = i8042_port_close;
1221 serio->port_data = port;
1222 serio->dev.parent = &i8042_platform_device->dev;
1223 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1224 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1226 port->serio = serio;
1227 port->irq = I8042_KBD_IRQ;
1232 static int __init i8042_create_aux_port(int idx)
1234 struct serio *serio;
1235 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1236 struct i8042_port *port = &i8042_ports[port_no];
1238 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1242 serio->id.type = SERIO_8042;
1243 serio->write = i8042_aux_write;
1244 serio->start = i8042_start;
1245 serio->stop = i8042_stop;
1246 serio->port_data = port;
1247 serio->dev.parent = &i8042_platform_device->dev;
1249 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1250 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1251 serio->close = i8042_port_close;
1253 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1254 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1257 port->serio = serio;
1259 port->irq = I8042_AUX_IRQ;
1264 static void __init i8042_free_kbd_port(void)
1266 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1267 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1270 static void __init i8042_free_aux_ports(void)
1274 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1275 kfree(i8042_ports[i].serio);
1276 i8042_ports[i].serio = NULL;
1280 static void __init i8042_register_ports(void)
1284 for (i = 0; i < I8042_NUM_PORTS; i++) {
1285 if (i8042_ports[i].serio) {
1286 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1287 i8042_ports[i].serio->name,
1288 (unsigned long) I8042_DATA_REG,
1289 (unsigned long) I8042_COMMAND_REG,
1290 i8042_ports[i].irq);
1291 serio_register_port(i8042_ports[i].serio);
1296 static void __devexit i8042_unregister_ports(void)
1300 for (i = 0; i < I8042_NUM_PORTS; i++) {
1301 if (i8042_ports[i].serio) {
1302 serio_unregister_port(i8042_ports[i].serio);
1303 i8042_ports[i].serio = NULL;
1309 * Checks whether port belongs to i8042 controller.
1311 bool i8042_check_port_owner(const struct serio *port)
1315 for (i = 0; i < I8042_NUM_PORTS; i++)
1316 if (i8042_ports[i].serio == port)
1321 EXPORT_SYMBOL(i8042_check_port_owner);
1323 static void i8042_free_irqs(void)
1325 if (i8042_aux_irq_registered)
1326 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1327 if (i8042_kbd_irq_registered)
1328 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1330 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1333 static int __init i8042_setup_aux(void)
1335 int (*aux_enable)(void);
1339 if (i8042_check_aux())
1342 if (i8042_nomux || i8042_check_mux()) {
1343 error = i8042_create_aux_port(-1);
1345 goto err_free_ports;
1346 aux_enable = i8042_enable_aux_port;
1348 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1349 error = i8042_create_aux_port(i);
1351 goto err_free_ports;
1353 aux_enable = i8042_enable_mux_ports;
1356 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1357 "i8042", i8042_platform_device);
1359 goto err_free_ports;
1364 i8042_aux_irq_registered = true;
1368 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1370 i8042_free_aux_ports();
1374 static int __init i8042_setup_kbd(void)
1378 error = i8042_create_kbd_port();
1382 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1383 "i8042", i8042_platform_device);
1387 error = i8042_enable_kbd_port();
1391 i8042_kbd_irq_registered = true;
1395 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1397 i8042_free_kbd_port();
1401 static int __init i8042_probe(struct platform_device *dev)
1405 i8042_platform_device = dev;
1408 error = i8042_controller_selftest();
1413 error = i8042_controller_init();
1419 i8042_dritek_enable();
1423 error = i8042_setup_aux();
1424 if (error && error != -ENODEV && error != -EBUSY)
1429 error = i8042_setup_kbd();
1434 * Ok, everything is ready, let's register all serio ports
1436 i8042_register_ports();
1441 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1443 i8042_controller_reset();
1444 i8042_platform_device = NULL;
1449 static int __devexit i8042_remove(struct platform_device *dev)
1451 i8042_unregister_ports();
1453 i8042_controller_reset();
1454 i8042_platform_device = NULL;
1459 static struct platform_driver i8042_driver = {
1462 .owner = THIS_MODULE,
1464 .pm = &i8042_pm_ops,
1467 .remove = __devexit_p(i8042_remove),
1468 .shutdown = i8042_shutdown,
1471 static int __init i8042_init(void)
1473 struct platform_device *pdev;
1478 err = i8042_platform_init();
1482 err = i8042_controller_check();
1484 goto err_platform_exit;
1486 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1488 err = PTR_ERR(pdev);
1489 goto err_platform_exit;
1492 panic_blink = i8042_panic_blink;
1497 i8042_platform_exit();
1501 static void __exit i8042_exit(void)
1503 platform_driver_unregister(&i8042_driver);
1504 platform_device_unregister(i8042_platform_device);
1505 i8042_platform_exit();
1510 module_init(i8042_init);
1511 module_exit(i8042_exit);