2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/init.h>
19 #include <linux/serio.h>
20 #include <linux/err.h>
21 #include <linux/rcupdate.h>
22 #include <linux/platform_device.h>
23 #include <linux/i8042.h>
27 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
28 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
29 MODULE_LICENSE("GPL");
31 static bool i8042_nokbd;
32 module_param_named(nokbd, i8042_nokbd, bool, 0);
33 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
35 static bool i8042_noaux;
36 module_param_named(noaux, i8042_noaux, bool, 0);
37 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
39 static bool i8042_nomux;
40 module_param_named(nomux, i8042_nomux, bool, 0);
41 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
43 static bool i8042_unlock;
44 module_param_named(unlock, i8042_unlock, bool, 0);
45 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
47 static bool i8042_reset;
48 module_param_named(reset, i8042_reset, bool, 0);
49 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
51 static bool i8042_direct;
52 module_param_named(direct, i8042_direct, bool, 0);
53 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
55 static bool i8042_dumbkbd;
56 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
57 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
59 static bool i8042_noloop;
60 module_param_named(noloop, i8042_noloop, bool, 0);
61 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
63 static unsigned int i8042_blink_frequency = 500;
64 module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
65 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
68 static bool i8042_dritek;
69 module_param_named(dritek, i8042_dritek, bool, 0);
70 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
74 static bool i8042_nopnp;
75 module_param_named(nopnp, i8042_nopnp, bool, 0);
76 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
81 static bool i8042_debug;
82 module_param_named(debug, i8042_debug, bool, 0600);
83 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
86 static bool i8042_bypass_aux_irq_test;
91 * i8042_lock protects serialization between i8042_command and
92 * the interrupt handler.
94 static DEFINE_SPINLOCK(i8042_lock);
97 * Writers to AUX and KBD ports as well as users issuing i8042_command
98 * directly should acquire i8042_mutex (by means of calling
99 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
100 * they do not disturb each other (unfortunately in many i8042
101 * implementations write to one of the ports will immediately abort
102 * command that is being processed by another port).
104 static DEFINE_MUTEX(i8042_mutex);
113 #define I8042_KBD_PORT_NO 0
114 #define I8042_AUX_PORT_NO 1
115 #define I8042_MUX_PORT_NO 2
116 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
118 static struct i8042_port i8042_ports[I8042_NUM_PORTS];
120 static unsigned char i8042_initial_ctr;
121 static unsigned char i8042_ctr;
122 static bool i8042_mux_present;
123 static bool i8042_kbd_irq_registered;
124 static bool i8042_aux_irq_registered;
125 static unsigned char i8042_suppress_kbd_ack;
126 static struct platform_device *i8042_platform_device;
128 static irqreturn_t i8042_interrupt(int irq, void *dev_id);
129 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
130 struct serio *serio);
132 void i8042_lock_chip(void)
134 mutex_lock(&i8042_mutex);
136 EXPORT_SYMBOL(i8042_lock_chip);
138 void i8042_unlock_chip(void)
140 mutex_unlock(&i8042_mutex);
142 EXPORT_SYMBOL(i8042_unlock_chip);
144 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
145 struct serio *serio))
150 spin_lock_irqsave(&i8042_lock, flags);
152 if (i8042_platform_filter) {
157 i8042_platform_filter = filter;
160 spin_unlock_irqrestore(&i8042_lock, flags);
163 EXPORT_SYMBOL(i8042_install_filter);
165 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
171 spin_lock_irqsave(&i8042_lock, flags);
173 if (i8042_platform_filter != filter) {
178 i8042_platform_filter = NULL;
181 spin_unlock_irqrestore(&i8042_lock, flags);
184 EXPORT_SYMBOL(i8042_remove_filter);
187 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
188 * be ready for reading values from it / writing values to it.
189 * Called always with i8042_lock held.
192 static int i8042_wait_read(void)
196 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
200 return -(i == I8042_CTL_TIMEOUT);
203 static int i8042_wait_write(void)
207 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
211 return -(i == I8042_CTL_TIMEOUT);
215 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
216 * of the i8042 down the toilet.
219 static int i8042_flush(void)
222 unsigned char data, str;
225 spin_lock_irqsave(&i8042_lock, flags);
227 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
229 data = i8042_read_data();
231 dbg("%02x <- i8042 (flush, %s)", data,
232 str & I8042_STR_AUXDATA ? "aux" : "kbd");
235 spin_unlock_irqrestore(&i8042_lock, flags);
241 * i8042_command() executes a command on the i8042. It also sends the input
242 * parameter(s) of the commands to it, and receives the output value(s). The
243 * parameters are to be stored in the param array, and the output is placed
244 * into the same array. The number of the parameters and output values is
245 * encoded in bits 8-11 of the command number.
248 static int __i8042_command(unsigned char *param, int command)
252 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
255 error = i8042_wait_write();
259 dbg("%02x -> i8042 (command)", command & 0xff);
260 i8042_write_command(command & 0xff);
262 for (i = 0; i < ((command >> 12) & 0xf); i++) {
263 error = i8042_wait_write();
266 dbg("%02x -> i8042 (parameter)", param[i]);
267 i8042_write_data(param[i]);
270 for (i = 0; i < ((command >> 8) & 0xf); i++) {
271 error = i8042_wait_read();
273 dbg(" -- i8042 (timeout)");
277 if (command == I8042_CMD_AUX_LOOP &&
278 !(i8042_read_status() & I8042_STR_AUXDATA)) {
279 dbg(" -- i8042 (auxerr)");
283 param[i] = i8042_read_data();
284 dbg("%02x <- i8042 (return)", param[i]);
290 int i8042_command(unsigned char *param, int command)
295 spin_lock_irqsave(&i8042_lock, flags);
296 retval = __i8042_command(param, command);
297 spin_unlock_irqrestore(&i8042_lock, flags);
301 EXPORT_SYMBOL(i8042_command);
304 * i8042_kbd_write() sends a byte out through the keyboard interface.
307 static int i8042_kbd_write(struct serio *port, unsigned char c)
312 spin_lock_irqsave(&i8042_lock, flags);
314 if (!(retval = i8042_wait_write())) {
315 dbg("%02x -> i8042 (kbd-data)", c);
319 spin_unlock_irqrestore(&i8042_lock, flags);
325 * i8042_aux_write() sends a byte out through the aux interface.
328 static int i8042_aux_write(struct serio *serio, unsigned char c)
330 struct i8042_port *port = serio->port_data;
332 return i8042_command(&c, port->mux == -1 ?
334 I8042_CMD_MUX_SEND + port->mux);
339 * i8042_aux_close attempts to clear AUX or KBD port state by disabling
340 * and then re-enabling it.
343 static void i8042_port_close(struct serio *serio)
347 const char *port_name;
349 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
350 irq_bit = I8042_CTR_AUXINT;
351 disable_bit = I8042_CTR_AUXDIS;
354 irq_bit = I8042_CTR_KBDINT;
355 disable_bit = I8042_CTR_KBDDIS;
359 i8042_ctr &= ~irq_bit;
360 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
362 "i8042.c: Can't write CTR while closing %s port.\n",
367 i8042_ctr &= ~disable_bit;
368 i8042_ctr |= irq_bit;
369 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
370 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n",
374 * See if there is any data appeared while we were messing with
377 i8042_interrupt(0, NULL);
381 * i8042_start() is called by serio core when port is about to finish
382 * registering. It will mark port as existing so i8042_interrupt can
383 * start sending data through it.
385 static int i8042_start(struct serio *serio)
387 struct i8042_port *port = serio->port_data;
395 * i8042_stop() marks serio port as non-existing so i8042_interrupt
396 * will not try to send data to the port that is about to go away.
397 * The function is called by serio core as part of unregister procedure.
399 static void i8042_stop(struct serio *serio)
401 struct i8042_port *port = serio->port_data;
403 port->exists = false;
406 * We synchronize with both AUX and KBD IRQs because there is
407 * a (very unlikely) chance that AUX IRQ is raised for KBD port
410 synchronize_irq(I8042_AUX_IRQ);
411 synchronize_irq(I8042_KBD_IRQ);
416 * i8042_filter() filters out unwanted bytes from the input data stream.
417 * It is called from i8042_interrupt and thus is running with interrupts
418 * off and i8042_lock held.
420 static bool i8042_filter(unsigned char data, unsigned char str,
423 if (unlikely(i8042_suppress_kbd_ack)) {
424 if ((~str & I8042_STR_AUXDATA) &&
425 (data == 0xfa || data == 0xfe)) {
426 i8042_suppress_kbd_ack--;
427 dbg("Extra keyboard ACK - filtered out\n");
432 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
433 dbg("Filtered out by platform filter\n");
441 * i8042_interrupt() is the most important function in this driver -
442 * it handles the interrupts from the i8042, and sends incoming bytes
443 * to the upper layers.
446 static irqreturn_t i8042_interrupt(int irq, void *dev_id)
448 struct i8042_port *port;
451 unsigned char str, data;
453 unsigned int port_no;
457 spin_lock_irqsave(&i8042_lock, flags);
459 str = i8042_read_status();
460 if (unlikely(~str & I8042_STR_OBF)) {
461 spin_unlock_irqrestore(&i8042_lock, flags);
462 if (irq) dbg("Interrupt %d, without any data", irq);
467 data = i8042_read_data();
469 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
470 static unsigned long last_transmit;
471 static unsigned char last_str;
474 if (str & I8042_STR_MUXERR) {
475 dbg("MUX error, status is %02x, data is %02x", str, data);
477 * When MUXERR condition is signalled the data register can only contain
478 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
479 * it is not always the case. Some KBCs also report 0xfc when there is
480 * nothing connected to the port while others sometimes get confused which
481 * port the data came from and signal error leaving the data intact. They
482 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
483 * to legacy mode yet, when we see one we'll add proper handling).
484 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
485 * rest assume that the data came from the same serio last byte
486 * was transmitted (if transmission happened not too long ago).
491 if (time_before(jiffies, last_transmit + HZ/10)) {
495 /* fall through - report timeout */
498 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
499 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
503 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
505 last_transmit = jiffies;
508 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
509 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
511 port_no = (str & I8042_STR_AUXDATA) ?
512 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
515 port = &i8042_ports[port_no];
516 serio = port->exists ? port->serio : NULL;
518 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)",
520 dfl & SERIO_PARITY ? ", bad parity" : "",
521 dfl & SERIO_TIMEOUT ? ", timeout" : "");
523 filtered = i8042_filter(data, str, serio);
525 spin_unlock_irqrestore(&i8042_lock, flags);
527 if (likely(port->exists && !filtered))
528 serio_interrupt(serio, data, dfl);
531 return IRQ_RETVAL(ret);
535 * i8042_enable_kbd_port enables keyboard port on chip
538 static int i8042_enable_kbd_port(void)
540 i8042_ctr &= ~I8042_CTR_KBDDIS;
541 i8042_ctr |= I8042_CTR_KBDINT;
543 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
544 i8042_ctr &= ~I8042_CTR_KBDINT;
545 i8042_ctr |= I8042_CTR_KBDDIS;
546 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n");
554 * i8042_enable_aux_port enables AUX (mouse) port on chip
557 static int i8042_enable_aux_port(void)
559 i8042_ctr &= ~I8042_CTR_AUXDIS;
560 i8042_ctr |= I8042_CTR_AUXINT;
562 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
563 i8042_ctr &= ~I8042_CTR_AUXINT;
564 i8042_ctr |= I8042_CTR_AUXDIS;
565 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n");
573 * i8042_enable_mux_ports enables 4 individual AUX ports after
574 * the controller has been switched into Multiplexed mode
577 static int i8042_enable_mux_ports(void)
582 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
583 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
584 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
587 return i8042_enable_aux_port();
591 * i8042_set_mux_mode checks whether the controller has an
592 * active multiplexor and puts the chip into Multiplexed (true)
593 * or Legacy (false) mode.
596 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
599 unsigned char param, val;
601 * Get rid of bytes in the queue.
607 * Internal loopback test - send three bytes, they should come back from the
608 * mouse interface, the last should be version.
612 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
614 param = val = multiplex ? 0x56 : 0xf6;
615 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
617 param = val = multiplex ? 0xa4 : 0xa5;
618 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
622 * Workaround for interference with USB Legacy emulation
623 * that causes a v10.12 MUX to be found.
629 *mux_version = param;
635 * i8042_check_mux() checks whether the controller supports the PS/2 Active
636 * Multiplexing specification by Synaptics, Phoenix, Insyde and
640 static int __init i8042_check_mux(void)
642 unsigned char mux_version;
644 if (i8042_set_mux_mode(true, &mux_version))
647 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
648 (mux_version >> 4) & 0xf, mux_version & 0xf);
651 * Disable all muxed ports by disabling AUX.
653 i8042_ctr |= I8042_CTR_AUXDIS;
654 i8042_ctr &= ~I8042_CTR_AUXINT;
656 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
657 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
661 i8042_mux_present = true;
667 * The following is used to test AUX IRQ delivery.
669 static struct completion i8042_aux_irq_delivered __initdata;
670 static bool i8042_irq_being_tested __initdata;
672 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
675 unsigned char str, data;
678 spin_lock_irqsave(&i8042_lock, flags);
679 str = i8042_read_status();
680 if (str & I8042_STR_OBF) {
681 data = i8042_read_data();
682 dbg("%02x <- i8042 (aux_test_irq, %s)",
683 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
684 if (i8042_irq_being_tested &&
685 data == 0xa5 && (str & I8042_STR_AUXDATA))
686 complete(&i8042_aux_irq_delivered);
689 spin_unlock_irqrestore(&i8042_lock, flags);
691 return IRQ_RETVAL(ret);
695 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
696 * verifies success by readinng CTR. Used when testing for presence of AUX
699 static int __init i8042_toggle_aux(bool on)
704 if (i8042_command(¶m,
705 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
708 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
709 for (i = 0; i < 100; i++) {
712 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
715 if (!(param & I8042_CTR_AUXDIS) == on)
723 * i8042_check_aux() applies as much paranoia as it can at detecting
724 * the presence of an AUX interface.
727 static int __init i8042_check_aux(void)
730 bool irq_registered = false;
731 bool aux_loop_broken = false;
736 * Get rid of bytes in the queue.
742 * Internal loopback test - filters out AT-type i8042's. Unfortunately
743 * SiS screwed up and their 5597 doesn't support the LOOP command even
744 * though it has an AUX port.
748 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
749 if (retval || param != 0x5a) {
752 * External connection test - filters out AT-soldered PS/2 i8042's
753 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
754 * 0xfa - no error on some notebooks which ignore the spec
755 * Because it's common for chipsets to return error on perfectly functioning
756 * AUX ports, we test for this only when the LOOP command failed.
759 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
760 (param && param != 0xfa && param != 0xff))
764 * If AUX_LOOP completed without error but returned unexpected data
768 aux_loop_broken = true;
772 * Bit assignment test - filters out PS/2 i8042's in AT mode
775 if (i8042_toggle_aux(false)) {
776 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
777 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
780 if (i8042_toggle_aux(true))
784 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
785 * used it for a PCI card or somethig else.
788 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
790 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
791 * is working and hope we are right.
797 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
798 "i8042", i8042_platform_device))
801 irq_registered = true;
803 if (i8042_enable_aux_port())
806 spin_lock_irqsave(&i8042_lock, flags);
808 init_completion(&i8042_aux_irq_delivered);
809 i8042_irq_being_tested = true;
812 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
814 spin_unlock_irqrestore(&i8042_lock, flags);
819 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
820 msecs_to_jiffies(250)) == 0) {
822 * AUX IRQ was never delivered so we need to flush the controller to
823 * get rid of the byte we put there; otherwise keyboard may not work.
825 dbg(" -- i8042 (aux irq test timeout)");
833 * Disable the interface.
836 i8042_ctr |= I8042_CTR_AUXDIS;
837 i8042_ctr &= ~I8042_CTR_AUXINT;
839 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
843 free_irq(I8042_AUX_IRQ, i8042_platform_device);
848 static int i8042_controller_check(void)
850 if (i8042_flush() == I8042_BUFFER_SIZE) {
851 printk(KERN_ERR "i8042.c: No controller found.\n");
858 static int i8042_controller_selftest(void)
867 * We try this 5 times; on some really fragile systems this does not
868 * take the first time...
872 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
873 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
877 if (param == I8042_RET_CTL_TEST)
880 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
881 param, I8042_RET_CTL_TEST);
887 * On x86, we don't fail entire i8042 initialization if controller
888 * reset fails in hopes that keyboard port will still be functional
889 * and user will still get a working keyboard. This is especially
890 * important on netbooks. On other arches we trust hardware more.
893 "i8042: giving up on controller selftest, continuing anyway...\n");
901 * i8042_controller init initializes the i8042 controller, and,
902 * most importantly, sets it into non-xlated mode if that's
906 static int i8042_controller_init(void)
910 unsigned char ctr[2];
913 * Save the CTR for restore on unload / reboot.
919 "i8042.c: Unable to get stable CTR read.\n");
926 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
928 "i8042.c: Can't read CTR while initializing i8042.\n");
932 } while (n < 2 || ctr[0] != ctr[1]);
934 i8042_initial_ctr = i8042_ctr = ctr[0];
937 * Disable the keyboard interface and interrupt.
940 i8042_ctr |= I8042_CTR_KBDDIS;
941 i8042_ctr &= ~I8042_CTR_KBDINT;
947 spin_lock_irqsave(&i8042_lock, flags);
948 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
950 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
952 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
954 spin_unlock_irqrestore(&i8042_lock, flags);
957 * If the chip is configured into nontranslated mode by the BIOS, don't
958 * bother enabling translating and be happy.
961 if (~i8042_ctr & I8042_CTR_XLATE)
965 * Set nontranslated mode for the kbd interface if requested by an option.
966 * After this the kbd interface becomes a simple serial in/out, like the aux
967 * interface is. We don't do this by default, since it can confuse notebook
972 i8042_ctr &= ~I8042_CTR_XLATE;
978 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
979 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
984 * Flush whatever accumulated while we were disabling keyboard port.
994 * Reset the controller and reset CRT to the original value set by BIOS.
997 static void i8042_controller_reset(void)
1002 * Disable both KBD and AUX interfaces so they don't get in the way
1005 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1006 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1008 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1009 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n");
1012 * Disable MUX mode if present.
1015 if (i8042_mux_present)
1016 i8042_set_mux_mode(false, NULL);
1019 * Reset the controller if requested.
1022 i8042_controller_selftest();
1025 * Restore the original control register setting.
1028 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1029 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
1034 * i8042_panic_blink() will flash the keyboard LEDs and is called when
1035 * kernel panics. Flashing LEDs is useful for users running X who may
1036 * not see the console and will help distingushing panics from "real"
1039 * Note that DELAY has a limit of 10ms so we will not get stuck here
1040 * waiting for KBC to free up even if KBD interrupt is off
1043 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1045 static long i8042_panic_blink(long count)
1048 static long last_blink;
1052 * We expect frequency to be about 1/2s. KDB uses about 1s.
1053 * Make sure they are different.
1055 if (!i8042_blink_frequency)
1057 if (count - last_blink < i8042_blink_frequency)
1061 while (i8042_read_status() & I8042_STR_IBF)
1063 dbg("%02x -> i8042 (panic blink)", 0xed);
1064 i8042_suppress_kbd_ack = 2;
1065 i8042_write_data(0xed); /* set leds */
1067 while (i8042_read_status() & I8042_STR_IBF)
1070 dbg("%02x -> i8042 (panic blink)", led);
1071 i8042_write_data(led);
1080 static void i8042_dritek_enable(void)
1085 error = i8042_command(¶m, 0x1059);
1088 "Failed to enable DRITEK extension: %d\n",
1096 * Here we try to restore the original BIOS settings to avoid
1100 static int i8042_pm_reset(struct device *dev)
1102 i8042_controller_reset();
1108 * Here we try to reset everything back to a state we had
1109 * before suspending.
1112 static int i8042_pm_restore(struct device *dev)
1116 error = i8042_controller_check();
1120 error = i8042_controller_selftest();
1125 * Restore original CTR value and disable all ports
1128 i8042_ctr = i8042_initial_ctr;
1130 i8042_ctr &= ~I8042_CTR_XLATE;
1131 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1132 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1133 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1134 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n");
1136 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1137 printk(KERN_ERR "i8042: CTR write retry failed\n");
1145 i8042_dritek_enable();
1148 if (i8042_mux_present) {
1149 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1151 "i8042: failed to resume active multiplexor, "
1152 "mouse won't work.\n");
1153 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1154 i8042_enable_aux_port();
1156 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1157 i8042_enable_kbd_port();
1159 i8042_interrupt(0, NULL);
1164 static int i8042_pm_thaw(struct device *dev)
1166 i8042_interrupt(0, NULL);
1171 static const struct dev_pm_ops i8042_pm_ops = {
1172 .suspend = i8042_pm_reset,
1173 .resume = i8042_pm_restore,
1174 .thaw = i8042_pm_thaw,
1175 .poweroff = i8042_pm_reset,
1176 .restore = i8042_pm_restore,
1179 #endif /* CONFIG_PM */
1182 * We need to reset the 8042 back to original mode on system shutdown,
1183 * because otherwise BIOSes will be confused.
1186 static void i8042_shutdown(struct platform_device *dev)
1188 i8042_controller_reset();
1191 static int __init i8042_create_kbd_port(void)
1193 struct serio *serio;
1194 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1196 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1200 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1201 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1202 serio->start = i8042_start;
1203 serio->stop = i8042_stop;
1204 serio->close = i8042_port_close;
1205 serio->port_data = port;
1206 serio->dev.parent = &i8042_platform_device->dev;
1207 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1208 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1210 port->serio = serio;
1211 port->irq = I8042_KBD_IRQ;
1216 static int __init i8042_create_aux_port(int idx)
1218 struct serio *serio;
1219 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1220 struct i8042_port *port = &i8042_ports[port_no];
1222 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1226 serio->id.type = SERIO_8042;
1227 serio->write = i8042_aux_write;
1228 serio->start = i8042_start;
1229 serio->stop = i8042_stop;
1230 serio->port_data = port;
1231 serio->dev.parent = &i8042_platform_device->dev;
1233 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1234 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1235 serio->close = i8042_port_close;
1237 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1238 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1241 port->serio = serio;
1243 port->irq = I8042_AUX_IRQ;
1248 static void __init i8042_free_kbd_port(void)
1250 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1251 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1254 static void __init i8042_free_aux_ports(void)
1258 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1259 kfree(i8042_ports[i].serio);
1260 i8042_ports[i].serio = NULL;
1264 static void __init i8042_register_ports(void)
1268 for (i = 0; i < I8042_NUM_PORTS; i++) {
1269 if (i8042_ports[i].serio) {
1270 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1271 i8042_ports[i].serio->name,
1272 (unsigned long) I8042_DATA_REG,
1273 (unsigned long) I8042_COMMAND_REG,
1274 i8042_ports[i].irq);
1275 serio_register_port(i8042_ports[i].serio);
1280 static void __devexit i8042_unregister_ports(void)
1284 for (i = 0; i < I8042_NUM_PORTS; i++) {
1285 if (i8042_ports[i].serio) {
1286 serio_unregister_port(i8042_ports[i].serio);
1287 i8042_ports[i].serio = NULL;
1293 * Checks whether port belongs to i8042 controller.
1295 bool i8042_check_port_owner(const struct serio *port)
1299 for (i = 0; i < I8042_NUM_PORTS; i++)
1300 if (i8042_ports[i].serio == port)
1305 EXPORT_SYMBOL(i8042_check_port_owner);
1307 static void i8042_free_irqs(void)
1309 if (i8042_aux_irq_registered)
1310 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1311 if (i8042_kbd_irq_registered)
1312 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1314 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1317 static int __init i8042_setup_aux(void)
1319 int (*aux_enable)(void);
1323 if (i8042_check_aux())
1326 if (i8042_nomux || i8042_check_mux()) {
1327 error = i8042_create_aux_port(-1);
1329 goto err_free_ports;
1330 aux_enable = i8042_enable_aux_port;
1332 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1333 error = i8042_create_aux_port(i);
1335 goto err_free_ports;
1337 aux_enable = i8042_enable_mux_ports;
1340 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1341 "i8042", i8042_platform_device);
1343 goto err_free_ports;
1348 i8042_aux_irq_registered = true;
1352 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1354 i8042_free_aux_ports();
1358 static int __init i8042_setup_kbd(void)
1362 error = i8042_create_kbd_port();
1366 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1367 "i8042", i8042_platform_device);
1371 error = i8042_enable_kbd_port();
1375 i8042_kbd_irq_registered = true;
1379 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1381 i8042_free_kbd_port();
1385 static int __init i8042_probe(struct platform_device *dev)
1389 i8042_platform_device = dev;
1391 error = i8042_controller_selftest();
1395 error = i8042_controller_init();
1401 i8042_dritek_enable();
1405 error = i8042_setup_aux();
1406 if (error && error != -ENODEV && error != -EBUSY)
1411 error = i8042_setup_kbd();
1416 * Ok, everything is ready, let's register all serio ports
1418 i8042_register_ports();
1423 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1425 i8042_controller_reset();
1426 i8042_platform_device = NULL;
1431 static int __devexit i8042_remove(struct platform_device *dev)
1433 i8042_unregister_ports();
1435 i8042_controller_reset();
1436 i8042_platform_device = NULL;
1441 static struct platform_driver i8042_driver = {
1444 .owner = THIS_MODULE,
1446 .pm = &i8042_pm_ops,
1449 .remove = __devexit_p(i8042_remove),
1450 .shutdown = i8042_shutdown,
1453 static int __init i8042_init(void)
1455 struct platform_device *pdev;
1460 err = i8042_platform_init();
1464 err = i8042_controller_check();
1466 goto err_platform_exit;
1468 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1470 err = PTR_ERR(pdev);
1471 goto err_platform_exit;
1474 panic_blink = i8042_panic_blink;
1479 i8042_platform_exit();
1483 static void __exit i8042_exit(void)
1485 platform_driver_unregister(&i8042_driver);
1486 platform_device_unregister(i8042_platform_device);
1487 i8042_platform_exit();
1492 module_init(i8042_init);
1493 module_exit(i8042_exit);