2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/serio.h>
22 #include <linux/err.h>
23 #include <linux/rcupdate.h>
24 #include <linux/platform_device.h>
25 #include <linux/i8042.h>
26 #include <linux/slab.h>
30 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
31 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
32 MODULE_LICENSE("GPL");
34 static bool i8042_nokbd;
35 module_param_named(nokbd, i8042_nokbd, bool, 0);
36 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
38 static bool i8042_noaux;
39 module_param_named(noaux, i8042_noaux, bool, 0);
40 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
42 static bool i8042_nomux;
43 module_param_named(nomux, i8042_nomux, bool, 0);
44 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
46 static bool i8042_unlock;
47 module_param_named(unlock, i8042_unlock, bool, 0);
48 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
50 static bool i8042_reset;
51 module_param_named(reset, i8042_reset, bool, 0);
52 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
54 static bool i8042_direct;
55 module_param_named(direct, i8042_direct, bool, 0);
56 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
58 static bool i8042_dumbkbd;
59 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
60 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
62 static bool i8042_noloop;
63 module_param_named(noloop, i8042_noloop, bool, 0);
64 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
67 static bool i8042_dritek;
68 module_param_named(dritek, i8042_dritek, bool, 0);
69 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
73 static bool i8042_nopnp;
74 module_param_named(nopnp, i8042_nopnp, bool, 0);
75 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
80 static bool i8042_debug;
81 module_param_named(debug, i8042_debug, bool, 0600);
82 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
85 static bool i8042_bypass_aux_irq_test;
90 * i8042_lock protects serialization between i8042_command and
91 * the interrupt handler.
93 static DEFINE_SPINLOCK(i8042_lock);
96 * Writers to AUX and KBD ports as well as users issuing i8042_command
97 * directly should acquire i8042_mutex (by means of calling
98 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
99 * they do not disturb each other (unfortunately in many i8042
100 * implementations write to one of the ports will immediately abort
101 * command that is being processed by another port).
103 static DEFINE_MUTEX(i8042_mutex);
112 #define I8042_KBD_PORT_NO 0
113 #define I8042_AUX_PORT_NO 1
114 #define I8042_MUX_PORT_NO 2
115 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
117 static struct i8042_port i8042_ports[I8042_NUM_PORTS];
119 static unsigned char i8042_initial_ctr;
120 static unsigned char i8042_ctr;
121 static bool i8042_mux_present;
122 static bool i8042_kbd_irq_registered;
123 static bool i8042_aux_irq_registered;
124 static unsigned char i8042_suppress_kbd_ack;
125 static struct platform_device *i8042_platform_device;
127 static irqreturn_t i8042_interrupt(int irq, void *dev_id);
128 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
129 struct serio *serio);
131 void i8042_lock_chip(void)
133 mutex_lock(&i8042_mutex);
135 EXPORT_SYMBOL(i8042_lock_chip);
137 void i8042_unlock_chip(void)
139 mutex_unlock(&i8042_mutex);
141 EXPORT_SYMBOL(i8042_unlock_chip);
143 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
144 struct serio *serio))
149 spin_lock_irqsave(&i8042_lock, flags);
151 if (i8042_platform_filter) {
156 i8042_platform_filter = filter;
159 spin_unlock_irqrestore(&i8042_lock, flags);
162 EXPORT_SYMBOL(i8042_install_filter);
164 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
170 spin_lock_irqsave(&i8042_lock, flags);
172 if (i8042_platform_filter != filter) {
177 i8042_platform_filter = NULL;
180 spin_unlock_irqrestore(&i8042_lock, flags);
183 EXPORT_SYMBOL(i8042_remove_filter);
186 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
187 * be ready for reading values from it / writing values to it.
188 * Called always with i8042_lock held.
191 static int i8042_wait_read(void)
195 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
199 return -(i == I8042_CTL_TIMEOUT);
202 static int i8042_wait_write(void)
206 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
210 return -(i == I8042_CTL_TIMEOUT);
214 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
215 * of the i8042 down the toilet.
218 static int i8042_flush(void)
221 unsigned char data, str;
224 spin_lock_irqsave(&i8042_lock, flags);
226 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
228 data = i8042_read_data();
230 dbg("%02x <- i8042 (flush, %s)\n",
231 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
234 spin_unlock_irqrestore(&i8042_lock, flags);
240 * i8042_command() executes a command on the i8042. It also sends the input
241 * parameter(s) of the commands to it, and receives the output value(s). The
242 * parameters are to be stored in the param array, and the output is placed
243 * into the same array. The number of the parameters and output values is
244 * encoded in bits 8-11 of the command number.
247 static int __i8042_command(unsigned char *param, int command)
251 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
254 error = i8042_wait_write();
258 dbg("%02x -> i8042 (command)\n", command & 0xff);
259 i8042_write_command(command & 0xff);
261 for (i = 0; i < ((command >> 12) & 0xf); i++) {
262 error = i8042_wait_write();
265 dbg("%02x -> i8042 (parameter)\n", param[i]);
266 i8042_write_data(param[i]);
269 for (i = 0; i < ((command >> 8) & 0xf); i++) {
270 error = i8042_wait_read();
272 dbg(" -- i8042 (timeout)\n");
276 if (command == I8042_CMD_AUX_LOOP &&
277 !(i8042_read_status() & I8042_STR_AUXDATA)) {
278 dbg(" -- i8042 (auxerr)\n");
282 param[i] = i8042_read_data();
283 dbg("%02x <- i8042 (return)\n", param[i]);
289 int i8042_command(unsigned char *param, int command)
294 spin_lock_irqsave(&i8042_lock, flags);
295 retval = __i8042_command(param, command);
296 spin_unlock_irqrestore(&i8042_lock, flags);
300 EXPORT_SYMBOL(i8042_command);
303 * i8042_kbd_write() sends a byte out through the keyboard interface.
306 static int i8042_kbd_write(struct serio *port, unsigned char c)
311 spin_lock_irqsave(&i8042_lock, flags);
313 if (!(retval = i8042_wait_write())) {
314 dbg("%02x -> i8042 (kbd-data)\n", c);
318 spin_unlock_irqrestore(&i8042_lock, flags);
324 * i8042_aux_write() sends a byte out through the aux interface.
327 static int i8042_aux_write(struct serio *serio, unsigned char c)
329 struct i8042_port *port = serio->port_data;
331 return i8042_command(&c, port->mux == -1 ?
333 I8042_CMD_MUX_SEND + port->mux);
338 * i8042_aux_close attempts to clear AUX or KBD port state by disabling
339 * and then re-enabling it.
342 static void i8042_port_close(struct serio *serio)
346 const char *port_name;
348 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
349 irq_bit = I8042_CTR_AUXINT;
350 disable_bit = I8042_CTR_AUXDIS;
353 irq_bit = I8042_CTR_KBDINT;
354 disable_bit = I8042_CTR_KBDDIS;
358 i8042_ctr &= ~irq_bit;
359 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
360 pr_warn("Can't write CTR while closing %s port\n", port_name);
364 i8042_ctr &= ~disable_bit;
365 i8042_ctr |= irq_bit;
366 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
367 pr_err("Can't reactivate %s port\n", port_name);
370 * See if there is any data appeared while we were messing with
373 i8042_interrupt(0, NULL);
377 * i8042_start() is called by serio core when port is about to finish
378 * registering. It will mark port as existing so i8042_interrupt can
379 * start sending data through it.
381 static int i8042_start(struct serio *serio)
383 struct i8042_port *port = serio->port_data;
391 * i8042_stop() marks serio port as non-existing so i8042_interrupt
392 * will not try to send data to the port that is about to go away.
393 * The function is called by serio core as part of unregister procedure.
395 static void i8042_stop(struct serio *serio)
397 struct i8042_port *port = serio->port_data;
399 port->exists = false;
402 * We synchronize with both AUX and KBD IRQs because there is
403 * a (very unlikely) chance that AUX IRQ is raised for KBD port
406 synchronize_irq(I8042_AUX_IRQ);
407 synchronize_irq(I8042_KBD_IRQ);
412 * i8042_filter() filters out unwanted bytes from the input data stream.
413 * It is called from i8042_interrupt and thus is running with interrupts
414 * off and i8042_lock held.
416 static bool i8042_filter(unsigned char data, unsigned char str,
419 if (unlikely(i8042_suppress_kbd_ack)) {
420 if ((~str & I8042_STR_AUXDATA) &&
421 (data == 0xfa || data == 0xfe)) {
422 i8042_suppress_kbd_ack--;
423 dbg("Extra keyboard ACK - filtered out\n");
428 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
429 dbg("Filtered out by platform filter\n");
437 * i8042_interrupt() is the most important function in this driver -
438 * it handles the interrupts from the i8042, and sends incoming bytes
439 * to the upper layers.
442 static irqreturn_t i8042_interrupt(int irq, void *dev_id)
444 struct i8042_port *port;
447 unsigned char str, data;
449 unsigned int port_no;
453 spin_lock_irqsave(&i8042_lock, flags);
455 str = i8042_read_status();
456 if (unlikely(~str & I8042_STR_OBF)) {
457 spin_unlock_irqrestore(&i8042_lock, flags);
459 dbg("Interrupt %d, without any data\n", irq);
464 data = i8042_read_data();
466 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
467 static unsigned long last_transmit;
468 static unsigned char last_str;
471 if (str & I8042_STR_MUXERR) {
472 dbg("MUX error, status is %02x, data is %02x\n",
475 * When MUXERR condition is signalled the data register can only contain
476 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
477 * it is not always the case. Some KBCs also report 0xfc when there is
478 * nothing connected to the port while others sometimes get confused which
479 * port the data came from and signal error leaving the data intact. They
480 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
481 * to legacy mode yet, when we see one we'll add proper handling).
482 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
483 * rest assume that the data came from the same serio last byte
484 * was transmitted (if transmission happened not too long ago).
489 if (time_before(jiffies, last_transmit + HZ/10)) {
493 /* fall through - report timeout */
496 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
497 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
501 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
503 last_transmit = jiffies;
506 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
507 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
509 port_no = (str & I8042_STR_AUXDATA) ?
510 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
513 port = &i8042_ports[port_no];
514 serio = port->exists ? port->serio : NULL;
516 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n",
518 dfl & SERIO_PARITY ? ", bad parity" : "",
519 dfl & SERIO_TIMEOUT ? ", timeout" : "");
521 filtered = i8042_filter(data, str, serio);
523 spin_unlock_irqrestore(&i8042_lock, flags);
525 if (likely(port->exists && !filtered))
526 serio_interrupt(serio, data, dfl);
529 return IRQ_RETVAL(ret);
533 * i8042_enable_kbd_port enables keyboard port on chip
536 static int i8042_enable_kbd_port(void)
538 i8042_ctr &= ~I8042_CTR_KBDDIS;
539 i8042_ctr |= I8042_CTR_KBDINT;
541 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
542 i8042_ctr &= ~I8042_CTR_KBDINT;
543 i8042_ctr |= I8042_CTR_KBDDIS;
544 pr_err("Failed to enable KBD port\n");
552 * i8042_enable_aux_port enables AUX (mouse) port on chip
555 static int i8042_enable_aux_port(void)
557 i8042_ctr &= ~I8042_CTR_AUXDIS;
558 i8042_ctr |= I8042_CTR_AUXINT;
560 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
561 i8042_ctr &= ~I8042_CTR_AUXINT;
562 i8042_ctr |= I8042_CTR_AUXDIS;
563 pr_err("Failed to enable AUX port\n");
571 * i8042_enable_mux_ports enables 4 individual AUX ports after
572 * the controller has been switched into Multiplexed mode
575 static int i8042_enable_mux_ports(void)
580 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
581 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
582 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
585 return i8042_enable_aux_port();
589 * i8042_set_mux_mode checks whether the controller has an
590 * active multiplexor and puts the chip into Multiplexed (true)
591 * or Legacy (false) mode.
594 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
597 unsigned char param, val;
599 * Get rid of bytes in the queue.
605 * Internal loopback test - send three bytes, they should come back from the
606 * mouse interface, the last should be version.
610 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
612 param = val = multiplex ? 0x56 : 0xf6;
613 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
615 param = val = multiplex ? 0xa4 : 0xa5;
616 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
620 * Workaround for interference with USB Legacy emulation
621 * that causes a v10.12 MUX to be found.
627 *mux_version = param;
633 * i8042_check_mux() checks whether the controller supports the PS/2 Active
634 * Multiplexing specification by Synaptics, Phoenix, Insyde and
638 static int __init i8042_check_mux(void)
640 unsigned char mux_version;
642 if (i8042_set_mux_mode(true, &mux_version))
645 pr_info("Detected active multiplexing controller, rev %d.%d\n",
646 (mux_version >> 4) & 0xf, mux_version & 0xf);
649 * Disable all muxed ports by disabling AUX.
651 i8042_ctr |= I8042_CTR_AUXDIS;
652 i8042_ctr &= ~I8042_CTR_AUXINT;
654 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
655 pr_err("Failed to disable AUX port, can't use MUX\n");
659 i8042_mux_present = true;
665 * The following is used to test AUX IRQ delivery.
667 static struct completion i8042_aux_irq_delivered __initdata;
668 static bool i8042_irq_being_tested __initdata;
670 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
673 unsigned char str, data;
676 spin_lock_irqsave(&i8042_lock, flags);
677 str = i8042_read_status();
678 if (str & I8042_STR_OBF) {
679 data = i8042_read_data();
680 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
681 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
682 if (i8042_irq_being_tested &&
683 data == 0xa5 && (str & I8042_STR_AUXDATA))
684 complete(&i8042_aux_irq_delivered);
687 spin_unlock_irqrestore(&i8042_lock, flags);
689 return IRQ_RETVAL(ret);
693 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
694 * verifies success by readinng CTR. Used when testing for presence of AUX
697 static int __init i8042_toggle_aux(bool on)
702 if (i8042_command(¶m,
703 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
706 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
707 for (i = 0; i < 100; i++) {
710 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
713 if (!(param & I8042_CTR_AUXDIS) == on)
721 * i8042_check_aux() applies as much paranoia as it can at detecting
722 * the presence of an AUX interface.
725 static int __init i8042_check_aux(void)
728 bool irq_registered = false;
729 bool aux_loop_broken = false;
734 * Get rid of bytes in the queue.
740 * Internal loopback test - filters out AT-type i8042's. Unfortunately
741 * SiS screwed up and their 5597 doesn't support the LOOP command even
742 * though it has an AUX port.
746 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
747 if (retval || param != 0x5a) {
750 * External connection test - filters out AT-soldered PS/2 i8042's
751 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
752 * 0xfa - no error on some notebooks which ignore the spec
753 * Because it's common for chipsets to return error on perfectly functioning
754 * AUX ports, we test for this only when the LOOP command failed.
757 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
758 (param && param != 0xfa && param != 0xff))
762 * If AUX_LOOP completed without error but returned unexpected data
766 aux_loop_broken = true;
770 * Bit assignment test - filters out PS/2 i8042's in AT mode
773 if (i8042_toggle_aux(false)) {
774 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
775 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
778 if (i8042_toggle_aux(true))
782 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
783 * used it for a PCI card or somethig else.
786 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
788 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
789 * is working and hope we are right.
795 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
796 "i8042", i8042_platform_device))
799 irq_registered = true;
801 if (i8042_enable_aux_port())
804 spin_lock_irqsave(&i8042_lock, flags);
806 init_completion(&i8042_aux_irq_delivered);
807 i8042_irq_being_tested = true;
810 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
812 spin_unlock_irqrestore(&i8042_lock, flags);
817 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
818 msecs_to_jiffies(250)) == 0) {
820 * AUX IRQ was never delivered so we need to flush the controller to
821 * get rid of the byte we put there; otherwise keyboard may not work.
823 dbg(" -- i8042 (aux irq test timeout)\n");
831 * Disable the interface.
834 i8042_ctr |= I8042_CTR_AUXDIS;
835 i8042_ctr &= ~I8042_CTR_AUXINT;
837 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
841 free_irq(I8042_AUX_IRQ, i8042_platform_device);
846 static int i8042_controller_check(void)
848 if (i8042_flush() == I8042_BUFFER_SIZE) {
849 pr_err("No controller found\n");
856 static int i8042_controller_selftest(void)
862 * We try this 5 times; on some really fragile systems this does not
863 * take the first time...
867 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
868 pr_err("i8042 controller self test timeout\n");
872 if (param == I8042_RET_CTL_TEST)
875 pr_err("i8042 controller selftest failed. (%#x != %#x)\n",
876 param, I8042_RET_CTL_TEST);
882 * On x86, we don't fail entire i8042 initialization if controller
883 * reset fails in hopes that keyboard port will still be functional
884 * and user will still get a working keyboard. This is especially
885 * important on netbooks. On other arches we trust hardware more.
887 pr_info("giving up on controller selftest, continuing anyway...\n");
895 * i8042_controller init initializes the i8042 controller, and,
896 * most importantly, sets it into non-xlated mode if that's
900 static int i8042_controller_init(void)
904 unsigned char ctr[2];
907 * Save the CTR for restore on unload / reboot.
912 pr_err("Unable to get stable CTR read\n");
919 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
920 pr_err("Can't read CTR while initializing i8042\n");
924 } while (n < 2 || ctr[0] != ctr[1]);
926 i8042_initial_ctr = i8042_ctr = ctr[0];
929 * Disable the keyboard interface and interrupt.
932 i8042_ctr |= I8042_CTR_KBDDIS;
933 i8042_ctr &= ~I8042_CTR_KBDINT;
939 spin_lock_irqsave(&i8042_lock, flags);
940 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
942 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
944 pr_warn("Warning: Keylock active\n");
946 spin_unlock_irqrestore(&i8042_lock, flags);
949 * If the chip is configured into nontranslated mode by the BIOS, don't
950 * bother enabling translating and be happy.
953 if (~i8042_ctr & I8042_CTR_XLATE)
957 * Set nontranslated mode for the kbd interface if requested by an option.
958 * After this the kbd interface becomes a simple serial in/out, like the aux
959 * interface is. We don't do this by default, since it can confuse notebook
964 i8042_ctr &= ~I8042_CTR_XLATE;
970 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
971 pr_err("Can't write CTR while initializing i8042\n");
976 * Flush whatever accumulated while we were disabling keyboard port.
986 * Reset the controller and reset CRT to the original value set by BIOS.
989 static void i8042_controller_reset(void)
994 * Disable both KBD and AUX interfaces so they don't get in the way
997 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
998 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1000 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1001 pr_warn("Can't write CTR while resetting\n");
1004 * Disable MUX mode if present.
1007 if (i8042_mux_present)
1008 i8042_set_mux_mode(false, NULL);
1011 * Reset the controller if requested.
1015 i8042_controller_selftest();
1018 * Restore the original control register setting.
1021 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1022 pr_warn("Can't restore CTR\n");
1027 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
1028 * when kernel panics. Flashing LEDs is useful for users running X who may
1029 * not see the console and will help distingushing panics from "real"
1032 * Note that DELAY has a limit of 10ms so we will not get stuck here
1033 * waiting for KBC to free up even if KBD interrupt is off
1036 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1038 static long i8042_panic_blink(int state)
1043 led = (state) ? 0x01 | 0x04 : 0;
1044 while (i8042_read_status() & I8042_STR_IBF)
1046 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1047 i8042_suppress_kbd_ack = 2;
1048 i8042_write_data(0xed); /* set leds */
1050 while (i8042_read_status() & I8042_STR_IBF)
1053 dbg("%02x -> i8042 (panic blink)\n", led);
1054 i8042_write_data(led);
1062 static void i8042_dritek_enable(void)
1064 unsigned char param = 0x90;
1067 error = i8042_command(¶m, 0x1059);
1069 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1076 * Here we try to reset everything back to a state we had
1077 * before suspending.
1080 static int i8042_controller_resume(bool force_reset)
1084 error = i8042_controller_check();
1088 if (i8042_reset || force_reset) {
1089 error = i8042_controller_selftest();
1095 * Restore original CTR value and disable all ports
1098 i8042_ctr = i8042_initial_ctr;
1100 i8042_ctr &= ~I8042_CTR_XLATE;
1101 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1102 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1103 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1104 pr_warn("Can't write CTR to resume, retrying...\n");
1106 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1107 pr_err("CTR write retry failed\n");
1115 i8042_dritek_enable();
1118 if (i8042_mux_present) {
1119 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1120 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1121 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1122 i8042_enable_aux_port();
1124 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1125 i8042_enable_kbd_port();
1127 i8042_interrupt(0, NULL);
1133 * Here we try to restore the original BIOS settings to avoid
1137 static int i8042_pm_reset(struct device *dev)
1139 i8042_controller_reset();
1144 static int i8042_pm_resume(struct device *dev)
1147 * On resume from S2R we always try to reset the controller
1148 * to bring it in a sane state. (In case of S2D we expect
1149 * BIOS to reset the controller for us.)
1151 return i8042_controller_resume(true);
1154 static int i8042_pm_thaw(struct device *dev)
1156 i8042_interrupt(0, NULL);
1161 static int i8042_pm_restore(struct device *dev)
1163 return i8042_controller_resume(false);
1166 static const struct dev_pm_ops i8042_pm_ops = {
1167 .suspend = i8042_pm_reset,
1168 .resume = i8042_pm_resume,
1169 .thaw = i8042_pm_thaw,
1170 .poweroff = i8042_pm_reset,
1171 .restore = i8042_pm_restore,
1174 #endif /* CONFIG_PM */
1177 * We need to reset the 8042 back to original mode on system shutdown,
1178 * because otherwise BIOSes will be confused.
1181 static void i8042_shutdown(struct platform_device *dev)
1183 i8042_controller_reset();
1186 static int __init i8042_create_kbd_port(void)
1188 struct serio *serio;
1189 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1191 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1195 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1196 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1197 serio->start = i8042_start;
1198 serio->stop = i8042_stop;
1199 serio->close = i8042_port_close;
1200 serio->port_data = port;
1201 serio->dev.parent = &i8042_platform_device->dev;
1202 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1203 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1205 port->serio = serio;
1206 port->irq = I8042_KBD_IRQ;
1211 static int __init i8042_create_aux_port(int idx)
1213 struct serio *serio;
1214 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1215 struct i8042_port *port = &i8042_ports[port_no];
1217 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1221 serio->id.type = SERIO_8042;
1222 serio->write = i8042_aux_write;
1223 serio->start = i8042_start;
1224 serio->stop = i8042_stop;
1225 serio->port_data = port;
1226 serio->dev.parent = &i8042_platform_device->dev;
1228 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1229 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1230 serio->close = i8042_port_close;
1232 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1233 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1236 port->serio = serio;
1238 port->irq = I8042_AUX_IRQ;
1243 static void __init i8042_free_kbd_port(void)
1245 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1246 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1249 static void __init i8042_free_aux_ports(void)
1253 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1254 kfree(i8042_ports[i].serio);
1255 i8042_ports[i].serio = NULL;
1259 static void __init i8042_register_ports(void)
1263 for (i = 0; i < I8042_NUM_PORTS; i++) {
1264 if (i8042_ports[i].serio) {
1265 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1266 i8042_ports[i].serio->name,
1267 (unsigned long) I8042_DATA_REG,
1268 (unsigned long) I8042_COMMAND_REG,
1269 i8042_ports[i].irq);
1270 serio_register_port(i8042_ports[i].serio);
1275 static void __devexit i8042_unregister_ports(void)
1279 for (i = 0; i < I8042_NUM_PORTS; i++) {
1280 if (i8042_ports[i].serio) {
1281 serio_unregister_port(i8042_ports[i].serio);
1282 i8042_ports[i].serio = NULL;
1288 * Checks whether port belongs to i8042 controller.
1290 bool i8042_check_port_owner(const struct serio *port)
1294 for (i = 0; i < I8042_NUM_PORTS; i++)
1295 if (i8042_ports[i].serio == port)
1300 EXPORT_SYMBOL(i8042_check_port_owner);
1302 static void i8042_free_irqs(void)
1304 if (i8042_aux_irq_registered)
1305 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1306 if (i8042_kbd_irq_registered)
1307 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1309 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1312 static int __init i8042_setup_aux(void)
1314 int (*aux_enable)(void);
1318 if (i8042_check_aux())
1321 if (i8042_nomux || i8042_check_mux()) {
1322 error = i8042_create_aux_port(-1);
1324 goto err_free_ports;
1325 aux_enable = i8042_enable_aux_port;
1327 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1328 error = i8042_create_aux_port(i);
1330 goto err_free_ports;
1332 aux_enable = i8042_enable_mux_ports;
1335 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1336 "i8042", i8042_platform_device);
1338 goto err_free_ports;
1343 i8042_aux_irq_registered = true;
1347 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1349 i8042_free_aux_ports();
1353 static int __init i8042_setup_kbd(void)
1357 error = i8042_create_kbd_port();
1361 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1362 "i8042", i8042_platform_device);
1366 error = i8042_enable_kbd_port();
1370 i8042_kbd_irq_registered = true;
1374 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1376 i8042_free_kbd_port();
1380 static int __init i8042_probe(struct platform_device *dev)
1384 i8042_platform_device = dev;
1387 error = i8042_controller_selftest();
1392 error = i8042_controller_init();
1398 i8042_dritek_enable();
1402 error = i8042_setup_aux();
1403 if (error && error != -ENODEV && error != -EBUSY)
1408 error = i8042_setup_kbd();
1413 * Ok, everything is ready, let's register all serio ports
1415 i8042_register_ports();
1420 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1422 i8042_controller_reset();
1423 i8042_platform_device = NULL;
1428 static int __devexit i8042_remove(struct platform_device *dev)
1430 i8042_unregister_ports();
1432 i8042_controller_reset();
1433 i8042_platform_device = NULL;
1438 static struct platform_driver i8042_driver = {
1441 .owner = THIS_MODULE,
1443 .pm = &i8042_pm_ops,
1446 .remove = __devexit_p(i8042_remove),
1447 .shutdown = i8042_shutdown,
1450 static int __init i8042_init(void)
1452 struct platform_device *pdev;
1457 err = i8042_platform_init();
1461 err = i8042_controller_check();
1463 goto err_platform_exit;
1465 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1467 err = PTR_ERR(pdev);
1468 goto err_platform_exit;
1471 panic_blink = i8042_panic_blink;
1476 i8042_platform_exit();
1480 static void __exit i8042_exit(void)
1482 platform_device_unregister(i8042_platform_device);
1483 platform_driver_unregister(&i8042_driver);
1484 i8042_platform_exit();
1489 module_init(i8042_init);
1490 module_exit(i8042_exit);