2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <asm/pci-direct.h>
33 #include <asm/iommu.h>
35 #include <asm/x86_init.h>
36 #include <asm/iommu_table.h>
37 #include <asm/io_apic.h>
38 #include <asm/irq_remapping.h>
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
42 #include "irq_remapping.h"
45 * definitions for the ACPI scanning code
47 #define IVRS_HEADER_LENGTH 48
49 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
50 #define ACPI_IVMD_TYPE_ALL 0x20
51 #define ACPI_IVMD_TYPE 0x21
52 #define ACPI_IVMD_TYPE_RANGE 0x22
54 #define IVHD_DEV_ALL 0x01
55 #define IVHD_DEV_SELECT 0x02
56 #define IVHD_DEV_SELECT_RANGE_START 0x03
57 #define IVHD_DEV_RANGE_END 0x04
58 #define IVHD_DEV_ALIAS 0x42
59 #define IVHD_DEV_ALIAS_RANGE 0x43
60 #define IVHD_DEV_EXT_SELECT 0x46
61 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
62 #define IVHD_DEV_SPECIAL 0x48
63 #define IVHD_DEV_ACPI_HID 0xf0
65 #define UID_NOT_PRESENT 0
66 #define UID_IS_INTEGER 1
67 #define UID_IS_CHARACTER 2
69 #define IVHD_SPECIAL_IOAPIC 1
70 #define IVHD_SPECIAL_HPET 2
72 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
73 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
74 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
75 #define IVHD_FLAG_ISOC_EN_MASK 0x08
77 #define IVMD_FLAG_EXCL_RANGE 0x08
78 #define IVMD_FLAG_UNITY_MAP 0x01
80 #define ACPI_DEVFLAG_INITPASS 0x01
81 #define ACPI_DEVFLAG_EXTINT 0x02
82 #define ACPI_DEVFLAG_NMI 0x04
83 #define ACPI_DEVFLAG_SYSMGT1 0x10
84 #define ACPI_DEVFLAG_SYSMGT2 0x20
85 #define ACPI_DEVFLAG_LINT0 0x40
86 #define ACPI_DEVFLAG_LINT1 0x80
87 #define ACPI_DEVFLAG_ATSDIS 0x10000000
89 #define LOOP_TIMEOUT 100000
91 * ACPI table definitions
93 * These data structures are laid over the table to parse the important values
97 extern const struct iommu_ops amd_iommu_ops;
100 * structure describing one IOMMU in the ACPI table. Typically followed by one
101 * or more ivhd_entrys.
114 /* Following only valid on IVHD type 11h and 40h */
115 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
117 } __attribute__((packed));
120 * A device entry describing which devices a specific IOMMU translates and
121 * which requestor ids they use.
133 } __attribute__((packed));
136 * An AMD IOMMU memory definition structure. It defines things like exclusion
137 * ranges for devices and regions that should be unity mapped.
148 } __attribute__((packed));
151 bool amd_iommu_irq_remap __read_mostly;
153 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
155 static bool amd_iommu_detected;
156 static bool __initdata amd_iommu_disabled;
157 static int amd_iommu_target_ivhd_type;
159 u16 amd_iommu_last_bdf; /* largest PCI device id we have
161 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
163 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
165 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
168 /* Array to assign indices to IOMMUs*/
169 struct amd_iommu *amd_iommus[MAX_IOMMUS];
171 /* Number of IOMMUs present in the system */
172 static int amd_iommus_present;
174 /* IOMMUs have a non-present cache? */
175 bool amd_iommu_np_cache __read_mostly;
176 bool amd_iommu_iotlb_sup __read_mostly = true;
178 u32 amd_iommu_max_pasid __read_mostly = ~0;
180 bool amd_iommu_v2_present __read_mostly;
181 static bool amd_iommu_pc_present __read_mostly;
183 bool amd_iommu_force_isolation __read_mostly;
186 * List of protection domains - used during resume
188 LIST_HEAD(amd_iommu_pd_list);
189 spinlock_t amd_iommu_pd_lock;
192 * Pointer to the device table which is shared by all AMD IOMMUs
193 * it is indexed by the PCI device id or the HT unit id and contains
194 * information about the domain the device belongs to as well as the
195 * page table root pointer.
197 struct dev_table_entry *amd_iommu_dev_table;
200 * The alias table is a driver specific data structure which contains the
201 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
202 * More than one device can share the same requestor id.
204 u16 *amd_iommu_alias_table;
207 * The rlookup table is used to find the IOMMU which is responsible
208 * for a specific device. It is also indexed by the PCI device id.
210 struct amd_iommu **amd_iommu_rlookup_table;
213 * This table is used to find the irq remapping table for a given device id
216 struct irq_remap_table **irq_lookup_table;
219 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
220 * to know which ones are already in use.
222 unsigned long *amd_iommu_pd_alloc_bitmap;
224 static u32 dev_table_size; /* size of the device table */
225 static u32 alias_table_size; /* size of the alias table */
226 static u32 rlookup_table_size; /* size if the rlookup table */
228 enum iommu_init_state {
241 /* Early ioapic and hpet maps from kernel command line */
242 #define EARLY_MAP_SIZE 4
243 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
244 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
245 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
247 static int __initdata early_ioapic_map_size;
248 static int __initdata early_hpet_map_size;
249 static int __initdata early_acpihid_map_size;
251 static bool __initdata cmdline_maps;
253 static enum iommu_init_state init_state = IOMMU_START_STATE;
255 static int amd_iommu_enable_interrupts(void);
256 static int __init iommu_go_to_state(enum iommu_init_state state);
257 static void init_device_table_dma(void);
259 static inline void update_last_devid(u16 devid)
261 if (devid > amd_iommu_last_bdf)
262 amd_iommu_last_bdf = devid;
265 static inline unsigned long tbl_size(int entry_size)
267 unsigned shift = PAGE_SHIFT +
268 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
273 int amd_iommu_get_num_iommus(void)
275 return amd_iommus_present;
278 /* Access to l1 and l2 indexed register spaces */
280 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
284 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
285 pci_read_config_dword(iommu->dev, 0xfc, &val);
289 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
291 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
292 pci_write_config_dword(iommu->dev, 0xfc, val);
293 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
296 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
300 pci_write_config_dword(iommu->dev, 0xf0, address);
301 pci_read_config_dword(iommu->dev, 0xf4, &val);
305 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
307 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
308 pci_write_config_dword(iommu->dev, 0xf4, val);
311 /****************************************************************************
313 * AMD IOMMU MMIO register space handling functions
315 * These functions are used to program the IOMMU device registers in
316 * MMIO space required for that driver.
318 ****************************************************************************/
321 * This function set the exclusion range in the IOMMU. DMA accesses to the
322 * exclusion range are passed through untranslated
324 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
326 u64 start = iommu->exclusion_start & PAGE_MASK;
327 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
330 if (!iommu->exclusion_start)
333 entry = start | MMIO_EXCL_ENABLE_MASK;
334 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
335 &entry, sizeof(entry));
338 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
339 &entry, sizeof(entry));
342 /* Programs the physical address of the device table into the IOMMU hardware */
343 static void iommu_set_device_table(struct amd_iommu *iommu)
347 BUG_ON(iommu->mmio_base == NULL);
349 entry = virt_to_phys(amd_iommu_dev_table);
350 entry |= (dev_table_size >> 12) - 1;
351 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
352 &entry, sizeof(entry));
355 /* Generic functions to enable/disable certain features of the IOMMU. */
356 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
360 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
362 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
365 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
369 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
371 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
374 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
378 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
379 ctrl &= ~CTRL_INV_TO_MASK;
380 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
381 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
384 /* Function to enable the hardware */
385 static void iommu_enable(struct amd_iommu *iommu)
387 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
390 static void iommu_disable(struct amd_iommu *iommu)
392 /* Disable command buffer */
393 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
395 /* Disable event logging and event interrupts */
396 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
397 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
399 /* Disable IOMMU GA_LOG */
400 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
401 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
403 /* Disable IOMMU hardware itself */
404 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
408 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
409 * the system has one.
411 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
413 if (!request_mem_region(address, end, "amd_iommu")) {
414 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
416 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
420 return (u8 __iomem *)ioremap_nocache(address, end);
423 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
425 if (iommu->mmio_base)
426 iounmap(iommu->mmio_base);
427 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
430 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
446 /****************************************************************************
448 * The functions below belong to the first pass of AMD IOMMU ACPI table
449 * parsing. In this pass we try to find out the highest device id this
450 * code has to handle. Upon this information the size of the shared data
451 * structures is determined later.
453 ****************************************************************************/
456 * This function calculates the length of a given IVHD entry
458 static inline int ivhd_entry_length(u8 *ivhd)
460 u32 type = ((struct ivhd_entry *)ivhd)->type;
463 return 0x04 << (*ivhd >> 6);
464 } else if (type == IVHD_DEV_ACPI_HID) {
465 /* For ACPI_HID, offset 21 is uid len */
466 return *((u8 *)ivhd + 21) + 22;
472 * After reading the highest device id from the IOMMU PCI capability header
473 * this function looks if there is a higher device id defined in the ACPI table
475 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
477 u8 *p = (void *)h, *end = (void *)h;
478 struct ivhd_entry *dev;
480 u32 ivhd_size = get_ivhd_header_size(h);
483 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
491 dev = (struct ivhd_entry *)p;
494 /* Use maximum BDF value for DEV_ALL */
495 update_last_devid(0xffff);
497 case IVHD_DEV_SELECT:
498 case IVHD_DEV_RANGE_END:
500 case IVHD_DEV_EXT_SELECT:
501 /* all the above subfield types refer to device ids */
502 update_last_devid(dev->devid);
507 p += ivhd_entry_length(p);
515 static int __init check_ivrs_checksum(struct acpi_table_header *table)
518 u8 checksum = 0, *p = (u8 *)table;
520 for (i = 0; i < table->length; ++i)
523 /* ACPI table corrupt */
524 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
532 * Iterate over all IVHD entries in the ACPI table and find the highest device
533 * id which we need to handle. This is the first of three functions which parse
534 * the ACPI table. So we check the checksum here.
536 static int __init find_last_devid_acpi(struct acpi_table_header *table)
538 u8 *p = (u8 *)table, *end = (u8 *)table;
539 struct ivhd_header *h;
541 p += IVRS_HEADER_LENGTH;
543 end += table->length;
545 h = (struct ivhd_header *)p;
546 if (h->type == amd_iommu_target_ivhd_type) {
547 int ret = find_last_devid_from_ivhd(h);
559 /****************************************************************************
561 * The following functions belong to the code path which parses the ACPI table
562 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
563 * data structures, initialize the device/alias/rlookup table and also
564 * basically initialize the hardware.
566 ****************************************************************************/
569 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
570 * write commands to that buffer later and the IOMMU will execute them
573 static int __init alloc_command_buffer(struct amd_iommu *iommu)
575 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
576 get_order(CMD_BUFFER_SIZE));
578 return iommu->cmd_buf ? 0 : -ENOMEM;
582 * This function resets the command buffer if the IOMMU stopped fetching
585 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
587 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
589 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
590 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
592 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
596 * This function writes the command buffer address to the hardware and
599 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
603 BUG_ON(iommu->cmd_buf == NULL);
605 entry = (u64)virt_to_phys(iommu->cmd_buf);
606 entry |= MMIO_CMD_SIZE_512;
608 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
609 &entry, sizeof(entry));
611 amd_iommu_reset_cmd_buffer(iommu);
614 static void __init free_command_buffer(struct amd_iommu *iommu)
616 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
619 /* allocates the memory where the IOMMU will log its events to */
620 static int __init alloc_event_buffer(struct amd_iommu *iommu)
622 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
623 get_order(EVT_BUFFER_SIZE));
625 return iommu->evt_buf ? 0 : -ENOMEM;
628 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
632 BUG_ON(iommu->evt_buf == NULL);
634 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
636 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
637 &entry, sizeof(entry));
639 /* set head and tail to zero manually */
640 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
641 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
643 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
646 static void __init free_event_buffer(struct amd_iommu *iommu)
648 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
651 /* allocates the memory where the IOMMU will log its events to */
652 static int __init alloc_ppr_log(struct amd_iommu *iommu)
654 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
655 get_order(PPR_LOG_SIZE));
657 return iommu->ppr_log ? 0 : -ENOMEM;
660 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
664 if (iommu->ppr_log == NULL)
667 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
669 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
670 &entry, sizeof(entry));
672 /* set head and tail to zero manually */
673 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
674 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
676 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
677 iommu_feature_enable(iommu, CONTROL_PPR_EN);
680 static void __init free_ppr_log(struct amd_iommu *iommu)
682 if (iommu->ppr_log == NULL)
685 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
688 static void free_ga_log(struct amd_iommu *iommu)
690 #ifdef CONFIG_IRQ_REMAP
692 free_pages((unsigned long)iommu->ga_log,
693 get_order(GA_LOG_SIZE));
694 if (iommu->ga_log_tail)
695 free_pages((unsigned long)iommu->ga_log_tail,
700 static int iommu_ga_log_enable(struct amd_iommu *iommu)
702 #ifdef CONFIG_IRQ_REMAP
708 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
710 /* Check if already running */
711 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
714 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
715 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
717 for (i = 0; i < LOOP_TIMEOUT; ++i) {
718 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
719 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
723 if (i >= LOOP_TIMEOUT)
725 #endif /* CONFIG_IRQ_REMAP */
729 #ifdef CONFIG_IRQ_REMAP
730 static int iommu_init_ga_log(struct amd_iommu *iommu)
734 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
737 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
738 get_order(GA_LOG_SIZE));
742 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
744 if (!iommu->ga_log_tail)
747 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
748 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
749 &entry, sizeof(entry));
750 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
751 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
752 &entry, sizeof(entry));
753 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
754 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
761 #endif /* CONFIG_IRQ_REMAP */
763 static int iommu_init_ga(struct amd_iommu *iommu)
767 #ifdef CONFIG_IRQ_REMAP
768 /* Note: We have already checked GASup from IVRS table.
769 * Now, we need to make sure that GAMSup is set.
771 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
772 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
773 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
775 ret = iommu_init_ga_log(iommu);
776 #endif /* CONFIG_IRQ_REMAP */
781 static void iommu_enable_gt(struct amd_iommu *iommu)
783 if (!iommu_feature(iommu, FEATURE_GT))
786 iommu_feature_enable(iommu, CONTROL_GT_EN);
789 /* sets a specific bit in the device table entry. */
790 static void set_dev_entry_bit(u16 devid, u8 bit)
792 int i = (bit >> 6) & 0x03;
793 int _bit = bit & 0x3f;
795 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
798 static int get_dev_entry_bit(u16 devid, u8 bit)
800 int i = (bit >> 6) & 0x03;
801 int _bit = bit & 0x3f;
803 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
807 void amd_iommu_apply_erratum_63(u16 devid)
811 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
812 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
815 set_dev_entry_bit(devid, DEV_ENTRY_IW);
818 /* Writes the specific IOMMU for a device into the rlookup table */
819 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
821 amd_iommu_rlookup_table[devid] = iommu;
825 * This function takes the device specific flags read from the ACPI
826 * table and sets up the device table entry with that information
828 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
829 u16 devid, u32 flags, u32 ext_flags)
831 if (flags & ACPI_DEVFLAG_INITPASS)
832 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
833 if (flags & ACPI_DEVFLAG_EXTINT)
834 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
835 if (flags & ACPI_DEVFLAG_NMI)
836 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
837 if (flags & ACPI_DEVFLAG_SYSMGT1)
838 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
839 if (flags & ACPI_DEVFLAG_SYSMGT2)
840 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
841 if (flags & ACPI_DEVFLAG_LINT0)
842 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
843 if (flags & ACPI_DEVFLAG_LINT1)
844 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
846 amd_iommu_apply_erratum_63(devid);
848 set_iommu_for_device(iommu, devid);
851 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
853 struct devid_map *entry;
854 struct list_head *list;
856 if (type == IVHD_SPECIAL_IOAPIC)
858 else if (type == IVHD_SPECIAL_HPET)
863 list_for_each_entry(entry, list, list) {
864 if (!(entry->id == id && entry->cmd_line))
867 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
868 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
870 *devid = entry->devid;
875 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
880 entry->devid = *devid;
881 entry->cmd_line = cmd_line;
883 list_add_tail(&entry->list, list);
888 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
891 struct acpihid_map_entry *entry;
892 struct list_head *list = &acpihid_map;
894 list_for_each_entry(entry, list, list) {
895 if (strcmp(entry->hid, hid) ||
896 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
900 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
902 *devid = entry->devid;
906 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
910 memcpy(entry->uid, uid, strlen(uid));
911 memcpy(entry->hid, hid, strlen(hid));
912 entry->devid = *devid;
913 entry->cmd_line = cmd_line;
914 entry->root_devid = (entry->devid & (~0x7));
916 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
917 entry->cmd_line ? "cmd" : "ivrs",
918 entry->hid, entry->uid, entry->root_devid);
920 list_add_tail(&entry->list, list);
924 static int __init add_early_maps(void)
928 for (i = 0; i < early_ioapic_map_size; ++i) {
929 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
930 early_ioapic_map[i].id,
931 &early_ioapic_map[i].devid,
932 early_ioapic_map[i].cmd_line);
937 for (i = 0; i < early_hpet_map_size; ++i) {
938 ret = add_special_device(IVHD_SPECIAL_HPET,
939 early_hpet_map[i].id,
940 &early_hpet_map[i].devid,
941 early_hpet_map[i].cmd_line);
946 for (i = 0; i < early_acpihid_map_size; ++i) {
947 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
948 early_acpihid_map[i].uid,
949 &early_acpihid_map[i].devid,
950 early_acpihid_map[i].cmd_line);
959 * Reads the device exclusion range from ACPI and initializes the IOMMU with
962 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
964 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
966 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
971 * We only can configure exclusion ranges per IOMMU, not
972 * per device. But we can enable the exclusion range per
973 * device. This is done here
975 set_dev_entry_bit(devid, DEV_ENTRY_EX);
976 iommu->exclusion_start = m->range_start;
977 iommu->exclusion_length = m->range_length;
982 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
983 * initializes the hardware and our data structures with it.
985 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
986 struct ivhd_header *h)
989 u8 *end = p, flags = 0;
990 u16 devid = 0, devid_start = 0, devid_to = 0;
991 u32 dev_i, ext_flags = 0;
993 struct ivhd_entry *e;
998 ret = add_early_maps();
1003 * First save the recommended feature enable bits from ACPI
1005 iommu->acpi_flags = h->flags;
1008 * Done. Now parse the device entries
1010 ivhd_size = get_ivhd_header_size(h);
1012 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1022 e = (struct ivhd_entry *)p;
1026 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1028 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1029 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1031 case IVHD_DEV_SELECT:
1033 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1035 PCI_BUS_NUM(e->devid),
1041 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1043 case IVHD_DEV_SELECT_RANGE_START:
1045 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1046 "devid: %02x:%02x.%x flags: %02x\n",
1047 PCI_BUS_NUM(e->devid),
1052 devid_start = e->devid;
1057 case IVHD_DEV_ALIAS:
1059 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1060 "flags: %02x devid_to: %02x:%02x.%x\n",
1061 PCI_BUS_NUM(e->devid),
1065 PCI_BUS_NUM(e->ext >> 8),
1066 PCI_SLOT(e->ext >> 8),
1067 PCI_FUNC(e->ext >> 8));
1070 devid_to = e->ext >> 8;
1071 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1072 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1073 amd_iommu_alias_table[devid] = devid_to;
1075 case IVHD_DEV_ALIAS_RANGE:
1077 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1078 "devid: %02x:%02x.%x flags: %02x "
1079 "devid_to: %02x:%02x.%x\n",
1080 PCI_BUS_NUM(e->devid),
1084 PCI_BUS_NUM(e->ext >> 8),
1085 PCI_SLOT(e->ext >> 8),
1086 PCI_FUNC(e->ext >> 8));
1088 devid_start = e->devid;
1090 devid_to = e->ext >> 8;
1094 case IVHD_DEV_EXT_SELECT:
1096 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1097 "flags: %02x ext: %08x\n",
1098 PCI_BUS_NUM(e->devid),
1104 set_dev_entry_from_acpi(iommu, devid, e->flags,
1107 case IVHD_DEV_EXT_SELECT_RANGE:
1109 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1110 "%02x:%02x.%x flags: %02x ext: %08x\n",
1111 PCI_BUS_NUM(e->devid),
1116 devid_start = e->devid;
1121 case IVHD_DEV_RANGE_END:
1123 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1124 PCI_BUS_NUM(e->devid),
1126 PCI_FUNC(e->devid));
1129 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1131 amd_iommu_alias_table[dev_i] = devid_to;
1132 set_dev_entry_from_acpi(iommu,
1133 devid_to, flags, ext_flags);
1135 set_dev_entry_from_acpi(iommu, dev_i,
1139 case IVHD_DEV_SPECIAL: {
1145 handle = e->ext & 0xff;
1146 devid = (e->ext >> 8) & 0xffff;
1147 type = (e->ext >> 24) & 0xff;
1149 if (type == IVHD_SPECIAL_IOAPIC)
1151 else if (type == IVHD_SPECIAL_HPET)
1156 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1162 ret = add_special_device(type, handle, &devid, false);
1167 * add_special_device might update the devid in case a
1168 * command-line override is present. So call
1169 * set_dev_entry_from_acpi after add_special_device.
1171 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1175 case IVHD_DEV_ACPI_HID: {
1177 u8 hid[ACPIHID_HID_LEN] = {0};
1178 u8 uid[ACPIHID_UID_LEN] = {0};
1181 if (h->type != 0x40) {
1182 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1187 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1188 hid[ACPIHID_HID_LEN - 1] = '\0';
1191 pr_err(FW_BUG "Invalid HID.\n");
1196 case UID_NOT_PRESENT:
1199 pr_warn(FW_BUG "Invalid UID length.\n");
1202 case UID_IS_INTEGER:
1204 sprintf(uid, "%d", e->uid);
1207 case UID_IS_CHARACTER:
1209 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1210 uid[ACPIHID_UID_LEN - 1] = '\0';
1218 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1226 ret = add_acpi_hid_device(hid, uid, &devid, false);
1231 * add_special_device might update the devid in case a
1232 * command-line override is present. So call
1233 * set_dev_entry_from_acpi after add_special_device.
1235 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1243 p += ivhd_entry_length(p);
1249 static void __init free_iommu_one(struct amd_iommu *iommu)
1251 free_command_buffer(iommu);
1252 free_event_buffer(iommu);
1253 free_ppr_log(iommu);
1255 iommu_unmap_mmio_space(iommu);
1258 static void __init free_iommu_all(void)
1260 struct amd_iommu *iommu, *next;
1262 for_each_iommu_safe(iommu, next) {
1263 list_del(&iommu->list);
1264 free_iommu_one(iommu);
1270 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1272 * BIOS should disable L2B micellaneous clock gating by setting
1273 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1275 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1279 if ((boot_cpu_data.x86 != 0x15) ||
1280 (boot_cpu_data.x86_model < 0x10) ||
1281 (boot_cpu_data.x86_model > 0x1f))
1284 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1285 pci_read_config_dword(iommu->dev, 0xf4, &value);
1290 /* Select NB indirect register 0x90 and enable writing */
1291 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1293 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1294 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1295 dev_name(&iommu->dev->dev));
1297 /* Clear the enable writing bit */
1298 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1302 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1304 * BIOS should enable ATS write permission check by setting
1305 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1307 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1311 if ((boot_cpu_data.x86 != 0x15) ||
1312 (boot_cpu_data.x86_model < 0x30) ||
1313 (boot_cpu_data.x86_model > 0x3f))
1316 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1317 value = iommu_read_l2(iommu, 0x47);
1322 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1323 iommu_write_l2(iommu, 0x47, value | BIT(0));
1325 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1326 dev_name(&iommu->dev->dev));
1330 * This function clues the initialization function for one IOMMU
1331 * together and also allocates the command buffer and programs the
1332 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1334 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1338 spin_lock_init(&iommu->lock);
1340 /* Add IOMMU to internal data structures */
1341 list_add_tail(&iommu->list, &amd_iommu_list);
1342 iommu->index = amd_iommus_present++;
1344 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1345 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1349 /* Index is fine - add IOMMU to the array */
1350 amd_iommus[iommu->index] = iommu;
1353 * Copy data from ACPI table entry to the iommu struct
1355 iommu->devid = h->devid;
1356 iommu->cap_ptr = h->cap_ptr;
1357 iommu->pci_seg = h->pci_seg;
1358 iommu->mmio_phys = h->mmio_phys;
1362 /* Check if IVHD EFR contains proper max banks/counters */
1363 if ((h->efr_attr != 0) &&
1364 ((h->efr_attr & (0xF << 13)) != 0) &&
1365 ((h->efr_attr & (0x3F << 17)) != 0))
1366 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1368 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1369 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1370 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1374 if (h->efr_reg & (1 << 9))
1375 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1377 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1378 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1379 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1385 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1386 iommu->mmio_phys_end);
1387 if (!iommu->mmio_base)
1390 if (alloc_command_buffer(iommu))
1393 if (alloc_event_buffer(iommu))
1396 iommu->int_enabled = false;
1398 ret = init_iommu_from_acpi(iommu, h);
1402 ret = amd_iommu_create_irq_domain(iommu);
1407 * Make sure IOMMU is not considered to translate itself. The IVRS
1408 * table tells us so, but this is a lie!
1410 amd_iommu_rlookup_table[iommu->devid] = NULL;
1416 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1417 * @ivrs Pointer to the IVRS header
1419 * This function search through all IVDB of the maximum supported IVHD
1421 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1423 u8 *base = (u8 *)ivrs;
1424 struct ivhd_header *ivhd = (struct ivhd_header *)
1425 (base + IVRS_HEADER_LENGTH);
1426 u8 last_type = ivhd->type;
1427 u16 devid = ivhd->devid;
1429 while (((u8 *)ivhd - base < ivrs->length) &&
1430 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1431 u8 *p = (u8 *) ivhd;
1433 if (ivhd->devid == devid)
1434 last_type = ivhd->type;
1435 ivhd = (struct ivhd_header *)(p + ivhd->length);
1442 * Iterates over all IOMMU entries in the ACPI table, allocates the
1443 * IOMMU structure and initializes it with init_iommu_one()
1445 static int __init init_iommu_all(struct acpi_table_header *table)
1447 u8 *p = (u8 *)table, *end = (u8 *)table;
1448 struct ivhd_header *h;
1449 struct amd_iommu *iommu;
1452 end += table->length;
1453 p += IVRS_HEADER_LENGTH;
1456 h = (struct ivhd_header *)p;
1457 if (*p == amd_iommu_target_ivhd_type) {
1459 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1460 "seg: %d flags: %01x info %04x\n",
1461 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1462 PCI_FUNC(h->devid), h->cap_ptr,
1463 h->pci_seg, h->flags, h->info);
1464 DUMP_printk(" mmio-addr: %016llx\n",
1467 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1471 ret = init_iommu_one(iommu, h);
1483 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1484 u8 fxn, u64 *value, bool is_write);
1486 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1488 u64 val = 0xabcd, val2 = 0;
1490 if (!iommu_feature(iommu, FEATURE_PC))
1493 amd_iommu_pc_present = true;
1495 /* Check if the performance counters can be written to */
1496 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1497 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1499 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1500 amd_iommu_pc_present = false;
1504 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1506 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1507 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1508 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1511 static ssize_t amd_iommu_show_cap(struct device *dev,
1512 struct device_attribute *attr,
1515 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1516 return sprintf(buf, "%x\n", iommu->cap);
1518 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1520 static ssize_t amd_iommu_show_features(struct device *dev,
1521 struct device_attribute *attr,
1524 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1525 return sprintf(buf, "%llx\n", iommu->features);
1527 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1529 static struct attribute *amd_iommu_attrs[] = {
1531 &dev_attr_features.attr,
1535 static struct attribute_group amd_iommu_group = {
1536 .name = "amd-iommu",
1537 .attrs = amd_iommu_attrs,
1540 static const struct attribute_group *amd_iommu_groups[] = {
1545 static int iommu_init_pci(struct amd_iommu *iommu)
1547 int cap_ptr = iommu->cap_ptr;
1548 u32 range, misc, low, high;
1551 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1552 iommu->devid & 0xff);
1556 /* Prevent binding other PCI device drivers to IOMMU devices */
1557 iommu->dev->match_driver = false;
1559 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1561 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1563 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1566 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1567 amd_iommu_iotlb_sup = false;
1569 /* read extended feature bits */
1570 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1571 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1573 iommu->features = ((u64)high << 32) | low;
1575 if (iommu_feature(iommu, FEATURE_GT)) {
1580 pasmax = iommu->features & FEATURE_PASID_MASK;
1581 pasmax >>= FEATURE_PASID_SHIFT;
1582 max_pasid = (1 << (pasmax + 1)) - 1;
1584 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1586 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1588 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1589 glxval >>= FEATURE_GLXVAL_SHIFT;
1591 if (amd_iommu_max_glx_val == -1)
1592 amd_iommu_max_glx_val = glxval;
1594 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1597 if (iommu_feature(iommu, FEATURE_GT) &&
1598 iommu_feature(iommu, FEATURE_PPR)) {
1599 iommu->is_iommu_v2 = true;
1600 amd_iommu_v2_present = true;
1603 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1606 ret = iommu_init_ga(iommu);
1610 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1611 amd_iommu_np_cache = true;
1613 init_iommu_perf_ctr(iommu);
1615 if (is_rd890_iommu(iommu->dev)) {
1618 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1622 * Some rd890 systems may not be fully reconfigured by the
1623 * BIOS, so it's necessary for us to store this information so
1624 * it can be reprogrammed on resume
1626 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1627 &iommu->stored_addr_lo);
1628 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1629 &iommu->stored_addr_hi);
1631 /* Low bit locks writes to configuration space */
1632 iommu->stored_addr_lo &= ~1;
1634 for (i = 0; i < 6; i++)
1635 for (j = 0; j < 0x12; j++)
1636 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1638 for (i = 0; i < 0x83; i++)
1639 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1642 amd_iommu_erratum_746_workaround(iommu);
1643 amd_iommu_ats_write_check_workaround(iommu);
1645 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1646 amd_iommu_groups, "ivhd%d", iommu->index);
1647 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1648 iommu_device_register(&iommu->iommu);
1650 return pci_enable_device(iommu->dev);
1653 static void print_iommu_info(void)
1655 static const char * const feat_str[] = {
1656 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1657 "IA", "GA", "HE", "PC"
1659 struct amd_iommu *iommu;
1661 for_each_iommu(iommu) {
1664 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1665 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1667 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1668 pr_info("AMD-Vi: Extended features (%#llx):\n",
1670 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1671 if (iommu_feature(iommu, (1ULL << i)))
1672 pr_cont(" %s", feat_str[i]);
1675 if (iommu->features & FEATURE_GAM_VAPIC)
1676 pr_cont(" GA_vAPIC");
1681 if (irq_remapping_enabled) {
1682 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1683 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1684 pr_info("AMD-Vi: virtual APIC enabled\n");
1688 static int __init amd_iommu_init_pci(void)
1690 struct amd_iommu *iommu;
1693 for_each_iommu(iommu) {
1694 ret = iommu_init_pci(iommu);
1700 * Order is important here to make sure any unity map requirements are
1701 * fulfilled. The unity mappings are created and written to the device
1702 * table during the amd_iommu_init_api() call.
1704 * After that we call init_device_table_dma() to make sure any
1705 * uninitialized DTE will block DMA, and in the end we flush the caches
1706 * of all IOMMUs to make sure the changes to the device table are
1709 ret = amd_iommu_init_api();
1711 init_device_table_dma();
1713 for_each_iommu(iommu)
1714 iommu_flush_all_caches(iommu);
1722 /****************************************************************************
1724 * The following functions initialize the MSI interrupts for all IOMMUs
1725 * in the system. It's a bit challenging because there could be multiple
1726 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1729 ****************************************************************************/
1731 static int iommu_setup_msi(struct amd_iommu *iommu)
1735 r = pci_enable_msi(iommu->dev);
1739 r = request_threaded_irq(iommu->dev->irq,
1740 amd_iommu_int_handler,
1741 amd_iommu_int_thread,
1746 pci_disable_msi(iommu->dev);
1750 iommu->int_enabled = true;
1755 static int iommu_init_msi(struct amd_iommu *iommu)
1759 if (iommu->int_enabled)
1762 if (iommu->dev->msi_cap)
1763 ret = iommu_setup_msi(iommu);
1771 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1773 if (iommu->ppr_log != NULL)
1774 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1776 iommu_ga_log_enable(iommu);
1781 /****************************************************************************
1783 * The next functions belong to the third pass of parsing the ACPI
1784 * table. In this last pass the memory mapping requirements are
1785 * gathered (like exclusion and unity mapping ranges).
1787 ****************************************************************************/
1789 static void __init free_unity_maps(void)
1791 struct unity_map_entry *entry, *next;
1793 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1794 list_del(&entry->list);
1799 /* called when we find an exclusion range definition in ACPI */
1800 static int __init init_exclusion_range(struct ivmd_header *m)
1805 case ACPI_IVMD_TYPE:
1806 set_device_exclusion_range(m->devid, m);
1808 case ACPI_IVMD_TYPE_ALL:
1809 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1810 set_device_exclusion_range(i, m);
1812 case ACPI_IVMD_TYPE_RANGE:
1813 for (i = m->devid; i <= m->aux; ++i)
1814 set_device_exclusion_range(i, m);
1823 /* called for unity map ACPI definition */
1824 static int __init init_unity_map_range(struct ivmd_header *m)
1826 struct unity_map_entry *e = NULL;
1829 e = kzalloc(sizeof(*e), GFP_KERNEL);
1837 case ACPI_IVMD_TYPE:
1838 s = "IVMD_TYPEi\t\t\t";
1839 e->devid_start = e->devid_end = m->devid;
1841 case ACPI_IVMD_TYPE_ALL:
1842 s = "IVMD_TYPE_ALL\t\t";
1844 e->devid_end = amd_iommu_last_bdf;
1846 case ACPI_IVMD_TYPE_RANGE:
1847 s = "IVMD_TYPE_RANGE\t\t";
1848 e->devid_start = m->devid;
1849 e->devid_end = m->aux;
1852 e->address_start = PAGE_ALIGN(m->range_start);
1853 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1854 e->prot = m->flags >> 1;
1856 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1857 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1858 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1859 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1860 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1861 e->address_start, e->address_end, m->flags);
1863 list_add_tail(&e->list, &amd_iommu_unity_map);
1868 /* iterates over all memory definitions we find in the ACPI table */
1869 static int __init init_memory_definitions(struct acpi_table_header *table)
1871 u8 *p = (u8 *)table, *end = (u8 *)table;
1872 struct ivmd_header *m;
1874 end += table->length;
1875 p += IVRS_HEADER_LENGTH;
1878 m = (struct ivmd_header *)p;
1879 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1880 init_exclusion_range(m);
1881 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1882 init_unity_map_range(m);
1891 * Init the device table to not allow DMA access for devices and
1892 * suppress all page faults
1894 static void init_device_table_dma(void)
1898 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1899 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1900 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1904 static void __init uninit_device_table_dma(void)
1908 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1909 amd_iommu_dev_table[devid].data[0] = 0ULL;
1910 amd_iommu_dev_table[devid].data[1] = 0ULL;
1914 static void init_device_table(void)
1918 if (!amd_iommu_irq_remap)
1921 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1922 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1925 static void iommu_init_flags(struct amd_iommu *iommu)
1927 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1928 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1929 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1931 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1932 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1933 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1935 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1936 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1937 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1939 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1940 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1941 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1944 * make IOMMU memory accesses cache coherent
1946 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1948 /* Set IOTLB invalidation timeout to 1s */
1949 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1952 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1955 u32 ioc_feature_control;
1956 struct pci_dev *pdev = iommu->root_pdev;
1958 /* RD890 BIOSes may not have completely reconfigured the iommu */
1959 if (!is_rd890_iommu(iommu->dev) || !pdev)
1963 * First, we need to ensure that the iommu is enabled. This is
1964 * controlled by a register in the northbridge
1967 /* Select Northbridge indirect register 0x75 and enable writing */
1968 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1969 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1971 /* Enable the iommu */
1972 if (!(ioc_feature_control & 0x1))
1973 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1975 /* Restore the iommu BAR */
1976 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1977 iommu->stored_addr_lo);
1978 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1979 iommu->stored_addr_hi);
1981 /* Restore the l1 indirect regs for each of the 6 l1s */
1982 for (i = 0; i < 6; i++)
1983 for (j = 0; j < 0x12; j++)
1984 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1986 /* Restore the l2 indirect regs */
1987 for (i = 0; i < 0x83; i++)
1988 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1990 /* Lock PCI setup registers */
1991 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1992 iommu->stored_addr_lo | 1);
1995 static void iommu_enable_ga(struct amd_iommu *iommu)
1997 #ifdef CONFIG_IRQ_REMAP
1998 switch (amd_iommu_guest_ir) {
1999 case AMD_IOMMU_GUEST_IR_VAPIC:
2000 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2002 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2003 iommu_feature_enable(iommu, CONTROL_GA_EN);
2004 iommu->irte_ops = &irte_128_ops;
2007 iommu->irte_ops = &irte_32_ops;
2014 * This function finally enables all IOMMUs found in the system after
2015 * they have been initialized
2017 static void early_enable_iommus(void)
2019 struct amd_iommu *iommu;
2021 for_each_iommu(iommu) {
2022 iommu_disable(iommu);
2023 iommu_init_flags(iommu);
2024 iommu_set_device_table(iommu);
2025 iommu_enable_command_buffer(iommu);
2026 iommu_enable_event_buffer(iommu);
2027 iommu_set_exclusion_range(iommu);
2028 iommu_enable_ga(iommu);
2029 iommu_enable(iommu);
2030 iommu_flush_all_caches(iommu);
2033 #ifdef CONFIG_IRQ_REMAP
2034 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2035 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2039 static void enable_iommus_v2(void)
2041 struct amd_iommu *iommu;
2043 for_each_iommu(iommu) {
2044 iommu_enable_ppr_log(iommu);
2045 iommu_enable_gt(iommu);
2049 static void enable_iommus(void)
2051 early_enable_iommus();
2056 static void disable_iommus(void)
2058 struct amd_iommu *iommu;
2060 for_each_iommu(iommu)
2061 iommu_disable(iommu);
2063 #ifdef CONFIG_IRQ_REMAP
2064 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2065 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2070 * Suspend/Resume support
2071 * disable suspend until real resume implemented
2074 static void amd_iommu_resume(void)
2076 struct amd_iommu *iommu;
2078 for_each_iommu(iommu)
2079 iommu_apply_resume_quirks(iommu);
2081 /* re-load the hardware */
2084 amd_iommu_enable_interrupts();
2087 static int amd_iommu_suspend(void)
2089 /* disable IOMMUs to go out of the way for BIOS */
2095 static struct syscore_ops amd_iommu_syscore_ops = {
2096 .suspend = amd_iommu_suspend,
2097 .resume = amd_iommu_resume,
2100 static void __init free_on_init_error(void)
2102 kmemleak_free(irq_lookup_table);
2103 free_pages((unsigned long)irq_lookup_table,
2104 get_order(rlookup_table_size));
2106 kmem_cache_destroy(amd_iommu_irq_cache);
2107 amd_iommu_irq_cache = NULL;
2109 free_pages((unsigned long)amd_iommu_rlookup_table,
2110 get_order(rlookup_table_size));
2112 free_pages((unsigned long)amd_iommu_alias_table,
2113 get_order(alias_table_size));
2115 free_pages((unsigned long)amd_iommu_dev_table,
2116 get_order(dev_table_size));
2120 #ifdef CONFIG_GART_IOMMU
2122 * We failed to initialize the AMD IOMMU - try fallback to GART
2130 /* SB IOAPIC is always on this device in AMD systems */
2131 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2133 static bool __init check_ioapic_information(void)
2135 const char *fw_bug = FW_BUG;
2136 bool ret, has_sb_ioapic;
2139 has_sb_ioapic = false;
2143 * If we have map overrides on the kernel command line the
2144 * messages in this function might not describe firmware bugs
2145 * anymore - so be careful
2150 for (idx = 0; idx < nr_ioapics; idx++) {
2151 int devid, id = mpc_ioapic_id(idx);
2153 devid = get_ioapic_devid(id);
2155 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2158 } else if (devid == IOAPIC_SB_DEVID) {
2159 has_sb_ioapic = true;
2164 if (!has_sb_ioapic) {
2166 * We expect the SB IOAPIC to be listed in the IVRS
2167 * table. The system timer is connected to the SB IOAPIC
2168 * and if we don't have it in the list the system will
2169 * panic at boot time. This situation usually happens
2170 * when the BIOS is buggy and provides us the wrong
2171 * device id for the IOAPIC in the system.
2173 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2177 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2182 static void __init free_dma_resources(void)
2184 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2185 get_order(MAX_DOMAIN_ID/8));
2191 * This is the hardware init function for AMD IOMMU in the system.
2192 * This function is called either from amd_iommu_init or from the interrupt
2193 * remapping setup code.
2195 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2198 * 1 pass) Discover the most comprehensive IVHD type to use.
2200 * 2 pass) Find the highest PCI device id the driver has to handle.
2201 * Upon this information the size of the data structures is
2202 * determined that needs to be allocated.
2204 * 3 pass) Initialize the data structures just allocated with the
2205 * information in the ACPI table about available AMD IOMMUs
2206 * in the system. It also maps the PCI devices in the
2207 * system to specific IOMMUs
2209 * 4 pass) After the basic data structures are allocated and
2210 * initialized we update them with information about memory
2211 * remapping requirements parsed out of the ACPI table in
2214 * After everything is set up the IOMMUs are enabled and the necessary
2215 * hotplug and suspend notifiers are registered.
2217 static int __init early_amd_iommu_init(void)
2219 struct acpi_table_header *ivrs_base;
2221 int i, remap_cache_sz, ret = 0;
2223 if (!amd_iommu_detected)
2226 status = acpi_get_table("IVRS", 0, &ivrs_base);
2227 if (status == AE_NOT_FOUND)
2229 else if (ACPI_FAILURE(status)) {
2230 const char *err = acpi_format_exception(status);
2231 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2236 * Validate checksum here so we don't need to do it when
2237 * we actually parse the table
2239 ret = check_ivrs_checksum(ivrs_base);
2243 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2244 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2247 * First parse ACPI tables to find the largest Bus/Dev/Func
2248 * we need to handle. Upon this information the shared data
2249 * structures for the IOMMUs in the system will be allocated
2251 ret = find_last_devid_acpi(ivrs_base);
2255 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2256 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2257 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2259 /* Device table - directly used by all IOMMUs */
2261 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2262 get_order(dev_table_size));
2263 if (amd_iommu_dev_table == NULL)
2267 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2268 * IOMMU see for that device
2270 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2271 get_order(alias_table_size));
2272 if (amd_iommu_alias_table == NULL)
2275 /* IOMMU rlookup table - find the IOMMU for a specific device */
2276 amd_iommu_rlookup_table = (void *)__get_free_pages(
2277 GFP_KERNEL | __GFP_ZERO,
2278 get_order(rlookup_table_size));
2279 if (amd_iommu_rlookup_table == NULL)
2282 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2283 GFP_KERNEL | __GFP_ZERO,
2284 get_order(MAX_DOMAIN_ID/8));
2285 if (amd_iommu_pd_alloc_bitmap == NULL)
2289 * let all alias entries point to itself
2291 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2292 amd_iommu_alias_table[i] = i;
2295 * never allocate domain 0 because its used as the non-allocated and
2296 * error value placeholder
2298 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2300 spin_lock_init(&amd_iommu_pd_lock);
2303 * now the data structures are allocated and basically initialized
2304 * start the real acpi table scan
2306 ret = init_iommu_all(ivrs_base);
2310 if (amd_iommu_irq_remap)
2311 amd_iommu_irq_remap = check_ioapic_information();
2313 if (amd_iommu_irq_remap) {
2315 * Interrupt remapping enabled, create kmem_cache for the
2319 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2320 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2322 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2323 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2325 IRQ_TABLE_ALIGNMENT,
2327 if (!amd_iommu_irq_cache)
2330 irq_lookup_table = (void *)__get_free_pages(
2331 GFP_KERNEL | __GFP_ZERO,
2332 get_order(rlookup_table_size));
2333 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2335 if (!irq_lookup_table)
2339 ret = init_memory_definitions(ivrs_base);
2343 /* init the device table */
2344 init_device_table();
2347 /* Don't leak any ACPI memory */
2348 acpi_put_table(ivrs_base);
2354 static int amd_iommu_enable_interrupts(void)
2356 struct amd_iommu *iommu;
2359 for_each_iommu(iommu) {
2360 ret = iommu_init_msi(iommu);
2369 static bool detect_ivrs(void)
2371 struct acpi_table_header *ivrs_base;
2374 status = acpi_get_table("IVRS", 0, &ivrs_base);
2375 if (status == AE_NOT_FOUND)
2377 else if (ACPI_FAILURE(status)) {
2378 const char *err = acpi_format_exception(status);
2379 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2383 acpi_put_table(ivrs_base);
2385 /* Make sure ACS will be enabled during PCI probe */
2391 /****************************************************************************
2393 * AMD IOMMU Initialization State Machine
2395 ****************************************************************************/
2397 static int __init state_next(void)
2401 switch (init_state) {
2402 case IOMMU_START_STATE:
2403 if (!detect_ivrs()) {
2404 init_state = IOMMU_NOT_FOUND;
2407 init_state = IOMMU_IVRS_DETECTED;
2410 case IOMMU_IVRS_DETECTED:
2411 ret = early_amd_iommu_init();
2412 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2414 case IOMMU_ACPI_FINISHED:
2415 early_enable_iommus();
2416 register_syscore_ops(&amd_iommu_syscore_ops);
2417 x86_platform.iommu_shutdown = disable_iommus;
2418 init_state = IOMMU_ENABLED;
2421 ret = amd_iommu_init_pci();
2422 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2425 case IOMMU_PCI_INIT:
2426 ret = amd_iommu_enable_interrupts();
2427 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2429 case IOMMU_INTERRUPTS_EN:
2430 ret = amd_iommu_init_dma_ops();
2431 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2434 init_state = IOMMU_INITIALIZED;
2436 case IOMMU_INITIALIZED:
2439 case IOMMU_NOT_FOUND:
2440 case IOMMU_INIT_ERROR:
2441 /* Error states => do nothing */
2452 static int __init iommu_go_to_state(enum iommu_init_state state)
2456 while (init_state != state) {
2458 if (init_state == IOMMU_NOT_FOUND ||
2459 init_state == IOMMU_INIT_ERROR)
2466 #ifdef CONFIG_IRQ_REMAP
2467 int __init amd_iommu_prepare(void)
2471 amd_iommu_irq_remap = true;
2473 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2476 return amd_iommu_irq_remap ? 0 : -ENODEV;
2479 int __init amd_iommu_enable(void)
2483 ret = iommu_go_to_state(IOMMU_ENABLED);
2487 irq_remapping_enabled = 1;
2492 void amd_iommu_disable(void)
2494 amd_iommu_suspend();
2497 int amd_iommu_reenable(int mode)
2504 int __init amd_iommu_enable_faulting(void)
2506 /* We enable MSI later when PCI is initialized */
2512 * This is the core init function for AMD IOMMU hardware in the system.
2513 * This function is called from the generic x86 DMA layer initialization
2516 static int __init amd_iommu_init(void)
2520 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2522 free_dma_resources();
2523 if (!irq_remapping_enabled) {
2525 free_on_init_error();
2527 struct amd_iommu *iommu;
2529 uninit_device_table_dma();
2530 for_each_iommu(iommu)
2531 iommu_flush_all_caches(iommu);
2538 /****************************************************************************
2540 * Early detect code. This code runs at IOMMU detection time in the DMA
2541 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2544 ****************************************************************************/
2545 int __init amd_iommu_detect(void)
2549 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2552 if (amd_iommu_disabled)
2555 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2559 amd_iommu_detected = true;
2561 x86_init.iommu.iommu_init = amd_iommu_init;
2566 /****************************************************************************
2568 * Parsing functions for the AMD IOMMU specific kernel command line
2571 ****************************************************************************/
2573 static int __init parse_amd_iommu_dump(char *str)
2575 amd_iommu_dump = true;
2580 static int __init parse_amd_iommu_intr(char *str)
2582 for (; *str; ++str) {
2583 if (strncmp(str, "legacy", 6) == 0) {
2584 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2587 if (strncmp(str, "vapic", 5) == 0) {
2588 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2595 static int __init parse_amd_iommu_options(char *str)
2597 for (; *str; ++str) {
2598 if (strncmp(str, "fullflush", 9) == 0)
2599 amd_iommu_unmap_flush = true;
2600 if (strncmp(str, "off", 3) == 0)
2601 amd_iommu_disabled = true;
2602 if (strncmp(str, "force_isolation", 15) == 0)
2603 amd_iommu_force_isolation = true;
2609 static int __init parse_ivrs_ioapic(char *str)
2611 unsigned int bus, dev, fn;
2615 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2618 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2622 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2623 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2628 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2630 cmdline_maps = true;
2631 i = early_ioapic_map_size++;
2632 early_ioapic_map[i].id = id;
2633 early_ioapic_map[i].devid = devid;
2634 early_ioapic_map[i].cmd_line = true;
2639 static int __init parse_ivrs_hpet(char *str)
2641 unsigned int bus, dev, fn;
2645 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2648 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2652 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2653 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2658 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2660 cmdline_maps = true;
2661 i = early_hpet_map_size++;
2662 early_hpet_map[i].id = id;
2663 early_hpet_map[i].devid = devid;
2664 early_hpet_map[i].cmd_line = true;
2669 static int __init parse_ivrs_acpihid(char *str)
2672 char *hid, *uid, *p;
2673 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2676 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2678 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2683 hid = strsep(&p, ":");
2686 if (!hid || !(*hid) || !uid) {
2687 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2691 i = early_acpihid_map_size++;
2692 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2693 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2694 early_acpihid_map[i].devid =
2695 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2696 early_acpihid_map[i].cmd_line = true;
2701 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2702 __setup("amd_iommu=", parse_amd_iommu_options);
2703 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2704 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2705 __setup("ivrs_hpet", parse_ivrs_hpet);
2706 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2708 IOMMU_INIT_FINISH(amd_iommu_detect,
2709 gart_iommu_hole_init,
2713 bool amd_iommu_v2_supported(void)
2715 return amd_iommu_v2_present;
2717 EXPORT_SYMBOL(amd_iommu_v2_supported);
2719 struct amd_iommu *get_amd_iommu(unsigned int idx)
2722 struct amd_iommu *iommu;
2724 for_each_iommu(iommu)
2729 EXPORT_SYMBOL(get_amd_iommu);
2731 /****************************************************************************
2733 * IOMMU EFR Performance Counter support functionality. This code allows
2734 * access to the IOMMU PC functionality.
2736 ****************************************************************************/
2738 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2740 struct amd_iommu *iommu = get_amd_iommu(idx);
2743 return iommu->max_banks;
2747 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2749 bool amd_iommu_pc_supported(void)
2751 return amd_iommu_pc_present;
2753 EXPORT_SYMBOL(amd_iommu_pc_supported);
2755 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
2757 struct amd_iommu *iommu = get_amd_iommu(idx);
2760 return iommu->max_counters;
2764 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2766 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2767 u8 fxn, u64 *value, bool is_write)
2772 /* Make sure the IOMMU PC resource is available */
2773 if (!amd_iommu_pc_present)
2776 /* Check for valid iommu and pc register indexing */
2777 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
2780 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
2782 /* Limit the offset to the hw defined mmio region aperture */
2783 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
2784 (iommu->max_counters << 8) | 0x28);
2785 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2786 (offset > max_offset_lim))
2790 u64 val = *value & GENMASK_ULL(47, 0);
2792 writel((u32)val, iommu->mmio_base + offset);
2793 writel((val >> 32), iommu->mmio_base + offset + 4);
2795 *value = readl(iommu->mmio_base + offset + 4);
2797 *value |= readl(iommu->mmio_base + offset);
2798 *value &= GENMASK_ULL(47, 0);
2804 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2809 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
2811 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
2813 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2818 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
2820 EXPORT_SYMBOL(amd_iommu_pc_set_reg);