2 * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/amd-iommu.h>
20 #include <linux/mm_types.h>
21 #include <linux/module.h>
22 #include <linux/sched.h>
23 #include <linux/iommu.h>
24 #include <linux/wait.h>
25 #include <linux/pci.h>
26 #include <linux/gfp.h>
28 #include "amd_iommu_types.h"
29 #include "amd_iommu_proto.h"
31 MODULE_LICENSE("GPL v2");
32 MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>");
34 #define MAX_DEVICES 0x10000
35 #define PRI_QUEUE_SIZE 512
44 struct list_head list; /* For global state-list */
45 atomic_t count; /* Reference count */
46 struct task_struct *task; /* Task bound to this PASID */
47 struct mm_struct *mm; /* mm_struct for the faults */
48 struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */
49 struct device_state *device_state; /* Link to our device_state */
50 int pasid; /* PASID index */
51 spinlock_t lock; /* Protect pri_queues */
52 wait_queue_head_t wq; /* To wait for count == 0 */
58 struct pasid_state **states;
59 struct iommu_domain *domain;
67 struct work_struct work;
68 struct device_state *dev_state;
69 struct pasid_state *state;
79 struct device_state **state_table;
80 static spinlock_t state_lock;
82 /* List and lock for all pasid_states */
83 static LIST_HEAD(pasid_state_list);
84 static DEFINE_SPINLOCK(ps_lock);
86 static struct workqueue_struct *iommu_wq;
88 static void free_pasid_states(struct device_state *dev_state);
89 static void unbind_pasid(struct device_state *dev_state, int pasid);
91 static u16 device_id(struct pci_dev *pdev)
95 devid = pdev->bus->number;
96 devid = (devid << 8) | pdev->devfn;
101 static struct device_state *get_device_state(u16 devid)
103 struct device_state *dev_state;
106 spin_lock_irqsave(&state_lock, flags);
107 dev_state = state_table[devid];
108 if (dev_state != NULL)
109 atomic_inc(&dev_state->count);
110 spin_unlock_irqrestore(&state_lock, flags);
115 static void free_device_state(struct device_state *dev_state)
118 * First detach device from domain - No more PRI requests will arrive
119 * from that device after it is unbound from the IOMMUv2 domain.
121 iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
123 /* Everything is down now, free the IOMMUv2 domain */
124 iommu_domain_free(dev_state->domain);
126 /* Finally get rid of the device-state */
130 static void put_device_state(struct device_state *dev_state)
132 if (atomic_dec_and_test(&dev_state->count))
133 wake_up(&dev_state->wq);
136 static void put_device_state_wait(struct device_state *dev_state)
140 prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE);
141 if (!atomic_dec_and_test(&dev_state->count))
143 finish_wait(&dev_state->wq, &wait);
145 free_device_state(dev_state);
147 static void link_pasid_state(struct pasid_state *pasid_state)
150 list_add_tail(&pasid_state->list, &pasid_state_list);
151 spin_unlock(&ps_lock);
154 static void __unlink_pasid_state(struct pasid_state *pasid_state)
156 list_del(&pasid_state->list);
159 static void unlink_pasid_state(struct pasid_state *pasid_state)
162 __unlink_pasid_state(pasid_state);
163 spin_unlock(&ps_lock);
166 /* Must be called under dev_state->lock */
167 static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
168 int pasid, bool alloc)
170 struct pasid_state **root, **ptr;
173 level = dev_state->pasid_levels;
174 root = dev_state->states;
178 index = (pasid >> (9 * level)) & 0x1ff;
188 *ptr = (void *)get_zeroed_page(GFP_ATOMIC);
193 root = (struct pasid_state **)*ptr;
200 static int set_pasid_state(struct device_state *dev_state,
201 struct pasid_state *pasid_state,
204 struct pasid_state **ptr;
208 spin_lock_irqsave(&dev_state->lock, flags);
209 ptr = __get_pasid_state_ptr(dev_state, pasid, true);
224 spin_unlock_irqrestore(&dev_state->lock, flags);
229 static void clear_pasid_state(struct device_state *dev_state, int pasid)
231 struct pasid_state **ptr;
234 spin_lock_irqsave(&dev_state->lock, flags);
235 ptr = __get_pasid_state_ptr(dev_state, pasid, true);
243 spin_unlock_irqrestore(&dev_state->lock, flags);
246 static struct pasid_state *get_pasid_state(struct device_state *dev_state,
249 struct pasid_state **ptr, *ret = NULL;
252 spin_lock_irqsave(&dev_state->lock, flags);
253 ptr = __get_pasid_state_ptr(dev_state, pasid, false);
260 atomic_inc(&ret->count);
263 spin_unlock_irqrestore(&dev_state->lock, flags);
268 static void free_pasid_state(struct pasid_state *pasid_state)
273 static void put_pasid_state(struct pasid_state *pasid_state)
275 if (atomic_dec_and_test(&pasid_state->count)) {
276 put_device_state(pasid_state->device_state);
277 wake_up(&pasid_state->wq);
281 static void put_pasid_state_wait(struct pasid_state *pasid_state)
285 prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE);
287 if (atomic_dec_and_test(&pasid_state->count))
288 put_device_state(pasid_state->device_state);
292 finish_wait(&pasid_state->wq, &wait);
293 mmput(pasid_state->mm);
294 free_pasid_state(pasid_state);
297 static void unbind_pasid(struct device_state *dev_state, int pasid)
299 struct pasid_state *pasid_state;
301 pasid_state = get_pasid_state(dev_state, pasid);
302 if (pasid_state == NULL)
305 unlink_pasid_state(pasid_state);
307 amd_iommu_domain_clear_gcr3(dev_state->domain, pasid);
308 clear_pasid_state(dev_state, pasid);
310 put_pasid_state(pasid_state); /* Reference taken in this function */
311 put_pasid_state_wait(pasid_state); /* Reference from bind() function */
314 static void free_pasid_states_level1(struct pasid_state **tbl)
318 for (i = 0; i < 512; ++i) {
322 free_page((unsigned long)tbl[i]);
326 static void free_pasid_states_level2(struct pasid_state **tbl)
328 struct pasid_state **ptr;
331 for (i = 0; i < 512; ++i) {
335 ptr = (struct pasid_state **)tbl[i];
336 free_pasid_states_level1(ptr);
340 static void free_pasid_states(struct device_state *dev_state)
342 struct pasid_state *pasid_state;
345 for (i = 0; i < dev_state->max_pasids; ++i) {
346 pasid_state = get_pasid_state(dev_state, i);
347 if (pasid_state == NULL)
350 put_pasid_state(pasid_state);
351 unbind_pasid(dev_state, i);
354 if (dev_state->pasid_levels == 2)
355 free_pasid_states_level2(dev_state->states);
356 else if (dev_state->pasid_levels == 1)
357 free_pasid_states_level1(dev_state->states);
358 else if (dev_state->pasid_levels != 0)
361 free_page((unsigned long)dev_state->states);
364 static void set_pri_tag_status(struct pasid_state *pasid_state,
369 spin_lock_irqsave(&pasid_state->lock, flags);
370 pasid_state->pri[tag].status = status;
371 spin_unlock_irqrestore(&pasid_state->lock, flags);
374 static void finish_pri_tag(struct device_state *dev_state,
375 struct pasid_state *pasid_state,
380 spin_lock_irqsave(&pasid_state->lock, flags);
381 if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
382 pasid_state->pri[tag].finish) {
383 amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
384 pasid_state->pri[tag].status, tag);
385 pasid_state->pri[tag].finish = false;
386 pasid_state->pri[tag].status = PPR_SUCCESS;
388 spin_unlock_irqrestore(&pasid_state->lock, flags);
391 static void do_fault(struct work_struct *work)
393 struct fault *fault = container_of(work, struct fault, work);
397 write = !!(fault->flags & PPR_FAULT_WRITE);
399 npages = get_user_pages(fault->state->task, fault->state->mm,
400 fault->address, 1, write, 0, &page, NULL);
405 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
407 finish_pri_tag(fault->dev_state, fault->state, fault->tag);
409 put_pasid_state(fault->state);
414 static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
416 struct amd_iommu_fault *iommu_fault;
417 struct pasid_state *pasid_state;
418 struct device_state *dev_state;
426 tag = iommu_fault->tag & 0x1ff;
427 finish = (iommu_fault->tag >> 9) & 1;
430 dev_state = get_device_state(iommu_fault->device_id);
431 if (dev_state == NULL)
434 pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
435 if (pasid_state == NULL) {
436 /* We know the device but not the PASID -> send INVALID */
437 amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
442 spin_lock_irqsave(&pasid_state->lock, flags);
443 atomic_inc(&pasid_state->pri[tag].inflight);
445 pasid_state->pri[tag].finish = true;
446 spin_unlock_irqrestore(&pasid_state->lock, flags);
448 fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
450 /* We are OOM - send success and let the device re-fault */
451 finish_pri_tag(dev_state, pasid_state, tag);
455 fault->dev_state = dev_state;
456 fault->address = iommu_fault->address;
457 fault->state = pasid_state;
459 fault->finish = finish;
460 fault->flags = iommu_fault->flags;
461 INIT_WORK(&fault->work, do_fault);
463 queue_work(iommu_wq, &fault->work);
468 put_device_state(dev_state);
474 static struct notifier_block ppr_nb = {
475 .notifier_call = ppr_notifier,
478 int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
479 struct task_struct *task)
481 struct pasid_state *pasid_state;
482 struct device_state *dev_state;
488 if (!amd_iommu_v2_supported())
491 devid = device_id(pdev);
492 dev_state = get_device_state(devid);
494 if (dev_state == NULL)
498 if (pasid < 0 || pasid >= dev_state->max_pasids)
502 pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
503 if (pasid_state == NULL)
506 atomic_set(&pasid_state->count, 1);
507 init_waitqueue_head(&pasid_state->wq);
508 pasid_state->task = task;
509 pasid_state->mm = get_task_mm(task);
510 pasid_state->device_state = dev_state;
511 pasid_state->pasid = pasid;
513 if (pasid_state->mm == NULL)
516 ret = set_pasid_state(dev_state, pasid_state, pasid);
520 ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
521 __pa(pasid_state->mm->pgd));
523 goto out_clear_state;
525 link_pasid_state(pasid_state);
530 clear_pasid_state(dev_state, pasid);
533 free_pasid_state(pasid_state);
536 put_device_state(dev_state);
540 EXPORT_SYMBOL(amd_iommu_bind_pasid);
542 void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
544 struct device_state *dev_state;
549 if (!amd_iommu_v2_supported())
552 devid = device_id(pdev);
553 dev_state = get_device_state(devid);
554 if (dev_state == NULL)
557 if (pasid < 0 || pasid >= dev_state->max_pasids)
560 unbind_pasid(dev_state, pasid);
563 put_device_state(dev_state);
565 EXPORT_SYMBOL(amd_iommu_unbind_pasid);
567 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
569 struct device_state *dev_state;
576 if (!amd_iommu_v2_supported())
579 if (pasids <= 0 || pasids > (PASID_MASK + 1))
582 devid = device_id(pdev);
584 dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
585 if (dev_state == NULL)
588 spin_lock_init(&dev_state->lock);
589 init_waitqueue_head(&dev_state->wq);
590 dev_state->pdev = pdev;
593 for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
594 dev_state->pasid_levels += 1;
596 atomic_set(&dev_state->count, 1);
597 dev_state->max_pasids = pasids;
600 dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
601 if (dev_state->states == NULL)
602 goto out_free_dev_state;
604 dev_state->domain = iommu_domain_alloc(&pci_bus_type);
605 if (dev_state->domain == NULL)
606 goto out_free_states;
608 amd_iommu_domain_direct_map(dev_state->domain);
610 ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
612 goto out_free_domain;
614 ret = iommu_attach_device(dev_state->domain, &pdev->dev);
616 goto out_free_domain;
618 spin_lock_irqsave(&state_lock, flags);
620 if (state_table[devid] != NULL) {
621 spin_unlock_irqrestore(&state_lock, flags);
623 goto out_free_domain;
626 state_table[devid] = dev_state;
628 spin_unlock_irqrestore(&state_lock, flags);
633 iommu_domain_free(dev_state->domain);
636 free_page((unsigned long)dev_state->states);
643 EXPORT_SYMBOL(amd_iommu_init_device);
645 void amd_iommu_free_device(struct pci_dev *pdev)
647 struct device_state *dev_state;
651 if (!amd_iommu_v2_supported())
654 devid = device_id(pdev);
656 spin_lock_irqsave(&state_lock, flags);
658 dev_state = state_table[devid];
659 if (dev_state == NULL) {
660 spin_unlock_irqrestore(&state_lock, flags);
664 state_table[devid] = NULL;
666 spin_unlock_irqrestore(&state_lock, flags);
668 /* Get rid of any remaining pasid states */
669 free_pasid_states(dev_state);
671 put_device_state_wait(dev_state);
673 EXPORT_SYMBOL(amd_iommu_free_device);
675 static int __init amd_iommu_v2_init(void)
677 size_t state_table_size;
680 pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>");
682 spin_lock_init(&state_lock);
684 state_table_size = MAX_DEVICES * sizeof(struct device_state *);
685 state_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
686 get_order(state_table_size));
687 if (state_table == NULL)
691 iommu_wq = create_workqueue("amd_iommu_v2");
692 if (iommu_wq == NULL) {
697 amd_iommu_register_ppr_notifier(&ppr_nb);
702 free_pages((unsigned long)state_table, get_order(state_table_size));
707 static void __exit amd_iommu_v2_exit(void)
709 struct device_state *dev_state;
710 size_t state_table_size;
713 amd_iommu_unregister_ppr_notifier(&ppr_nb);
715 flush_workqueue(iommu_wq);
718 * The loop below might call flush_workqueue(), so call
719 * destroy_workqueue() after it
721 for (i = 0; i < MAX_DEVICES; ++i) {
722 dev_state = get_device_state(i);
724 if (dev_state == NULL)
729 put_device_state(dev_state);
730 amd_iommu_free_device(dev_state->pdev);
733 destroy_workqueue(iommu_wq);
735 state_table_size = MAX_DEVICES * sizeof(struct device_state *);
736 free_pages((unsigned long)state_table, get_order(state_table_size));
739 module_init(amd_iommu_v2_init);
740 module_exit(amd_iommu_v2_exit);