2 * IOMMU API for ARM architected SMMU implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * Copyright (C) 2013 ARM Limited
19 * Author: Will Deacon <will.deacon@arm.com>
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 42-bit addressing (dependent on VA_BITS)
28 * - Context fault reporting
31 #define pr_fmt(fmt) "arm-smmu: " fmt
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
38 #include <linux/iommu.h>
40 #include <linux/module.h>
42 #include <linux/pci.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
47 #include <linux/amba/bus.h>
49 #include <asm/pgalloc.h>
51 /* Maximum number of stream IDs assigned to a single device */
52 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
54 /* Maximum number of context banks per SMMU */
55 #define ARM_SMMU_MAX_CBS 128
57 /* Maximum number of mapping groups per SMMU */
58 #define ARM_SMMU_MAX_SMRS 128
60 /* SMMU global address space */
61 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
62 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
65 * SMMU global address space with conditional offset to access secure
66 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
69 #define ARM_SMMU_GR0_NS(smmu) \
71 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
75 #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
76 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
77 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
78 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
79 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
80 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
81 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
83 #if PAGE_SIZE == SZ_4K
84 #define ARM_SMMU_PTE_CONT_ENTRIES 16
85 #elif PAGE_SIZE == SZ_64K
86 #define ARM_SMMU_PTE_CONT_ENTRIES 32
88 #define ARM_SMMU_PTE_CONT_ENTRIES 1
91 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
92 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
95 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
96 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
98 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
101 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
102 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
103 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
104 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
105 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
106 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
108 /* Configuration registers */
109 #define ARM_SMMU_GR0_sCR0 0x0
110 #define sCR0_CLIENTPD (1 << 0)
111 #define sCR0_GFRE (1 << 1)
112 #define sCR0_GFIE (1 << 2)
113 #define sCR0_GCFGFRE (1 << 4)
114 #define sCR0_GCFGFIE (1 << 5)
115 #define sCR0_USFCFG (1 << 10)
116 #define sCR0_VMIDPNE (1 << 11)
117 #define sCR0_PTM (1 << 12)
118 #define sCR0_FB (1 << 13)
119 #define sCR0_BSU_SHIFT 14
120 #define sCR0_BSU_MASK 0x3
122 /* Identification registers */
123 #define ARM_SMMU_GR0_ID0 0x20
124 #define ARM_SMMU_GR0_ID1 0x24
125 #define ARM_SMMU_GR0_ID2 0x28
126 #define ARM_SMMU_GR0_ID3 0x2c
127 #define ARM_SMMU_GR0_ID4 0x30
128 #define ARM_SMMU_GR0_ID5 0x34
129 #define ARM_SMMU_GR0_ID6 0x38
130 #define ARM_SMMU_GR0_ID7 0x3c
131 #define ARM_SMMU_GR0_sGFSR 0x48
132 #define ARM_SMMU_GR0_sGFSYNR0 0x50
133 #define ARM_SMMU_GR0_sGFSYNR1 0x54
134 #define ARM_SMMU_GR0_sGFSYNR2 0x58
135 #define ARM_SMMU_GR0_PIDR0 0xfe0
136 #define ARM_SMMU_GR0_PIDR1 0xfe4
137 #define ARM_SMMU_GR0_PIDR2 0xfe8
139 #define ID0_S1TS (1 << 30)
140 #define ID0_S2TS (1 << 29)
141 #define ID0_NTS (1 << 28)
142 #define ID0_SMS (1 << 27)
143 #define ID0_PTFS_SHIFT 24
144 #define ID0_PTFS_MASK 0x2
145 #define ID0_PTFS_V8_ONLY 0x2
146 #define ID0_CTTW (1 << 14)
147 #define ID0_NUMIRPT_SHIFT 16
148 #define ID0_NUMIRPT_MASK 0xff
149 #define ID0_NUMSMRG_SHIFT 0
150 #define ID0_NUMSMRG_MASK 0xff
152 #define ID1_PAGESIZE (1 << 31)
153 #define ID1_NUMPAGENDXB_SHIFT 28
154 #define ID1_NUMPAGENDXB_MASK 7
155 #define ID1_NUMS2CB_SHIFT 16
156 #define ID1_NUMS2CB_MASK 0xff
157 #define ID1_NUMCB_SHIFT 0
158 #define ID1_NUMCB_MASK 0xff
160 #define ID2_OAS_SHIFT 4
161 #define ID2_OAS_MASK 0xf
162 #define ID2_IAS_SHIFT 0
163 #define ID2_IAS_MASK 0xf
164 #define ID2_UBS_SHIFT 8
165 #define ID2_UBS_MASK 0xf
166 #define ID2_PTFS_4K (1 << 12)
167 #define ID2_PTFS_16K (1 << 13)
168 #define ID2_PTFS_64K (1 << 14)
170 #define PIDR2_ARCH_SHIFT 4
171 #define PIDR2_ARCH_MASK 0xf
173 /* Global TLB invalidation */
174 #define ARM_SMMU_GR0_STLBIALL 0x60
175 #define ARM_SMMU_GR0_TLBIVMID 0x64
176 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
177 #define ARM_SMMU_GR0_TLBIALLH 0x6c
178 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
179 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
180 #define sTLBGSTATUS_GSACTIVE (1 << 0)
181 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
183 /* Stream mapping registers */
184 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
185 #define SMR_VALID (1 << 31)
186 #define SMR_MASK_SHIFT 16
187 #define SMR_MASK_MASK 0x7fff
188 #define SMR_ID_SHIFT 0
189 #define SMR_ID_MASK 0x7fff
191 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
192 #define S2CR_CBNDX_SHIFT 0
193 #define S2CR_CBNDX_MASK 0xff
194 #define S2CR_TYPE_SHIFT 16
195 #define S2CR_TYPE_MASK 0x3
196 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
197 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
198 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
200 /* Context bank attribute registers */
201 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
202 #define CBAR_VMID_SHIFT 0
203 #define CBAR_VMID_MASK 0xff
204 #define CBAR_S1_BPSHCFG_SHIFT 8
205 #define CBAR_S1_BPSHCFG_MASK 3
206 #define CBAR_S1_BPSHCFG_NSH 3
207 #define CBAR_S1_MEMATTR_SHIFT 12
208 #define CBAR_S1_MEMATTR_MASK 0xf
209 #define CBAR_S1_MEMATTR_WB 0xf
210 #define CBAR_TYPE_SHIFT 16
211 #define CBAR_TYPE_MASK 0x3
212 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
213 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
214 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
215 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
216 #define CBAR_IRPTNDX_SHIFT 24
217 #define CBAR_IRPTNDX_MASK 0xff
219 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
220 #define CBA2R_RW64_32BIT (0 << 0)
221 #define CBA2R_RW64_64BIT (1 << 0)
223 /* Translation context bank */
224 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
225 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
227 #define ARM_SMMU_CB_SCTLR 0x0
228 #define ARM_SMMU_CB_RESUME 0x8
229 #define ARM_SMMU_CB_TTBCR2 0x10
230 #define ARM_SMMU_CB_TTBR0_LO 0x20
231 #define ARM_SMMU_CB_TTBR0_HI 0x24
232 #define ARM_SMMU_CB_TTBCR 0x30
233 #define ARM_SMMU_CB_S1_MAIR0 0x38
234 #define ARM_SMMU_CB_FSR 0x58
235 #define ARM_SMMU_CB_FAR_LO 0x60
236 #define ARM_SMMU_CB_FAR_HI 0x64
237 #define ARM_SMMU_CB_FSYNR0 0x68
238 #define ARM_SMMU_CB_S1_TLBIASID 0x610
240 #define SCTLR_S1_ASIDPNE (1 << 12)
241 #define SCTLR_CFCFG (1 << 7)
242 #define SCTLR_CFIE (1 << 6)
243 #define SCTLR_CFRE (1 << 5)
244 #define SCTLR_E (1 << 4)
245 #define SCTLR_AFE (1 << 2)
246 #define SCTLR_TRE (1 << 1)
247 #define SCTLR_M (1 << 0)
248 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
250 #define RESUME_RETRY (0 << 0)
251 #define RESUME_TERMINATE (1 << 0)
253 #define TTBCR_EAE (1 << 31)
255 #define TTBCR_PASIZE_SHIFT 16
256 #define TTBCR_PASIZE_MASK 0x7
258 #define TTBCR_TG0_4K (0 << 14)
259 #define TTBCR_TG0_64K (1 << 14)
261 #define TTBCR_SH0_SHIFT 12
262 #define TTBCR_SH0_MASK 0x3
263 #define TTBCR_SH_NS 0
264 #define TTBCR_SH_OS 2
265 #define TTBCR_SH_IS 3
267 #define TTBCR_ORGN0_SHIFT 10
268 #define TTBCR_IRGN0_SHIFT 8
269 #define TTBCR_RGN_MASK 0x3
270 #define TTBCR_RGN_NC 0
271 #define TTBCR_RGN_WBWA 1
272 #define TTBCR_RGN_WT 2
273 #define TTBCR_RGN_WB 3
275 #define TTBCR_SL0_SHIFT 6
276 #define TTBCR_SL0_MASK 0x3
277 #define TTBCR_SL0_LVL_2 0
278 #define TTBCR_SL0_LVL_1 1
280 #define TTBCR_T1SZ_SHIFT 16
281 #define TTBCR_T0SZ_SHIFT 0
282 #define TTBCR_SZ_MASK 0xf
284 #define TTBCR2_SEP_SHIFT 15
285 #define TTBCR2_SEP_MASK 0x7
287 #define TTBCR2_PASIZE_SHIFT 0
288 #define TTBCR2_PASIZE_MASK 0x7
290 /* Common definitions for PASize and SEP fields */
291 #define TTBCR2_ADDR_32 0
292 #define TTBCR2_ADDR_36 1
293 #define TTBCR2_ADDR_40 2
294 #define TTBCR2_ADDR_42 3
295 #define TTBCR2_ADDR_44 4
296 #define TTBCR2_ADDR_48 5
298 #define TTBRn_HI_ASID_SHIFT 16
300 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
301 #define MAIR_ATTR_MASK 0xff
302 #define MAIR_ATTR_DEVICE 0x04
303 #define MAIR_ATTR_NC 0x44
304 #define MAIR_ATTR_WBRWA 0xff
305 #define MAIR_ATTR_IDX_NC 0
306 #define MAIR_ATTR_IDX_CACHE 1
307 #define MAIR_ATTR_IDX_DEV 2
309 #define FSR_MULTI (1 << 31)
310 #define FSR_SS (1 << 30)
311 #define FSR_UUT (1 << 8)
312 #define FSR_ASF (1 << 7)
313 #define FSR_TLBLKF (1 << 6)
314 #define FSR_TLBMCF (1 << 5)
315 #define FSR_EF (1 << 4)
316 #define FSR_PF (1 << 3)
317 #define FSR_AFF (1 << 2)
318 #define FSR_TF (1 << 1)
320 #define FSR_IGN (FSR_AFF | FSR_ASF | \
321 FSR_TLBMCF | FSR_TLBLKF)
322 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
323 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
325 #define FSYNR0_WNR (1 << 4)
327 struct arm_smmu_smr {
333 struct arm_smmu_master_cfg {
335 u16 streamids[MAX_MASTER_STREAMIDS];
336 struct arm_smmu_smr *smrs;
339 struct arm_smmu_master {
340 struct device_node *of_node;
342 struct arm_smmu_master_cfg cfg;
345 struct arm_smmu_device {
350 unsigned long pagesize;
352 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
353 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
354 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
355 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
356 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
359 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
363 u32 num_context_banks;
364 u32 num_s2_context_banks;
365 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
368 u32 num_mapping_groups;
369 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
371 unsigned long input_size;
372 unsigned long s1_output_size;
373 unsigned long s2_output_size;
376 u32 num_context_irqs;
379 struct list_head list;
380 struct rb_root masters;
383 struct arm_smmu_cfg {
389 #define INVALID_IRPTNDX 0xff
391 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
392 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
394 struct arm_smmu_domain {
395 struct arm_smmu_device *smmu;
396 struct arm_smmu_cfg cfg;
400 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
401 static LIST_HEAD(arm_smmu_devices);
403 struct arm_smmu_option_prop {
408 static struct arm_smmu_option_prop arm_smmu_options[] = {
409 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
413 static void parse_driver_options(struct arm_smmu_device *smmu)
418 if (of_property_read_bool(smmu->dev->of_node,
419 arm_smmu_options[i].prop)) {
420 smmu->options |= arm_smmu_options[i].opt;
421 dev_notice(smmu->dev, "option %s\n",
422 arm_smmu_options[i].prop);
424 } while (arm_smmu_options[++i].opt);
427 static struct device *dev_get_master_dev(struct device *dev)
429 if (dev_is_pci(dev)) {
430 struct pci_bus *bus = to_pci_dev(dev)->bus;
432 while (!pci_is_root_bus(bus))
434 return bus->bridge->parent;
440 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
441 struct device_node *dev_node)
443 struct rb_node *node = smmu->masters.rb_node;
446 struct arm_smmu_master *master;
448 master = container_of(node, struct arm_smmu_master, node);
450 if (dev_node < master->of_node)
451 node = node->rb_left;
452 else if (dev_node > master->of_node)
453 node = node->rb_right;
461 static struct arm_smmu_master_cfg *
462 find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev)
464 struct arm_smmu_master *master;
467 return dev->archdata.iommu;
469 master = find_smmu_master(smmu, dev->of_node);
470 return master ? &master->cfg : NULL;
473 static int insert_smmu_master(struct arm_smmu_device *smmu,
474 struct arm_smmu_master *master)
476 struct rb_node **new, *parent;
478 new = &smmu->masters.rb_node;
481 struct arm_smmu_master *this
482 = container_of(*new, struct arm_smmu_master, node);
485 if (master->of_node < this->of_node)
486 new = &((*new)->rb_left);
487 else if (master->of_node > this->of_node)
488 new = &((*new)->rb_right);
493 rb_link_node(&master->node, parent, new);
494 rb_insert_color(&master->node, &smmu->masters);
498 static int register_smmu_master(struct arm_smmu_device *smmu,
500 struct of_phandle_args *masterspec)
503 struct arm_smmu_master *master;
505 master = find_smmu_master(smmu, masterspec->np);
508 "rejecting multiple registrations for master device %s\n",
509 masterspec->np->name);
513 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
515 "reached maximum number (%d) of stream IDs for master device %s\n",
516 MAX_MASTER_STREAMIDS, masterspec->np->name);
520 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
524 master->of_node = masterspec->np;
525 master->cfg.num_streamids = masterspec->args_count;
527 for (i = 0; i < master->cfg.num_streamids; ++i)
528 master->cfg.streamids[i] = masterspec->args[i];
530 return insert_smmu_master(smmu, master);
533 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
535 struct arm_smmu_device *smmu;
536 struct arm_smmu_master *master = NULL;
537 struct device_node *dev_node = dev_get_master_dev(dev)->of_node;
539 spin_lock(&arm_smmu_devices_lock);
540 list_for_each_entry(smmu, &arm_smmu_devices, list) {
541 master = find_smmu_master(smmu, dev_node);
545 spin_unlock(&arm_smmu_devices_lock);
547 return master ? smmu : NULL;
550 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
555 idx = find_next_zero_bit(map, end, start);
558 } while (test_and_set_bit(idx, map));
563 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
568 /* Wait for any pending TLB invalidations to complete */
569 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
572 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
574 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
575 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
576 & sTLBGSTATUS_GSACTIVE) {
578 if (++count == TLB_LOOP_TIMEOUT) {
579 dev_err_ratelimited(smmu->dev,
580 "TLB sync timed out -- SMMU may be deadlocked\n");
587 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
589 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
590 struct arm_smmu_device *smmu = smmu_domain->smmu;
591 void __iomem *base = ARM_SMMU_GR0(smmu);
592 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
595 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
596 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
597 base + ARM_SMMU_CB_S1_TLBIASID);
599 base = ARM_SMMU_GR0(smmu);
600 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
601 base + ARM_SMMU_GR0_TLBIVMID);
604 arm_smmu_tlb_sync(smmu);
607 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
610 u32 fsr, far, fsynr, resume;
612 struct iommu_domain *domain = dev;
613 struct arm_smmu_domain *smmu_domain = domain->priv;
614 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
615 struct arm_smmu_device *smmu = smmu_domain->smmu;
616 void __iomem *cb_base;
618 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
619 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
621 if (!(fsr & FSR_FAULT))
625 dev_err_ratelimited(smmu->dev,
626 "Unexpected context fault (fsr 0x%u)\n",
629 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
630 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
632 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
635 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
636 iova |= ((unsigned long)far << 32);
639 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
641 resume = RESUME_RETRY;
643 dev_err_ratelimited(smmu->dev,
644 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
645 iova, fsynr, cfg->cbndx);
647 resume = RESUME_TERMINATE;
650 /* Clear the faulting FSR */
651 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
653 /* Retry or terminate any stalled transactions */
655 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
660 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
662 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
663 struct arm_smmu_device *smmu = dev;
664 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
666 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
667 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
668 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
669 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
674 dev_err_ratelimited(smmu->dev,
675 "Unexpected global fault, this could be serious\n");
676 dev_err_ratelimited(smmu->dev,
677 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
678 gfsr, gfsynr0, gfsynr1, gfsynr2);
680 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
684 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
687 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
690 /* Ensure new page tables are visible to the hardware walker */
691 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
695 * If the SMMU can't walk tables in the CPU caches, treat them
696 * like non-coherent DMA since we need to flush the new entries
697 * all the way out to memory. There's no possibility of
698 * recursion here as the SMMU table walker will not be wired
699 * through another SMMU.
701 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
706 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
710 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
711 struct arm_smmu_device *smmu = smmu_domain->smmu;
712 void __iomem *cb_base, *gr0_base, *gr1_base;
714 gr0_base = ARM_SMMU_GR0(smmu);
715 gr1_base = ARM_SMMU_GR1(smmu);
716 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
717 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
721 if (smmu->version == 1)
722 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
725 * Use the weakest shareability/memory types, so they are
726 * overridden by the ttbcr/pte.
729 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
730 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
732 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
734 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
736 if (smmu->version > 1) {
739 reg = CBA2R_RW64_64BIT;
741 reg = CBA2R_RW64_32BIT;
744 gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
747 switch (smmu->input_size) {
749 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
752 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
755 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
758 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
761 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
764 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
768 switch (smmu->s1_output_size) {
770 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
773 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
776 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
779 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
782 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
785 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
790 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
794 arm_smmu_flush_pgtable(smmu, cfg->pgd,
795 PTRS_PER_PGD * sizeof(pgd_t));
796 reg = __pa(cfg->pgd);
797 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
798 reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
800 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
801 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
805 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
807 if (smmu->version > 1) {
808 if (PAGE_SIZE == SZ_4K)
814 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
816 switch (smmu->s2_output_size) {
818 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
821 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
824 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
827 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
830 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
833 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
837 reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
844 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
845 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
846 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
847 (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
848 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
850 /* MAIR0 (stage-1 only) */
852 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
853 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
854 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
855 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
859 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
861 reg |= SCTLR_S1_ASIDPNE;
865 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
868 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
869 struct arm_smmu_device *smmu)
872 struct arm_smmu_domain *smmu_domain = domain->priv;
873 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
875 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
877 * We will likely want to change this if/when KVM gets
880 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
881 start = smmu->num_s2_context_banks;
882 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
883 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
884 start = smmu->num_s2_context_banks;
886 cfg->cbar = CBAR_TYPE_S2_TRANS;
890 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
891 smmu->num_context_banks);
892 if (IS_ERR_VALUE(ret))
896 if (smmu->version == 1) {
897 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
898 cfg->irptndx %= smmu->num_context_irqs;
900 cfg->irptndx = cfg->cbndx;
903 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
904 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
905 "arm-smmu-context-fault", domain);
906 if (IS_ERR_VALUE(ret)) {
907 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
909 cfg->irptndx = INVALID_IRPTNDX;
910 goto out_free_context;
913 smmu_domain->smmu = smmu;
914 arm_smmu_init_context_bank(smmu_domain);
918 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
922 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
924 struct arm_smmu_domain *smmu_domain = domain->priv;
925 struct arm_smmu_device *smmu = smmu_domain->smmu;
926 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
927 void __iomem *cb_base;
933 /* Disable the context bank and nuke the TLB before freeing it. */
934 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
935 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
936 arm_smmu_tlb_inv_context(smmu_domain);
938 if (cfg->irptndx != INVALID_IRPTNDX) {
939 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
940 free_irq(irq, domain);
943 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
946 static int arm_smmu_domain_init(struct iommu_domain *domain)
948 struct arm_smmu_domain *smmu_domain;
952 * Allocate the domain and initialise some of its data structures.
953 * We can't really do anything meaningful until we've added a
956 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
960 pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
962 goto out_free_domain;
963 smmu_domain->cfg.pgd = pgd;
965 spin_lock_init(&smmu_domain->lock);
966 domain->priv = smmu_domain;
974 static void arm_smmu_free_ptes(pmd_t *pmd)
976 pgtable_t table = pmd_pgtable(*pmd);
978 pgtable_page_dtor(table);
982 static void arm_smmu_free_pmds(pud_t *pud)
985 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
988 for (i = 0; i < PTRS_PER_PMD; ++i) {
992 arm_smmu_free_ptes(pmd);
996 pmd_free(NULL, pmd_base);
999 static void arm_smmu_free_puds(pgd_t *pgd)
1002 pud_t *pud, *pud_base = pud_offset(pgd, 0);
1005 for (i = 0; i < PTRS_PER_PUD; ++i) {
1009 arm_smmu_free_pmds(pud);
1013 pud_free(NULL, pud_base);
1016 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1019 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1020 pgd_t *pgd, *pgd_base = cfg->pgd;
1023 * Recursively free the page tables for this domain. We don't
1024 * care about speculative TLB filling because the tables should
1025 * not be active in any context bank at this point (SCTLR.M is 0).
1028 for (i = 0; i < PTRS_PER_PGD; ++i) {
1031 arm_smmu_free_puds(pgd);
1038 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1040 struct arm_smmu_domain *smmu_domain = domain->priv;
1043 * Free the domain resources. We assume that all devices have
1044 * already been detached.
1046 arm_smmu_destroy_domain_context(domain);
1047 arm_smmu_free_pgtables(smmu_domain);
1051 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1052 struct arm_smmu_master_cfg *cfg)
1055 struct arm_smmu_smr *smrs;
1056 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1058 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1064 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1066 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1067 cfg->num_streamids);
1071 /* Allocate the SMRs on the SMMU */
1072 for (i = 0; i < cfg->num_streamids; ++i) {
1073 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1074 smmu->num_mapping_groups);
1075 if (IS_ERR_VALUE(idx)) {
1076 dev_err(smmu->dev, "failed to allocate free SMR\n");
1080 smrs[i] = (struct arm_smmu_smr) {
1082 .mask = 0, /* We don't currently share SMRs */
1083 .id = cfg->streamids[i],
1087 /* It worked! Now, poke the actual hardware */
1088 for (i = 0; i < cfg->num_streamids; ++i) {
1089 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1090 smrs[i].mask << SMR_MASK_SHIFT;
1091 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1099 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1104 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1105 struct arm_smmu_master_cfg *cfg)
1108 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1109 struct arm_smmu_smr *smrs = cfg->smrs;
1111 /* Invalidate the SMRs before freeing back to the allocator */
1112 for (i = 0; i < cfg->num_streamids; ++i) {
1113 u8 idx = smrs[i].idx;
1115 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1116 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1123 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1124 struct arm_smmu_master_cfg *cfg)
1127 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1129 for (i = 0; i < cfg->num_streamids; ++i) {
1130 u16 sid = cfg->streamids[i];
1132 writel_relaxed(S2CR_TYPE_BYPASS,
1133 gr0_base + ARM_SMMU_GR0_S2CR(sid));
1137 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1138 struct arm_smmu_master_cfg *cfg)
1141 struct arm_smmu_device *smmu = smmu_domain->smmu;
1142 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1144 ret = arm_smmu_master_configure_smrs(smmu, cfg);
1148 for (i = 0; i < cfg->num_streamids; ++i) {
1151 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1152 s2cr = S2CR_TYPE_TRANS |
1153 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1154 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1160 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1161 struct arm_smmu_master_cfg *cfg)
1163 struct arm_smmu_device *smmu = smmu_domain->smmu;
1166 * We *must* clear the S2CR first, because freeing the SMR means
1167 * that it can be re-allocated immediately.
1169 arm_smmu_bypass_stream_mapping(smmu, cfg);
1170 arm_smmu_master_free_smrs(smmu, cfg);
1173 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1176 struct arm_smmu_domain *smmu_domain = domain->priv;
1177 struct arm_smmu_device *smmu;
1178 struct arm_smmu_master_cfg *cfg;
1179 unsigned long flags;
1181 smmu = dev_get_master_dev(dev)->archdata.iommu;
1183 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1188 * Sanity check the domain. We don't support domains across
1191 spin_lock_irqsave(&smmu_domain->lock, flags);
1192 if (!smmu_domain->smmu) {
1193 /* Now that we have a master, we can finalise the domain */
1194 ret = arm_smmu_init_domain_context(domain, smmu);
1195 if (IS_ERR_VALUE(ret))
1197 } else if (smmu_domain->smmu != smmu) {
1199 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1200 dev_name(smmu_domain->smmu->dev),
1201 dev_name(smmu->dev));
1204 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1206 /* Looks ok, so add the device to the domain */
1207 cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1211 return arm_smmu_domain_add_master(smmu_domain, cfg);
1214 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1218 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1220 struct arm_smmu_domain *smmu_domain = domain->priv;
1221 struct arm_smmu_master_cfg *cfg;
1223 cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1225 arm_smmu_domain_remove_master(smmu_domain, cfg);
1228 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1231 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1232 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1235 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1236 unsigned long addr, unsigned long end,
1237 unsigned long pfn, int prot, int stage)
1240 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1242 if (pmd_none(*pmd)) {
1243 /* Allocate a new set of tables */
1244 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1249 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1250 if (!pgtable_page_ctor(table)) {
1254 pmd_populate(NULL, pmd, table);
1255 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1259 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1260 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1261 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1263 if (prot & IOMMU_CACHE)
1264 pteval |= (MAIR_ATTR_IDX_CACHE <<
1265 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1267 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1268 if (prot & IOMMU_READ)
1269 pteval |= ARM_SMMU_PTE_HAP_READ;
1270 if (prot & IOMMU_WRITE)
1271 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1272 if (prot & IOMMU_CACHE)
1273 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1275 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1278 /* If no access, create a faulting entry to avoid TLB fills */
1279 if (prot & IOMMU_EXEC)
1280 pteval &= ~ARM_SMMU_PTE_XN;
1281 else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1282 pteval &= ~ARM_SMMU_PTE_PAGE;
1284 pteval |= ARM_SMMU_PTE_SH_IS;
1285 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1289 * Install the page table entries. This is fairly complicated
1290 * since we attempt to make use of the contiguous hint in the
1291 * ptes where possible. The contiguous hint indicates a series
1292 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1293 * contiguous region with the following constraints:
1295 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1296 * - Each pte in the region has the contiguous hint bit set
1298 * This complicates unmapping (also handled by this code, when
1299 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1300 * possible, yet highly unlikely, that a client may unmap only
1301 * part of a contiguous range. This requires clearing of the
1302 * contiguous hint bits in the range before installing the new
1305 * Note that re-mapping an address range without first unmapping
1306 * it is not supported, so TLB invalidation is not required here
1307 * and is instead performed at unmap and domain-init time.
1312 pteval &= ~ARM_SMMU_PTE_CONT;
1314 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1315 i = ARM_SMMU_PTE_CONT_ENTRIES;
1316 pteval |= ARM_SMMU_PTE_CONT;
1317 } else if (pte_val(*pte) &
1318 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1321 unsigned long idx = pte_index(addr);
1323 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1324 cont_start = pmd_page_vaddr(*pmd) + idx;
1325 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1326 pte_val(*(cont_start + j)) &=
1329 arm_smmu_flush_pgtable(smmu, cont_start,
1331 ARM_SMMU_PTE_CONT_ENTRIES);
1335 *pte = pfn_pte(pfn, __pgprot(pteval));
1336 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1337 } while (addr != end);
1339 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1343 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1344 unsigned long addr, unsigned long end,
1345 phys_addr_t phys, int prot, int stage)
1349 unsigned long next, pfn = __phys_to_pfn(phys);
1351 #ifndef __PAGETABLE_PMD_FOLDED
1352 if (pud_none(*pud)) {
1353 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1357 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1358 pud_populate(NULL, pud, pmd);
1359 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1361 pmd += pmd_index(addr);
1364 pmd = pmd_offset(pud, addr);
1367 next = pmd_addr_end(addr, end);
1368 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1370 phys += next - addr;
1371 } while (pmd++, addr = next, addr < end);
1376 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1377 unsigned long addr, unsigned long end,
1378 phys_addr_t phys, int prot, int stage)
1384 #ifndef __PAGETABLE_PUD_FOLDED
1385 if (pgd_none(*pgd)) {
1386 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1390 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1391 pgd_populate(NULL, pgd, pud);
1392 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1394 pud += pud_index(addr);
1397 pud = pud_offset(pgd, addr);
1400 next = pud_addr_end(addr, end);
1401 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1403 phys += next - addr;
1404 } while (pud++, addr = next, addr < end);
1409 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1410 unsigned long iova, phys_addr_t paddr,
1411 size_t size, int prot)
1415 phys_addr_t input_mask, output_mask;
1416 struct arm_smmu_device *smmu = smmu_domain->smmu;
1417 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1418 pgd_t *pgd = cfg->pgd;
1419 unsigned long flags;
1421 if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1423 output_mask = (1ULL << smmu->s2_output_size) - 1;
1426 output_mask = (1ULL << smmu->s1_output_size) - 1;
1432 if (size & ~PAGE_MASK)
1435 input_mask = (1ULL << smmu->input_size) - 1;
1436 if ((phys_addr_t)iova & ~input_mask)
1439 if (paddr & ~output_mask)
1442 spin_lock_irqsave(&smmu_domain->lock, flags);
1443 pgd += pgd_index(iova);
1446 unsigned long next = pgd_addr_end(iova, end);
1448 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1453 paddr += next - iova;
1455 } while (pgd++, iova != end);
1458 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1463 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1464 phys_addr_t paddr, size_t size, int prot)
1466 struct arm_smmu_domain *smmu_domain = domain->priv;
1471 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1474 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1478 struct arm_smmu_domain *smmu_domain = domain->priv;
1480 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1481 arm_smmu_tlb_inv_context(smmu_domain);
1482 return ret ? 0 : size;
1485 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1492 struct arm_smmu_domain *smmu_domain = domain->priv;
1493 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1499 pgd = *(pgdp + pgd_index(iova));
1503 pud = *pud_offset(&pgd, iova);
1507 pmd = *pmd_offset(&pud, iova);
1511 pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1515 return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1518 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1521 struct arm_smmu_domain *smmu_domain = domain->priv;
1522 struct arm_smmu_device *smmu = smmu_domain->smmu;
1523 u32 features = smmu ? smmu->features : 0;
1526 case IOMMU_CAP_CACHE_COHERENCY:
1527 return features & ARM_SMMU_FEAT_COHERENT_WALK;
1528 case IOMMU_CAP_INTR_REMAP:
1529 return 1; /* MSIs are just memory writes */
1535 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1537 *((u16 *)data) = alias;
1538 return 0; /* Continue walking */
1541 static int arm_smmu_add_device(struct device *dev)
1543 struct arm_smmu_device *smmu;
1544 struct iommu_group *group;
1547 if (dev->archdata.iommu) {
1548 dev_warn(dev, "IOMMU driver already assigned to device\n");
1552 smmu = find_smmu_for_device(dev);
1556 group = iommu_group_alloc();
1557 if (IS_ERR(group)) {
1558 dev_err(dev, "Failed to allocate IOMMU group\n");
1559 return PTR_ERR(group);
1562 if (dev_is_pci(dev)) {
1563 struct arm_smmu_master_cfg *cfg;
1564 struct pci_dev *pdev = to_pci_dev(dev);
1566 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1572 cfg->num_streamids = 1;
1574 * Assume Stream ID == Requester ID for now.
1575 * We need a way to describe the ID mappings in FDT.
1577 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1578 &cfg->streamids[0]);
1579 dev->archdata.iommu = cfg;
1581 dev->archdata.iommu = smmu;
1584 ret = iommu_group_add_device(group, dev);
1587 iommu_group_put(group);
1591 static void arm_smmu_remove_device(struct device *dev)
1593 if (dev_is_pci(dev))
1594 kfree(dev->archdata.iommu);
1596 dev->archdata.iommu = NULL;
1597 iommu_group_remove_device(dev);
1600 static const struct iommu_ops arm_smmu_ops = {
1601 .domain_init = arm_smmu_domain_init,
1602 .domain_destroy = arm_smmu_domain_destroy,
1603 .attach_dev = arm_smmu_attach_dev,
1604 .detach_dev = arm_smmu_detach_dev,
1605 .map = arm_smmu_map,
1606 .unmap = arm_smmu_unmap,
1607 .iova_to_phys = arm_smmu_iova_to_phys,
1608 .domain_has_cap = arm_smmu_domain_has_cap,
1609 .add_device = arm_smmu_add_device,
1610 .remove_device = arm_smmu_remove_device,
1611 .pgsize_bitmap = (SECTION_SIZE |
1612 ARM_SMMU_PTE_CONT_SIZE |
1616 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1618 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1619 void __iomem *cb_base;
1623 /* clear global FSR */
1624 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1625 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1627 /* Mark all SMRn as invalid and all S2CRn as bypass */
1628 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1629 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1630 writel_relaxed(S2CR_TYPE_BYPASS,
1631 gr0_base + ARM_SMMU_GR0_S2CR(i));
1634 /* Make sure all context banks are disabled and clear CB_FSR */
1635 for (i = 0; i < smmu->num_context_banks; ++i) {
1636 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1637 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1638 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1641 /* Invalidate the TLB, just in case */
1642 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1643 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1644 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1646 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1648 /* Enable fault reporting */
1649 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1651 /* Disable TLB broadcasting. */
1652 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1654 /* Enable client access, but bypass when no mapping is found */
1655 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1657 /* Disable forced broadcasting */
1660 /* Don't upgrade barriers */
1661 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1663 /* Push the button */
1664 arm_smmu_tlb_sync(smmu);
1665 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1668 static int arm_smmu_id_size_to_bits(int size)
1687 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1690 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1693 dev_notice(smmu->dev, "probing hardware configuration...\n");
1696 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1697 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1698 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1701 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1702 #ifndef CONFIG_64BIT
1703 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1704 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1708 if (id & ID0_S1TS) {
1709 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1710 dev_notice(smmu->dev, "\tstage 1 translation\n");
1713 if (id & ID0_S2TS) {
1714 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1715 dev_notice(smmu->dev, "\tstage 2 translation\n");
1719 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1720 dev_notice(smmu->dev, "\tnested translation\n");
1723 if (!(smmu->features &
1724 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1725 ARM_SMMU_FEAT_TRANS_NESTED))) {
1726 dev_err(smmu->dev, "\tno translation support!\n");
1730 if (id & ID0_CTTW) {
1731 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1732 dev_notice(smmu->dev, "\tcoherent table walk\n");
1738 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1739 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1741 if (smmu->num_mapping_groups == 0) {
1743 "stream-matching supported, but no SMRs present!\n");
1747 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1748 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1749 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1750 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1752 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1753 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1754 if ((mask & sid) != sid) {
1756 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1761 dev_notice(smmu->dev,
1762 "\tstream matching with %u register groups, mask 0x%x",
1763 smmu->num_mapping_groups, mask);
1767 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1768 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1770 /* Check for size mismatch of SMMU address space from mapped region */
1772 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1773 size *= (smmu->pagesize << 1);
1774 if (smmu->size != size)
1776 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1779 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1781 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1782 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1783 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1786 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1787 smmu->num_context_banks, smmu->num_s2_context_banks);
1790 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1791 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1794 * Stage-1 output limited by stage-2 input size due to pgd
1795 * allocation (PTRS_PER_PGD).
1798 smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
1800 smmu->s1_output_size = min(32UL, size);
1803 /* The stage-2 output mask is also applied for bypass */
1804 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1805 smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1807 if (smmu->version == 1) {
1808 smmu->input_size = 32;
1811 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1812 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1816 smmu->input_size = size;
1818 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1819 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1820 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1821 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1827 dev_notice(smmu->dev,
1828 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1829 smmu->input_size, smmu->s1_output_size,
1830 smmu->s2_output_size);
1834 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1836 struct resource *res;
1837 struct arm_smmu_device *smmu;
1838 struct device *dev = &pdev->dev;
1839 struct rb_node *node;
1840 struct of_phandle_args masterspec;
1841 int num_irqs, i, err;
1843 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1845 dev_err(dev, "failed to allocate arm_smmu_device\n");
1850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1851 smmu->base = devm_ioremap_resource(dev, res);
1852 if (IS_ERR(smmu->base))
1853 return PTR_ERR(smmu->base);
1854 smmu->size = resource_size(res);
1856 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1857 &smmu->num_global_irqs)) {
1858 dev_err(dev, "missing #global-interrupts property\n");
1863 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1865 if (num_irqs > smmu->num_global_irqs)
1866 smmu->num_context_irqs++;
1869 if (!smmu->num_context_irqs) {
1870 dev_err(dev, "found %d interrupts but expected at least %d\n",
1871 num_irqs, smmu->num_global_irqs + 1);
1875 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1878 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1882 for (i = 0; i < num_irqs; ++i) {
1883 int irq = platform_get_irq(pdev, i);
1886 dev_err(dev, "failed to get irq index %d\n", i);
1889 smmu->irqs[i] = irq;
1893 smmu->masters = RB_ROOT;
1894 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1895 "#stream-id-cells", i,
1897 err = register_smmu_master(smmu, dev, &masterspec);
1899 dev_err(dev, "failed to add master %s\n",
1900 masterspec.np->name);
1901 goto out_put_masters;
1906 dev_notice(dev, "registered %d master devices\n", i);
1908 err = arm_smmu_device_cfg_probe(smmu);
1910 goto out_put_masters;
1912 parse_driver_options(smmu);
1914 if (smmu->version > 1 &&
1915 smmu->num_context_banks != smmu->num_context_irqs) {
1917 "found only %d context interrupt(s) but %d required\n",
1918 smmu->num_context_irqs, smmu->num_context_banks);
1920 goto out_put_masters;
1923 for (i = 0; i < smmu->num_global_irqs; ++i) {
1924 err = request_irq(smmu->irqs[i],
1925 arm_smmu_global_fault,
1927 "arm-smmu global fault",
1930 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1936 INIT_LIST_HEAD(&smmu->list);
1937 spin_lock(&arm_smmu_devices_lock);
1938 list_add(&smmu->list, &arm_smmu_devices);
1939 spin_unlock(&arm_smmu_devices_lock);
1941 arm_smmu_device_reset(smmu);
1946 free_irq(smmu->irqs[i], smmu);
1949 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1950 struct arm_smmu_master *master
1951 = container_of(node, struct arm_smmu_master, node);
1952 of_node_put(master->of_node);
1958 static int arm_smmu_device_remove(struct platform_device *pdev)
1961 struct device *dev = &pdev->dev;
1962 struct arm_smmu_device *curr, *smmu = NULL;
1963 struct rb_node *node;
1965 spin_lock(&arm_smmu_devices_lock);
1966 list_for_each_entry(curr, &arm_smmu_devices, list) {
1967 if (curr->dev == dev) {
1969 list_del(&smmu->list);
1973 spin_unlock(&arm_smmu_devices_lock);
1978 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1979 struct arm_smmu_master *master
1980 = container_of(node, struct arm_smmu_master, node);
1981 of_node_put(master->of_node);
1984 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1985 dev_err(dev, "removing device with active domains!\n");
1987 for (i = 0; i < smmu->num_global_irqs; ++i)
1988 free_irq(smmu->irqs[i], smmu);
1990 /* Turn the thing off */
1991 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1996 static struct of_device_id arm_smmu_of_match[] = {
1997 { .compatible = "arm,smmu-v1", },
1998 { .compatible = "arm,smmu-v2", },
1999 { .compatible = "arm,mmu-400", },
2000 { .compatible = "arm,mmu-500", },
2003 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2006 static struct platform_driver arm_smmu_driver = {
2008 .owner = THIS_MODULE,
2010 .of_match_table = of_match_ptr(arm_smmu_of_match),
2012 .probe = arm_smmu_device_dt_probe,
2013 .remove = arm_smmu_device_remove,
2016 static int __init arm_smmu_init(void)
2020 ret = platform_driver_register(&arm_smmu_driver);
2024 /* Oh, for a proper bus abstraction */
2025 if (!iommu_present(&platform_bus_type))
2026 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2028 #ifdef CONFIG_ARM_AMBA
2029 if (!iommu_present(&amba_bustype))
2030 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2034 if (!iommu_present(&pci_bus_type))
2035 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2041 static void __exit arm_smmu_exit(void)
2043 return platform_driver_unregister(&arm_smmu_driver);
2046 subsys_initcall(arm_smmu_init);
2047 module_exit(arm_smmu_exit);
2049 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2050 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2051 MODULE_LICENSE("GPL v2");