2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
22 * This file implements early detection/parsing of Remapping Devices
23 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
26 * These routines are used by both DMA-remapping and Interrupt-remapping
29 #define pr_fmt(fmt) "DMAR: " fmt
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/iova.h>
34 #include <linux/intel-iommu.h>
35 #include <linux/timer.h>
36 #include <linux/irq.h>
37 #include <linux/interrupt.h>
38 #include <linux/tboot.h>
39 #include <linux/dmi.h>
40 #include <linux/slab.h>
41 #include <linux/iommu.h>
42 #include <asm/irq_remapping.h>
43 #include <asm/iommu_table.h>
45 #include "irq_remapping.h"
47 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
48 struct dmar_res_callback {
49 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED];
50 void *arg[ACPI_DMAR_TYPE_RESERVED];
51 bool ignore_unhandled;
57 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
58 * before IO devices managed by that unit.
59 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
60 * after IO devices managed by that unit.
61 * 3) Hotplug events are rare.
63 * Locking rules for DMA and interrupt remapping related global data structures:
64 * 1) Use dmar_global_lock in process context
65 * 2) Use RCU in interrupt context
67 DECLARE_RWSEM(dmar_global_lock);
68 LIST_HEAD(dmar_drhd_units);
70 struct acpi_table_header * __initdata dmar_tbl;
71 static int dmar_dev_scope_status = 1;
72 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
74 static int alloc_iommu(struct dmar_drhd_unit *drhd);
75 static void free_iommu(struct intel_iommu *iommu);
77 extern const struct iommu_ops intel_iommu_ops;
79 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
82 * add INCLUDE_ALL at the tail, so scan the list will find it at
85 if (drhd->include_all)
86 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
88 list_add_rcu(&drhd->list, &dmar_drhd_units);
91 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
93 struct acpi_dmar_device_scope *scope;
98 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
99 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
100 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
102 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
103 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
104 pr_warn("Unsupported device scope\n");
106 start += scope->length;
111 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
114 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
117 struct device *tmp_dev;
119 if (*devices && *cnt) {
120 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
129 /* Optimize out kzalloc()/kfree() for normal cases */
130 static char dmar_pci_notify_info_buf[64];
132 static struct dmar_pci_notify_info *
133 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
138 struct dmar_pci_notify_info *info;
140 BUG_ON(dev->is_virtfn);
142 /* Only generate path[] for device addition event */
143 if (event == BUS_NOTIFY_ADD_DEVICE)
144 for (tmp = dev; tmp; tmp = tmp->bus->self)
147 size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path);
148 if (size <= sizeof(dmar_pci_notify_info_buf)) {
149 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
151 info = kzalloc(size, GFP_KERNEL);
153 pr_warn("Out of memory when allocating notify_info "
154 "for %s.\n", pci_name(dev));
155 if (dmar_dev_scope_status == 0)
156 dmar_dev_scope_status = -ENOMEM;
163 info->seg = pci_domain_nr(dev->bus);
165 if (event == BUS_NOTIFY_ADD_DEVICE) {
166 for (tmp = dev; tmp; tmp = tmp->bus->self) {
168 info->path[level].bus = tmp->bus->number;
169 info->path[level].device = PCI_SLOT(tmp->devfn);
170 info->path[level].function = PCI_FUNC(tmp->devfn);
171 if (pci_is_root_bus(tmp->bus))
172 info->bus = tmp->bus->number;
179 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
181 if ((void *)info != dmar_pci_notify_info_buf)
185 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
186 struct acpi_dmar_pci_path *path, int count)
190 if (info->bus != bus)
192 if (info->level != count)
195 for (i = 0; i < count; i++) {
196 if (path[i].device != info->path[i].device ||
197 path[i].function != info->path[i].function)
209 if (bus == info->path[i].bus &&
210 path[0].device == info->path[i].device &&
211 path[0].function == info->path[i].function) {
212 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
213 bus, path[0].device, path[0].function);
220 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
221 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
222 void *start, void*end, u16 segment,
223 struct dmar_dev_scope *devices,
227 struct device *tmp, *dev = &info->dev->dev;
228 struct acpi_dmar_device_scope *scope;
229 struct acpi_dmar_pci_path *path;
231 if (segment != info->seg)
234 for (; start < end; start += scope->length) {
236 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
237 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
240 path = (struct acpi_dmar_pci_path *)(scope + 1);
241 level = (scope->length - sizeof(*scope)) / sizeof(*path);
242 if (!dmar_match_pci_path(info, scope->bus, path, level))
246 * We expect devices with endpoint scope to have normal PCI
247 * headers, and devices with bridge scope to have bridge PCI
248 * headers. However PCI NTB devices may be listed in the
249 * DMAR table with bridge scope, even though they have a
250 * normal PCI header. NTB devices are identified by class
251 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
252 * for this special case.
254 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
255 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
256 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
257 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
258 info->dev->class >> 8 != PCI_CLASS_BRIDGE_OTHER))) {
259 pr_warn("Device scope type does not match for %s\n",
260 pci_name(info->dev));
264 for_each_dev_scope(devices, devices_cnt, i, tmp)
266 devices[i].bus = info->dev->bus->number;
267 devices[i].devfn = info->dev->devfn;
268 rcu_assign_pointer(devices[i].dev,
272 BUG_ON(i >= devices_cnt);
278 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
279 struct dmar_dev_scope *devices, int count)
284 if (info->seg != segment)
287 for_each_active_dev_scope(devices, count, index, tmp)
288 if (tmp == &info->dev->dev) {
289 RCU_INIT_POINTER(devices[index].dev, NULL);
298 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
301 struct dmar_drhd_unit *dmaru;
302 struct acpi_dmar_hardware_unit *drhd;
304 for_each_drhd_unit(dmaru) {
305 if (dmaru->include_all)
308 drhd = container_of(dmaru->hdr,
309 struct acpi_dmar_hardware_unit, header);
310 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
311 ((void *)drhd) + drhd->header.length,
313 dmaru->devices, dmaru->devices_cnt);
318 ret = dmar_iommu_notify_scope_dev(info);
319 if (ret < 0 && dmar_dev_scope_status == 0)
320 dmar_dev_scope_status = ret;
325 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
327 struct dmar_drhd_unit *dmaru;
329 for_each_drhd_unit(dmaru)
330 if (dmar_remove_dev_scope(info, dmaru->segment,
331 dmaru->devices, dmaru->devices_cnt))
333 dmar_iommu_notify_scope_dev(info);
336 static int dmar_pci_bus_notifier(struct notifier_block *nb,
337 unsigned long action, void *data)
339 struct pci_dev *pdev = to_pci_dev(data);
340 struct dmar_pci_notify_info *info;
342 /* Only care about add/remove events for physical functions.
343 * For VFs we actually do the lookup based on the corresponding
344 * PF in device_to_iommu() anyway. */
347 if (action != BUS_NOTIFY_ADD_DEVICE &&
348 action != BUS_NOTIFY_REMOVED_DEVICE)
351 info = dmar_alloc_pci_notify_info(pdev, action);
355 down_write(&dmar_global_lock);
356 if (action == BUS_NOTIFY_ADD_DEVICE)
357 dmar_pci_bus_add_dev(info);
358 else if (action == BUS_NOTIFY_REMOVED_DEVICE)
359 dmar_pci_bus_del_dev(info);
360 up_write(&dmar_global_lock);
362 dmar_free_pci_notify_info(info);
367 static struct notifier_block dmar_pci_bus_nb = {
368 .notifier_call = dmar_pci_bus_notifier,
372 static struct dmar_drhd_unit *
373 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
375 struct dmar_drhd_unit *dmaru;
377 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list)
378 if (dmaru->segment == drhd->segment &&
379 dmaru->reg_base_addr == drhd->address)
386 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
387 * structure which uniquely represent one DMA remapping hardware unit
388 * present in the platform
390 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
392 struct acpi_dmar_hardware_unit *drhd;
393 struct dmar_drhd_unit *dmaru;
396 drhd = (struct acpi_dmar_hardware_unit *)header;
397 dmaru = dmar_find_dmaru(drhd);
401 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
406 * If header is allocated from slab by ACPI _DSM method, we need to
407 * copy the content because the memory buffer will be freed on return.
409 dmaru->hdr = (void *)(dmaru + 1);
410 memcpy(dmaru->hdr, header, header->length);
411 dmaru->reg_base_addr = drhd->address;
412 dmaru->segment = drhd->segment;
413 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
414 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
415 ((void *)drhd) + drhd->header.length,
416 &dmaru->devices_cnt);
417 if (dmaru->devices_cnt && dmaru->devices == NULL) {
422 ret = alloc_iommu(dmaru);
424 dmar_free_dev_scope(&dmaru->devices,
425 &dmaru->devices_cnt);
429 dmar_register_drhd_unit(dmaru);
438 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
440 if (dmaru->devices && dmaru->devices_cnt)
441 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
443 free_iommu(dmaru->iommu);
447 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
450 struct acpi_dmar_andd *andd = (void *)header;
452 /* Check for NUL termination within the designated length */
453 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
454 WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND,
455 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
456 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
457 dmi_get_system_info(DMI_BIOS_VENDOR),
458 dmi_get_system_info(DMI_BIOS_VERSION),
459 dmi_get_system_info(DMI_PRODUCT_VERSION));
462 pr_info("ANDD device: %x name: %s\n", andd->device_number,
468 #ifdef CONFIG_ACPI_NUMA
469 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
471 struct acpi_dmar_rhsa *rhsa;
472 struct dmar_drhd_unit *drhd;
474 rhsa = (struct acpi_dmar_rhsa *)header;
475 for_each_drhd_unit(drhd) {
476 if (drhd->reg_base_addr == rhsa->base_address) {
477 int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
479 if (!node_online(node))
481 drhd->iommu->node = node;
486 1, TAINT_FIRMWARE_WORKAROUND,
487 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
488 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
490 dmi_get_system_info(DMI_BIOS_VENDOR),
491 dmi_get_system_info(DMI_BIOS_VERSION),
492 dmi_get_system_info(DMI_PRODUCT_VERSION));
497 #define dmar_parse_one_rhsa dmar_res_noop
501 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
503 struct acpi_dmar_hardware_unit *drhd;
504 struct acpi_dmar_reserved_memory *rmrr;
505 struct acpi_dmar_atsr *atsr;
506 struct acpi_dmar_rhsa *rhsa;
508 switch (header->type) {
509 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
510 drhd = container_of(header, struct acpi_dmar_hardware_unit,
512 pr_info("DRHD base: %#016Lx flags: %#x\n",
513 (unsigned long long)drhd->address, drhd->flags);
515 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
516 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
518 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
519 (unsigned long long)rmrr->base_address,
520 (unsigned long long)rmrr->end_address);
522 case ACPI_DMAR_TYPE_ROOT_ATS:
523 atsr = container_of(header, struct acpi_dmar_atsr, header);
524 pr_info("ATSR flags: %#x\n", atsr->flags);
526 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
527 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
528 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
529 (unsigned long long)rhsa->base_address,
530 rhsa->proximity_domain);
532 case ACPI_DMAR_TYPE_NAMESPACE:
533 /* We don't print this here because we need to sanity-check
534 it first. So print it in dmar_parse_one_andd() instead. */
540 * dmar_table_detect - checks to see if the platform supports DMAR devices
542 static int __init dmar_table_detect(void)
544 acpi_status status = AE_OK;
546 /* if we could find DMAR table, then there are DMAR devices */
547 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
549 if (ACPI_SUCCESS(status) && !dmar_tbl) {
550 pr_warn("Unable to map DMAR\n");
551 status = AE_NOT_FOUND;
554 return (ACPI_SUCCESS(status) ? 1 : 0);
557 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
558 size_t len, struct dmar_res_callback *cb)
561 struct acpi_dmar_header *iter, *next;
562 struct acpi_dmar_header *end = ((void *)start) + len;
564 for (iter = start; iter < end && ret == 0; iter = next) {
565 next = (void *)iter + iter->length;
566 if (iter->length == 0) {
567 /* Avoid looping forever on bad ACPI tables */
568 pr_debug(FW_BUG "Invalid 0-length structure\n");
570 } else if (next > end) {
571 /* Avoid passing table end */
572 pr_warn(FW_BUG "Record passes table end\n");
578 dmar_table_print_dmar_entry(iter);
580 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
581 /* continue for forward compatibility */
582 pr_debug("Unknown DMAR structure type %d\n",
584 } else if (cb->cb[iter->type]) {
585 ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
586 } else if (!cb->ignore_unhandled) {
587 pr_warn("No handler for DMAR structure type %d\n",
596 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
597 struct dmar_res_callback *cb)
599 return dmar_walk_remapping_entries((void *)(dmar + 1),
600 dmar->header.length - sizeof(*dmar), cb);
604 * parse_dmar_table - parses the DMA reporting table
607 parse_dmar_table(void)
609 struct acpi_table_dmar *dmar;
612 struct dmar_res_callback cb = {
614 .ignore_unhandled = true,
615 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
616 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
617 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
618 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
619 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
620 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
624 * Do it again, earlier dmar_tbl mapping could be mapped with
630 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
631 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
633 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
635 dmar = (struct acpi_table_dmar *)dmar_tbl;
639 if (dmar->width < PAGE_SHIFT - 1) {
640 pr_warn("Invalid DMAR haw\n");
644 pr_info("Host address width %d\n", dmar->width + 1);
645 ret = dmar_walk_dmar_table(dmar, &cb);
646 if (ret == 0 && drhd_count == 0)
647 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
652 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
653 int cnt, struct pci_dev *dev)
659 for_each_active_dev_scope(devices, cnt, index, tmp)
660 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
663 /* Check our parent */
664 dev = dev->bus->self;
670 struct dmar_drhd_unit *
671 dmar_find_matched_drhd_unit(struct pci_dev *dev)
673 struct dmar_drhd_unit *dmaru;
674 struct acpi_dmar_hardware_unit *drhd;
676 dev = pci_physfn(dev);
679 for_each_drhd_unit(dmaru) {
680 drhd = container_of(dmaru->hdr,
681 struct acpi_dmar_hardware_unit,
684 if (dmaru->include_all &&
685 drhd->segment == pci_domain_nr(dev->bus))
688 if (dmar_pci_device_match(dmaru->devices,
689 dmaru->devices_cnt, dev))
699 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
700 struct acpi_device *adev)
702 struct dmar_drhd_unit *dmaru;
703 struct acpi_dmar_hardware_unit *drhd;
704 struct acpi_dmar_device_scope *scope;
707 struct acpi_dmar_pci_path *path;
709 for_each_drhd_unit(dmaru) {
710 drhd = container_of(dmaru->hdr,
711 struct acpi_dmar_hardware_unit,
714 for (scope = (void *)(drhd + 1);
715 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
716 scope = ((void *)scope) + scope->length) {
717 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
719 if (scope->enumeration_id != device_number)
722 path = (void *)(scope + 1);
723 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
724 dev_name(&adev->dev), dmaru->reg_base_addr,
725 scope->bus, path->device, path->function);
726 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
728 dmaru->devices[i].bus = scope->bus;
729 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
731 rcu_assign_pointer(dmaru->devices[i].dev,
732 get_device(&adev->dev));
735 BUG_ON(i >= dmaru->devices_cnt);
738 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
739 device_number, dev_name(&adev->dev));
742 static int __init dmar_acpi_dev_scope_init(void)
744 struct acpi_dmar_andd *andd;
746 if (dmar_tbl == NULL)
749 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
750 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
751 andd = ((void *)andd) + andd->header.length) {
752 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
754 struct acpi_device *adev;
756 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
759 pr_err("Failed to find handle for ACPI object %s\n",
763 if (acpi_bus_get_device(h, &adev)) {
764 pr_err("Failed to get device for ACPI object %s\n",
768 dmar_acpi_insert_dev_scope(andd->device_number, adev);
774 int __init dmar_dev_scope_init(void)
776 struct pci_dev *dev = NULL;
777 struct dmar_pci_notify_info *info;
779 if (dmar_dev_scope_status != 1)
780 return dmar_dev_scope_status;
782 if (list_empty(&dmar_drhd_units)) {
783 dmar_dev_scope_status = -ENODEV;
785 dmar_dev_scope_status = 0;
787 dmar_acpi_dev_scope_init();
789 for_each_pci_dev(dev) {
793 info = dmar_alloc_pci_notify_info(dev,
794 BUS_NOTIFY_ADD_DEVICE);
796 return dmar_dev_scope_status;
798 dmar_pci_bus_add_dev(info);
799 dmar_free_pci_notify_info(info);
803 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
806 return dmar_dev_scope_status;
810 int __init dmar_table_init(void)
812 static int dmar_table_initialized;
815 if (dmar_table_initialized == 0) {
816 ret = parse_dmar_table();
819 pr_info("Parse DMAR table failure.\n");
820 } else if (list_empty(&dmar_drhd_units)) {
821 pr_info("No DMAR devices found\n");
826 dmar_table_initialized = ret;
828 dmar_table_initialized = 1;
831 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
834 static void warn_invalid_dmar(u64 addr, const char *message)
837 1, TAINT_FIRMWARE_WORKAROUND,
838 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
839 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
841 dmi_get_system_info(DMI_BIOS_VENDOR),
842 dmi_get_system_info(DMI_BIOS_VERSION),
843 dmi_get_system_info(DMI_PRODUCT_VERSION));
847 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
849 struct acpi_dmar_hardware_unit *drhd;
853 drhd = (void *)entry;
854 if (!drhd->address) {
855 warn_invalid_dmar(0, "");
860 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
862 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
864 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
868 cap = dmar_readq(addr + DMAR_CAP_REG);
869 ecap = dmar_readq(addr + DMAR_ECAP_REG);
874 early_iounmap(addr, VTD_PAGE_SIZE);
876 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
877 warn_invalid_dmar(drhd->address, " returns all ones");
884 int __init detect_intel_iommu(void)
887 struct dmar_res_callback validate_drhd_cb = {
888 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
889 .ignore_unhandled = true,
892 down_write(&dmar_global_lock);
893 ret = dmar_table_detect();
895 ret = !dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
897 if (ret && !no_iommu && !iommu_detected && !dmar_disabled) {
899 /* Make sure ACS will be enabled */
905 x86_init.iommu.iommu_init = intel_iommu_init;
909 acpi_put_table(dmar_tbl);
912 up_write(&dmar_global_lock);
914 return ret ? 1 : -ENODEV;
918 static void unmap_iommu(struct intel_iommu *iommu)
921 release_mem_region(iommu->reg_phys, iommu->reg_size);
925 * map_iommu: map the iommu's registers
926 * @iommu: the iommu to map
927 * @phys_addr: the physical address of the base resgister
929 * Memory map the iommu's registers. Start w/ a single page, and
930 * possibly expand if that turns out to be insufficent.
932 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
936 iommu->reg_phys = phys_addr;
937 iommu->reg_size = VTD_PAGE_SIZE;
939 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
940 pr_err("Can't reserve memory\n");
945 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
947 pr_err("Can't map the region\n");
952 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
953 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
955 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
957 warn_invalid_dmar(phys_addr, " returns all ones");
961 /* the registers might be more than one page */
962 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
963 cap_max_fault_reg_offset(iommu->cap));
964 map_size = VTD_PAGE_ALIGN(map_size);
965 if (map_size > iommu->reg_size) {
967 release_mem_region(iommu->reg_phys, iommu->reg_size);
968 iommu->reg_size = map_size;
969 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
971 pr_err("Can't reserve memory\n");
975 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
977 pr_err("Can't map the region\n");
988 release_mem_region(iommu->reg_phys, iommu->reg_size);
993 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
995 iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
996 DMAR_UNITS_SUPPORTED);
997 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
1000 set_bit(iommu->seq_id, dmar_seq_ids);
1001 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1004 return iommu->seq_id;
1007 static void dmar_free_seq_id(struct intel_iommu *iommu)
1009 if (iommu->seq_id >= 0) {
1010 clear_bit(iommu->seq_id, dmar_seq_ids);
1015 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1017 struct intel_iommu *iommu;
1023 if (!drhd->reg_base_addr) {
1024 warn_invalid_dmar(0, "");
1028 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1032 if (dmar_alloc_seq_id(iommu) < 0) {
1033 pr_err("Failed to allocate seq_id\n");
1038 err = map_iommu(iommu, drhd->reg_base_addr);
1040 pr_err("Failed to map %s\n", iommu->name);
1041 goto error_free_seq_id;
1045 agaw = iommu_calculate_agaw(iommu);
1047 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1051 msagaw = iommu_calculate_max_sagaw(iommu);
1053 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1058 iommu->msagaw = msagaw;
1059 iommu->segment = drhd->segment;
1063 ver = readl(iommu->reg + DMAR_VER_REG);
1064 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1066 (unsigned long long)drhd->reg_base_addr,
1067 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1068 (unsigned long long)iommu->cap,
1069 (unsigned long long)iommu->ecap);
1071 /* Reflect status in gcmd */
1072 sts = readl(iommu->reg + DMAR_GSTS_REG);
1073 if (sts & DMA_GSTS_IRES)
1074 iommu->gcmd |= DMA_GCMD_IRE;
1075 if (sts & DMA_GSTS_TES)
1076 iommu->gcmd |= DMA_GCMD_TE;
1077 if (sts & DMA_GSTS_QIES)
1078 iommu->gcmd |= DMA_GCMD_QIE;
1080 raw_spin_lock_init(&iommu->register_lock);
1082 if (intel_iommu_enabled) {
1083 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1089 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1091 err = iommu_device_register(&iommu->iommu);
1096 drhd->iommu = iommu;
1103 dmar_free_seq_id(iommu);
1109 static void free_iommu(struct intel_iommu *iommu)
1111 iommu_device_sysfs_remove(&iommu->iommu);
1112 iommu_device_unregister(&iommu->iommu);
1115 if (iommu->pr_irq) {
1116 free_irq(iommu->pr_irq, iommu);
1117 dmar_free_hwirq(iommu->pr_irq);
1120 free_irq(iommu->irq, iommu);
1121 dmar_free_hwirq(iommu->irq);
1126 free_page((unsigned long)iommu->qi->desc);
1127 kfree(iommu->qi->desc_status);
1134 dmar_free_seq_id(iommu);
1139 * Reclaim all the submitted descriptors which have completed its work.
1141 static inline void reclaim_free_desc(struct q_inval *qi)
1143 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1144 qi->desc_status[qi->free_tail] == QI_ABORT) {
1145 qi->desc_status[qi->free_tail] = QI_FREE;
1146 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1151 static int qi_check_fault(struct intel_iommu *iommu, int index)
1155 struct q_inval *qi = iommu->qi;
1156 int wait_index = (index + 1) % QI_LENGTH;
1158 if (qi->desc_status[wait_index] == QI_ABORT)
1161 fault = readl(iommu->reg + DMAR_FSTS_REG);
1164 * If IQE happens, the head points to the descriptor associated
1165 * with the error. No new descriptors are fetched until the IQE
1168 if (fault & DMA_FSTS_IQE) {
1169 head = readl(iommu->reg + DMAR_IQH_REG);
1170 if ((head >> DMAR_IQ_SHIFT) == index) {
1171 pr_err("VT-d detected invalid descriptor: "
1172 "low=%llx, high=%llx\n",
1173 (unsigned long long)qi->desc[index].low,
1174 (unsigned long long)qi->desc[index].high);
1175 memcpy(&qi->desc[index], &qi->desc[wait_index],
1176 sizeof(struct qi_desc));
1177 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1183 * If ITE happens, all pending wait_desc commands are aborted.
1184 * No new descriptors are fetched until the ITE is cleared.
1186 if (fault & DMA_FSTS_ITE) {
1187 head = readl(iommu->reg + DMAR_IQH_REG);
1188 head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1190 tail = readl(iommu->reg + DMAR_IQT_REG);
1191 tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1193 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1196 if (qi->desc_status[head] == QI_IN_USE)
1197 qi->desc_status[head] = QI_ABORT;
1198 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1199 } while (head != tail);
1201 if (qi->desc_status[wait_index] == QI_ABORT)
1205 if (fault & DMA_FSTS_ICE)
1206 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1212 * Submit the queued invalidation descriptor to the remapping
1213 * hardware unit and wait for its completion.
1215 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1218 struct q_inval *qi = iommu->qi;
1219 struct qi_desc *hw, wait_desc;
1220 int wait_index, index;
1221 unsigned long flags;
1231 raw_spin_lock_irqsave(&qi->q_lock, flags);
1232 while (qi->free_cnt < 3) {
1233 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1235 raw_spin_lock_irqsave(&qi->q_lock, flags);
1238 index = qi->free_head;
1239 wait_index = (index + 1) % QI_LENGTH;
1241 qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1245 wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
1246 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1247 wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
1249 hw[wait_index] = wait_desc;
1251 qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1255 * update the HW tail register indicating the presence of
1258 writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);
1260 while (qi->desc_status[wait_index] != QI_DONE) {
1262 * We will leave the interrupts disabled, to prevent interrupt
1263 * context to queue another cmd while a cmd is already submitted
1264 * and waiting for completion on this cpu. This is to avoid
1265 * a deadlock where the interrupt context can wait indefinitely
1266 * for free slots in the queue.
1268 rc = qi_check_fault(iommu, index);
1272 raw_spin_unlock(&qi->q_lock);
1274 raw_spin_lock(&qi->q_lock);
1277 qi->desc_status[index] = QI_DONE;
1279 reclaim_free_desc(qi);
1280 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1289 * Flush the global interrupt entry cache.
1291 void qi_global_iec(struct intel_iommu *iommu)
1293 struct qi_desc desc;
1295 desc.low = QI_IEC_TYPE;
1298 /* should never fail */
1299 qi_submit_sync(&desc, iommu);
1302 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1305 struct qi_desc desc;
1307 desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1308 | QI_CC_GRAN(type) | QI_CC_TYPE;
1311 qi_submit_sync(&desc, iommu);
1314 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1315 unsigned int size_order, u64 type)
1319 struct qi_desc desc;
1322 if (cap_write_drain(iommu->cap))
1325 if (cap_read_drain(iommu->cap))
1328 desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1329 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1330 desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1331 | QI_IOTLB_AM(size_order);
1333 qi_submit_sync(&desc, iommu);
1336 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
1337 u64 addr, unsigned mask)
1339 struct qi_desc desc;
1342 BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
1343 addr |= (1 << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1344 desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1346 desc.high = QI_DEV_IOTLB_ADDR(addr);
1348 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1351 desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1354 qi_submit_sync(&desc, iommu);
1358 * Disable Queued Invalidation interface.
1360 void dmar_disable_qi(struct intel_iommu *iommu)
1362 unsigned long flags;
1364 cycles_t start_time = get_cycles();
1366 if (!ecap_qis(iommu->ecap))
1369 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1371 sts = readl(iommu->reg + DMAR_GSTS_REG);
1372 if (!(sts & DMA_GSTS_QIES))
1376 * Give a chance to HW to complete the pending invalidation requests.
1378 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1379 readl(iommu->reg + DMAR_IQH_REG)) &&
1380 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1383 iommu->gcmd &= ~DMA_GCMD_QIE;
1384 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1386 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1387 !(sts & DMA_GSTS_QIES), sts);
1389 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1393 * Enable queued invalidation.
1395 static void __dmar_enable_qi(struct intel_iommu *iommu)
1398 unsigned long flags;
1399 struct q_inval *qi = iommu->qi;
1401 qi->free_head = qi->free_tail = 0;
1402 qi->free_cnt = QI_LENGTH;
1404 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1406 /* write zero to the tail reg */
1407 writel(0, iommu->reg + DMAR_IQT_REG);
1409 dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
1411 iommu->gcmd |= DMA_GCMD_QIE;
1412 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1414 /* Make sure hardware complete it */
1415 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1417 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1421 * Enable Queued Invalidation interface. This is a must to support
1422 * interrupt-remapping. Also used by DMA-remapping, which replaces
1423 * register based IOTLB invalidation.
1425 int dmar_enable_qi(struct intel_iommu *iommu)
1428 struct page *desc_page;
1430 if (!ecap_qis(iommu->ecap))
1434 * queued invalidation is already setup and enabled.
1439 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1446 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);
1453 qi->desc = page_address(desc_page);
1455 qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
1456 if (!qi->desc_status) {
1457 free_page((unsigned long) qi->desc);
1463 raw_spin_lock_init(&qi->q_lock);
1465 __dmar_enable_qi(iommu);
1470 /* iommu interrupt handling. Most stuff are MSI-like. */
1478 static const char *dma_remap_fault_reasons[] =
1481 "Present bit in root entry is clear",
1482 "Present bit in context entry is clear",
1483 "Invalid context entry",
1484 "Access beyond MGAW",
1485 "PTE Write access is not set",
1486 "PTE Read access is not set",
1487 "Next page table ptr is invalid",
1488 "Root table address invalid",
1489 "Context table ptr is invalid",
1490 "non-zero reserved fields in RTP",
1491 "non-zero reserved fields in CTP",
1492 "non-zero reserved fields in PTE",
1493 "PCE for translation request specifies blocking",
1496 static const char *irq_remap_fault_reasons[] =
1498 "Detected reserved fields in the decoded interrupt-remapped request",
1499 "Interrupt index exceeded the interrupt-remapping table size",
1500 "Present field in the IRTE entry is clear",
1501 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1502 "Detected reserved fields in the IRTE entry",
1503 "Blocked a compatibility format interrupt request",
1504 "Blocked an interrupt request due to source-id verification failure",
1507 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1509 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1510 ARRAY_SIZE(irq_remap_fault_reasons))) {
1511 *fault_type = INTR_REMAP;
1512 return irq_remap_fault_reasons[fault_reason - 0x20];
1513 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1514 *fault_type = DMA_REMAP;
1515 return dma_remap_fault_reasons[fault_reason];
1517 *fault_type = UNKNOWN;
1523 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1525 if (iommu->irq == irq)
1526 return DMAR_FECTL_REG;
1527 else if (iommu->pr_irq == irq)
1528 return DMAR_PECTL_REG;
1533 void dmar_msi_unmask(struct irq_data *data)
1535 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1536 int reg = dmar_msi_reg(iommu, data->irq);
1540 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1541 writel(0, iommu->reg + reg);
1542 /* Read a reg to force flush the post write */
1543 readl(iommu->reg + reg);
1544 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1547 void dmar_msi_mask(struct irq_data *data)
1549 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1550 int reg = dmar_msi_reg(iommu, data->irq);
1554 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1555 writel(DMA_FECTL_IM, iommu->reg + reg);
1556 /* Read a reg to force flush the post write */
1557 readl(iommu->reg + reg);
1558 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1561 void dmar_msi_write(int irq, struct msi_msg *msg)
1563 struct intel_iommu *iommu = irq_get_handler_data(irq);
1564 int reg = dmar_msi_reg(iommu, irq);
1567 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1568 writel(msg->data, iommu->reg + reg + 4);
1569 writel(msg->address_lo, iommu->reg + reg + 8);
1570 writel(msg->address_hi, iommu->reg + reg + 12);
1571 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1574 void dmar_msi_read(int irq, struct msi_msg *msg)
1576 struct intel_iommu *iommu = irq_get_handler_data(irq);
1577 int reg = dmar_msi_reg(iommu, irq);
1580 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1581 msg->data = readl(iommu->reg + reg + 4);
1582 msg->address_lo = readl(iommu->reg + reg + 8);
1583 msg->address_hi = readl(iommu->reg + reg + 12);
1584 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1587 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1588 u8 fault_reason, u16 source_id, unsigned long long addr)
1593 reason = dmar_get_fault_reason(fault_reason, &fault_type);
1595 if (fault_type == INTR_REMAP)
1596 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1597 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1598 PCI_FUNC(source_id & 0xFF), addr >> 48,
1599 fault_reason, reason);
1601 pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n",
1602 type ? "DMA Read" : "DMA Write",
1603 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1604 PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
1608 #define PRIMARY_FAULT_REG_LEN (16)
1609 irqreturn_t dmar_fault(int irq, void *dev_id)
1611 struct intel_iommu *iommu = dev_id;
1612 int reg, fault_index;
1616 static DEFINE_RATELIMIT_STATE(rs,
1617 DEFAULT_RATELIMIT_INTERVAL,
1618 DEFAULT_RATELIMIT_BURST);
1620 /* Disable printing, simply clear the fault when ratelimited */
1621 ratelimited = !__ratelimit(&rs);
1623 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1624 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1625 if (fault_status && !ratelimited)
1626 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1628 /* TBD: ignore advanced fault log currently */
1629 if (!(fault_status & DMA_FSTS_PPF))
1632 fault_index = dma_fsts_fault_record_index(fault_status);
1633 reg = cap_fault_reg_offset(iommu->cap);
1641 /* highest 32 bits */
1642 data = readl(iommu->reg + reg +
1643 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1644 if (!(data & DMA_FRCD_F))
1648 fault_reason = dma_frcd_fault_reason(data);
1649 type = dma_frcd_type(data);
1651 data = readl(iommu->reg + reg +
1652 fault_index * PRIMARY_FAULT_REG_LEN + 8);
1653 source_id = dma_frcd_source_id(data);
1655 guest_addr = dmar_readq(iommu->reg + reg +
1656 fault_index * PRIMARY_FAULT_REG_LEN);
1657 guest_addr = dma_frcd_page_addr(guest_addr);
1660 /* clear the fault */
1661 writel(DMA_FRCD_F, iommu->reg + reg +
1662 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1664 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1667 dmar_fault_do_one(iommu, type, fault_reason,
1668 source_id, guest_addr);
1671 if (fault_index >= cap_num_fault_regs(iommu->cap))
1673 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1676 writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG);
1679 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1683 int dmar_set_interrupt(struct intel_iommu *iommu)
1688 * Check if the fault interrupt is already initialized.
1693 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1697 pr_err("No free IRQ vectors\n");
1701 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1703 pr_err("Can't request irq\n");
1707 int __init enable_drhd_fault_handling(void)
1709 struct dmar_drhd_unit *drhd;
1710 struct intel_iommu *iommu;
1713 * Enable fault control interrupt.
1715 for_each_iommu(iommu, drhd) {
1717 int ret = dmar_set_interrupt(iommu);
1720 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1721 (unsigned long long)drhd->reg_base_addr, ret);
1726 * Clear any previous faults.
1728 dmar_fault(iommu->irq, iommu);
1729 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1730 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1737 * Re-enable Queued Invalidation interface.
1739 int dmar_reenable_qi(struct intel_iommu *iommu)
1741 if (!ecap_qis(iommu->ecap))
1748 * First disable queued invalidation.
1750 dmar_disable_qi(iommu);
1752 * Then enable queued invalidation again. Since there is no pending
1753 * invalidation requests now, it's safe to re-enable queued
1756 __dmar_enable_qi(iommu);
1762 * Check interrupt remapping support in DMAR table description.
1764 int __init dmar_ir_support(void)
1766 struct acpi_table_dmar *dmar;
1767 dmar = (struct acpi_table_dmar *)dmar_tbl;
1770 return dmar->flags & 0x1;
1773 /* Check whether DMAR units are in use */
1774 static inline bool dmar_in_use(void)
1776 return irq_remapping_enabled || intel_iommu_enabled;
1779 static int __init dmar_free_unused_resources(void)
1781 struct dmar_drhd_unit *dmaru, *dmaru_n;
1786 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1787 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1789 down_write(&dmar_global_lock);
1790 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1791 list_del(&dmaru->list);
1792 dmar_free_drhd(dmaru);
1794 up_write(&dmar_global_lock);
1799 late_initcall(dmar_free_unused_resources);
1800 IOMMU_INIT_POST(detect_intel_iommu);
1803 * DMAR Hotplug Support
1804 * For more details, please refer to Intel(R) Virtualization Technology
1805 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1806 * "Remapping Hardware Unit Hot Plug".
1808 static u8 dmar_hp_uuid[] = {
1809 /* 0000 */ 0xA6, 0xA3, 0xC1, 0xD8, 0x9B, 0xBE, 0x9B, 0x4C,
1810 /* 0008 */ 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF
1814 * Currently there's only one revision and BIOS will not check the revision id,
1815 * so use 0 for safety.
1817 #define DMAR_DSM_REV_ID 0
1818 #define DMAR_DSM_FUNC_DRHD 1
1819 #define DMAR_DSM_FUNC_ATSR 2
1820 #define DMAR_DSM_FUNC_RHSA 3
1822 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1824 return acpi_check_dsm(handle, dmar_hp_uuid, DMAR_DSM_REV_ID, 1 << func);
1827 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1828 dmar_res_handler_t handler, void *arg)
1831 union acpi_object *obj;
1832 struct acpi_dmar_header *start;
1833 struct dmar_res_callback callback;
1834 static int res_type[] = {
1835 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1836 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1837 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1840 if (!dmar_detect_dsm(handle, func))
1843 obj = acpi_evaluate_dsm_typed(handle, dmar_hp_uuid, DMAR_DSM_REV_ID,
1844 func, NULL, ACPI_TYPE_BUFFER);
1848 memset(&callback, 0, sizeof(callback));
1849 callback.cb[res_type[func]] = handler;
1850 callback.arg[res_type[func]] = arg;
1851 start = (struct acpi_dmar_header *)obj->buffer.pointer;
1852 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1859 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
1862 struct dmar_drhd_unit *dmaru;
1864 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1868 ret = dmar_ir_hotplug(dmaru, true);
1870 ret = dmar_iommu_hotplug(dmaru, true);
1875 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
1879 struct dmar_drhd_unit *dmaru;
1881 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1886 * All PCI devices managed by this unit should have been destroyed.
1888 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
1889 for_each_active_dev_scope(dmaru->devices,
1890 dmaru->devices_cnt, i, dev)
1894 ret = dmar_ir_hotplug(dmaru, false);
1896 ret = dmar_iommu_hotplug(dmaru, false);
1901 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
1903 struct dmar_drhd_unit *dmaru;
1905 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1907 list_del_rcu(&dmaru->list);
1909 dmar_free_drhd(dmaru);
1915 static int dmar_hotplug_insert(acpi_handle handle)
1920 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1921 &dmar_validate_one_drhd, (void *)1);
1925 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1926 &dmar_parse_one_drhd, (void *)&drhd_count);
1927 if (ret == 0 && drhd_count == 0) {
1928 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
1934 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
1935 &dmar_parse_one_rhsa, NULL);
1939 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1940 &dmar_parse_one_atsr, NULL);
1944 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1945 &dmar_hp_add_drhd, NULL);
1949 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1950 &dmar_hp_remove_drhd, NULL);
1952 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1953 &dmar_release_one_atsr, NULL);
1955 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1956 &dmar_hp_release_drhd, NULL);
1961 static int dmar_hotplug_remove(acpi_handle handle)
1965 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1966 &dmar_check_one_atsr, NULL);
1970 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1971 &dmar_hp_remove_drhd, NULL);
1973 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1974 &dmar_release_one_atsr, NULL));
1975 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1976 &dmar_hp_release_drhd, NULL));
1978 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1979 &dmar_hp_add_drhd, NULL);
1985 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
1986 void *context, void **retval)
1988 acpi_handle *phdl = retval;
1990 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
1992 return AE_CTRL_TERMINATE;
1998 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2001 acpi_handle tmp = NULL;
2007 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2010 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2012 dmar_get_dsm_handle,
2014 if (ACPI_FAILURE(status)) {
2015 pr_warn("Failed to locate _DSM method.\n");
2022 down_write(&dmar_global_lock);
2024 ret = dmar_hotplug_insert(tmp);
2026 ret = dmar_hotplug_remove(tmp);
2027 up_write(&dmar_global_lock);
2032 int dmar_device_add(acpi_handle handle)
2034 return dmar_device_hotplug(handle, true);
2037 int dmar_device_remove(acpi_handle handle)
2039 return dmar_device_hotplug(handle, false);