drivers/iommu/exynos-iommu.c

   1 /* linux/drivers/iommu/exynos_iommu.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  12 #define DEBUG
  13 #endif
  14
  15 #include <linux/io.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/clk.h>
  21 #include <linux/err.h>
  22 #include <linux/mm.h>
  23 #include <linux/iommu.h>
  24 #include <linux/errno.h>
  25 #include <linux/list.h>
  26 #include <linux/memblock.h>
  27 #include <linux/export.h>
  28
  29 #include <asm/cacheflush.h>
  30 #include <asm/pgtable.h>
  31
  32 typedef u32 sysmmu_iova_t;
  33 typedef u32 sysmmu_pte_t;
  34
  35 /* We does not consider super section mapping (16MB) */
  36 #define SECT_ORDER 20
  37 #define LPAGE_ORDER 16
  38 #define SPAGE_ORDER 12
  39
  40 #define SECT_SIZE (1 << SECT_ORDER)
  41 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  42 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  43
  44 #define SECT_MASK (~(SECT_SIZE - 1))
  45 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  46 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  47
  48 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  49                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  50 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  51 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  52 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  53                           ((*(sent) & 3) == 1))
  54 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  55
  56 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  57 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  58 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  59
  60 static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
  61 {
  62         return iova & (size - 1);
  63 }
  64
  65 #define section_phys(sent) (*(sent) & SECT_MASK)
  66 #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
  67 #define lpage_phys(pent) (*(pent) & LPAGE_MASK)
  68 #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
  69 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  70 #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
  71
  72 #define NUM_LV1ENTRIES 4096
  73 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  74
  75 static u32 lv1ent_offset(sysmmu_iova_t iova)
  76 {
  77         return iova >> SECT_ORDER;
  78 }
  79
  80 static u32 lv2ent_offset(sysmmu_iova_t iova)
  81 {
  82         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  83 }
  84
  85 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  86
  87 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  88
  89 #define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
  90
  91 #define mk_lv1ent_sect(pa) ((pa) | 2)
  92 #define mk_lv1ent_page(pa) ((pa) | 1)
  93 #define mk_lv2ent_lpage(pa) ((pa) | 1)
  94 #define mk_lv2ent_spage(pa) ((pa) | 2)
  95
  96 #define CTRL_ENABLE     0x5
  97 #define CTRL_BLOCK      0x7
  98 #define CTRL_DISABLE    0x0
  99
 100 #define CFG_LRU         0x1
 101 #define CFG_QOS(n)      ((n & 0xF) << 7)
 102 #define CFG_MASK        0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
 103 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 104 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 105 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 106
 107 #define REG_MMU_CTRL            0x000
 108 #define REG_MMU_CFG             0x004
 109 #define REG_MMU_STATUS          0x008
 110 #define REG_MMU_FLUSH           0x00C
 111 #define REG_MMU_FLUSH_ENTRY     0x010
 112 #define REG_PT_BASE_ADDR        0x014
 113 #define REG_INT_STATUS          0x018
 114 #define REG_INT_CLEAR           0x01C
 115
 116 #define REG_PAGE_FAULT_ADDR     0x024
 117 #define REG_AW_FAULT_ADDR       0x028
 118 #define REG_AR_FAULT_ADDR       0x02C
 119 #define REG_DEFAULT_SLAVE_ADDR  0x030
 120
 121 #define REG_MMU_VERSION         0x034
 122
 123 #define MMU_MAJ_VER(val)        ((val) >> 7)
 124 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 125 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 126
 127 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 128
 129 #define REG_PB0_SADDR           0x04C
 130 #define REG_PB0_EADDR           0x050
 131 #define REG_PB1_SADDR           0x054
 132 #define REG_PB1_EADDR           0x058
 133
 134 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 135
 136 static struct kmem_cache *lv2table_kmem_cache;
 137 static sysmmu_pte_t *zero_lv2_table;
 138 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 139
 140 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 141 {
 142         return pgtable + lv1ent_offset(iova);
 143 }
 144
 145 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 146 {
 147         return (sysmmu_pte_t *)phys_to_virt(
 148                                 lv2table_base(sent)) + lv2ent_offset(iova);
 149 }
 150
 151 enum exynos_sysmmu_inttype {
 152         SYSMMU_PAGEFAULT,
 153         SYSMMU_AR_MULTIHIT,
 154         SYSMMU_AW_MULTIHIT,
 155         SYSMMU_BUSERROR,
 156         SYSMMU_AR_SECURITY,
 157         SYSMMU_AR_ACCESS,
 158         SYSMMU_AW_SECURITY,
 159         SYSMMU_AW_PROTECTION, /* 7 */
 160         SYSMMU_FAULT_UNKNOWN,
 161         SYSMMU_FAULTS_NUM
 162 };
 163
 164 static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
 165         REG_PAGE_FAULT_ADDR,
 166         REG_AR_FAULT_ADDR,
 167         REG_AW_FAULT_ADDR,
 168         REG_DEFAULT_SLAVE_ADDR,
 169         REG_AR_FAULT_ADDR,
 170         REG_AR_FAULT_ADDR,
 171         REG_AW_FAULT_ADDR,
 172         REG_AW_FAULT_ADDR
 173 };
 174
 175 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
 176         "PAGE FAULT",
 177         "AR MULTI-HIT FAULT",
 178         "AW MULTI-HIT FAULT",
 179         "BUS ERROR",
 180         "AR SECURITY PROTECTION FAULT",
 181         "AR ACCESS PROTECTION FAULT",
 182         "AW SECURITY PROTECTION FAULT",
 183         "AW ACCESS PROTECTION FAULT",
 184         "UNKNOWN FAULT"
 185 };
 186
 187 /* attached to dev.archdata.iommu of the master device */
 188 struct exynos_iommu_owner {
 189         struct list_head client; /* entry of exynos_iommu_domain.clients */
 190         struct device *dev;
 191         struct device *sysmmu;
 192         struct iommu_domain *domain;
 193         void *vmm_data;         /* IO virtual memory manager's data */
 194         spinlock_t lock;        /* Lock to preserve consistency of System MMU */
 195 };
 196
 197 struct exynos_iommu_domain {
 198         struct list_head clients; /* list of sysmmu_drvdata.node */
 199         sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
 200         short *lv2entcnt; /* free lv2 entry counter for each section */
 201         spinlock_t lock; /* lock for this structure */
 202         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 203 };
 204
 205 struct sysmmu_drvdata {
 206         struct device *sysmmu;  /* System MMU's device descriptor */
 207         struct device *master;  /* Owner of system MMU */
 208         void __iomem *sfrbase;
 209         struct clk *clk;
 210         struct clk *clk_master;
 211         int activations;
 212         spinlock_t lock;
 213         struct iommu_domain *domain;
 214         phys_addr_t pgtable;
 215 };
 216
 217 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 218 {
 219         /* return true if the System MMU was not active previously
 220            and it needs to be initialized */
 221         return ++data->activations == 1;
 222 }
 223
 224 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 225 {
 226         /* return true if the System MMU is needed to be disabled */
 227         BUG_ON(data->activations < 1);
 228         return --data->activations == 0;
 229 }
 230
 231 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 232 {
 233         return data->activations > 0;
 234 }
 235
 236 static void sysmmu_unblock(void __iomem *sfrbase)
 237 {
 238         __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
 239 }
 240
 241 static unsigned int __raw_sysmmu_version(struct sysmmu_drvdata *data)
 242 {
 243         return MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
 244 }
 245
 246 static bool sysmmu_block(void __iomem *sfrbase)
 247 {
 248         int i = 120;
 249
 250         __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
 251         while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
 252                 --i;
 253
 254         if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
 255                 sysmmu_unblock(sfrbase);
 256                 return false;
 257         }
 258
 259         return true;
 260 }
 261
 262 static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
 263 {
 264         __raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
 265 }
 266
 267 static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
 268                                 sysmmu_iova_t iova, unsigned int num_inv)
 269 {
 270         unsigned int i;
 271         for (i = 0; i < num_inv; i++) {
 272                 __raw_writel((iova & SPAGE_MASK) | 1,
 273                                 sfrbase + REG_MMU_FLUSH_ENTRY);
 274                 iova += SPAGE_SIZE;
 275         }
 276 }
 277
 278 static void __sysmmu_set_ptbase(void __iomem *sfrbase,
 279                                        phys_addr_t pgd)
 280 {
 281         __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
 282
 283         __sysmmu_tlb_invalidate(sfrbase);
 284 }
 285
 286 static void show_fault_information(const char *name,
 287                 enum exynos_sysmmu_inttype itype,
 288                 phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
 289 {
 290         sysmmu_pte_t *ent;
 291
 292         if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
 293                 itype = SYSMMU_FAULT_UNKNOWN;
 294
 295         pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
 296                 sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
 297
 298         ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
 299         pr_err("\tLv1 entry: %#x\n", *ent);
 300
 301         if (lv1ent_page(ent)) {
 302                 ent = page_entry(ent, fault_addr);
 303                 pr_err("\t Lv2 entry: %#x\n", *ent);
 304         }
 305 }
 306
 307 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 308 {
 309         /* SYSMMU is in blocked when interrupt occurred. */
 310         struct sysmmu_drvdata *data = dev_id;
 311         enum exynos_sysmmu_inttype itype;
 312         sysmmu_iova_t addr = -1;
 313         int ret = -ENOSYS;
 314
 315         WARN_ON(!is_sysmmu_active(data));
 316
 317         spin_lock(&data->lock);
 318
 319         if (!IS_ERR(data->clk_master))
 320                 clk_enable(data->clk_master);
 321
 322         itype = (enum exynos_sysmmu_inttype)
 323                 __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
 324         if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
 325                 itype = SYSMMU_FAULT_UNKNOWN;
 326         else
 327                 addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
 328
 329         if (itype == SYSMMU_FAULT_UNKNOWN) {
 330                 pr_err("%s: Fault is not occurred by System MMU '%s'!\n",
 331                         __func__, dev_name(data->sysmmu));
 332                 pr_err("%s: Please check if IRQ is correctly configured.\n",
 333                         __func__);
 334                 BUG();
 335         } else {
 336                 unsigned int base =
 337                                 __raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
 338                 show_fault_information(dev_name(data->sysmmu),
 339                                         itype, base, addr);
 340                 if (data->domain)
 341                         ret = report_iommu_fault(data->domain,
 342                                         data->master, addr, itype);
 343         }
 344
 345         /* fault is not recovered by fault handler */
 346         BUG_ON(ret != 0);
 347
 348         __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
 349
 350         sysmmu_unblock(data->sfrbase);
 351
 352         if (!IS_ERR(data->clk_master))
 353                 clk_disable(data->clk_master);
 354
 355         spin_unlock(&data->lock);
 356
 357         return IRQ_HANDLED;
 358 }
 359
 360 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 361 {
 362         if (!IS_ERR(data->clk_master))
 363                 clk_enable(data->clk_master);
 364
 365         __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 366         __raw_writel(0, data->sfrbase + REG_MMU_CFG);
 367
 368         clk_disable(data->clk);
 369         if (!IS_ERR(data->clk_master))
 370                 clk_disable(data->clk_master);
 371 }
 372
 373 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 374 {
 375         bool disabled;
 376         unsigned long flags;
 377
 378         spin_lock_irqsave(&data->lock, flags);
 379
 380         disabled = set_sysmmu_inactive(data);
 381
 382         if (disabled) {
 383                 data->pgtable = 0;
 384                 data->domain = NULL;
 385
 386                 __sysmmu_disable_nocount(data);
 387
 388                 dev_dbg(data->sysmmu, "Disabled\n");
 389         } else  {
 390                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 391                                         data->activations);
 392         }
 393
 394         spin_unlock_irqrestore(&data->lock, flags);
 395
 396         return disabled;
 397 }
 398
 399 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 400 {
 401         unsigned int cfg = CFG_LRU | CFG_QOS(15);
 402         unsigned int ver;
 403
 404         ver = __raw_sysmmu_version(data);
 405         if (MMU_MAJ_VER(ver) == 3) {
 406                 if (MMU_MIN_VER(ver) >= 2) {
 407                         cfg |= CFG_FLPDCACHE;
 408                         if (MMU_MIN_VER(ver) == 3) {
 409                                 cfg |= CFG_ACGEN;
 410                                 cfg &= ~CFG_LRU;
 411                         } else {
 412                                 cfg |= CFG_SYSSEL;
 413                         }
 414                 }
 415         }
 416
 417         __raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
 418 }
 419
 420 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 421 {
 422         if (!IS_ERR(data->clk_master))
 423                 clk_enable(data->clk_master);
 424         clk_enable(data->clk);
 425
 426         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 427
 428         __sysmmu_init_config(data);
 429
 430         __sysmmu_set_ptbase(data->sfrbase, data->pgtable);
 431
 432         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 433
 434         if (!IS_ERR(data->clk_master))
 435                 clk_disable(data->clk_master);
 436 }
 437
 438 static int __sysmmu_enable(struct sysmmu_drvdata *data,
 439                         phys_addr_t pgtable, struct iommu_domain *domain)
 440 {
 441         int ret = 0;
 442         unsigned long flags;
 443
 444         spin_lock_irqsave(&data->lock, flags);
 445         if (set_sysmmu_active(data)) {
 446                 data->pgtable = pgtable;
 447                 data->domain = domain;
 448
 449                 __sysmmu_enable_nocount(data);
 450
 451                 dev_dbg(data->sysmmu, "Enabled\n");
 452         } else {
 453                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 454
 455                 dev_dbg(data->sysmmu, "already enabled\n");
 456         }
 457
 458         if (WARN_ON(ret < 0))
 459                 set_sysmmu_inactive(data); /* decrement count */
 460
 461         spin_unlock_irqrestore(&data->lock, flags);
 462
 463         return ret;
 464 }
 465
 466 /* __exynos_sysmmu_enable: Enables System MMU
 467  *
 468  * returns -error if an error occurred and System MMU is not enabled,
 469  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 470  * enabled before.
 471  */
 472 static int __exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable,
 473                                   struct iommu_domain *domain)
 474 {
 475         int ret = 0;
 476         unsigned long flags;
 477         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 478         struct sysmmu_drvdata *data;
 479
 480         BUG_ON(!has_sysmmu(dev));
 481
 482         spin_lock_irqsave(&owner->lock, flags);
 483
 484         data = dev_get_drvdata(owner->sysmmu);
 485
 486         ret = __sysmmu_enable(data, pgtable, domain);
 487         if (ret >= 0)
 488                 data->master = dev;
 489
 490         spin_unlock_irqrestore(&owner->lock, flags);
 491
 492         return ret;
 493 }
 494
 495 int exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable)
 496 {
 497         BUG_ON(!memblock_is_memory(pgtable));
 498
 499         return __exynos_sysmmu_enable(dev, pgtable, NULL);
 500 }
 501
 502 static bool exynos_sysmmu_disable(struct device *dev)
 503 {
 504         unsigned long flags;
 505         bool disabled = true;
 506         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 507         struct sysmmu_drvdata *data;
 508
 509         BUG_ON(!has_sysmmu(dev));
 510
 511         spin_lock_irqsave(&owner->lock, flags);
 512
 513         data = dev_get_drvdata(owner->sysmmu);
 514
 515         disabled = __sysmmu_disable(data);
 516         if (disabled)
 517                 data->master = NULL;
 518
 519         spin_unlock_irqrestore(&owner->lock, flags);
 520
 521         return disabled;
 522 }
 523
 524 static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 525                                               sysmmu_iova_t iova)
 526 {
 527         if (__raw_sysmmu_version(data) == MAKE_MMU_VER(3, 3))
 528                 __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY);
 529 }
 530
 531 static void sysmmu_tlb_invalidate_flpdcache(struct device *dev,
 532                                             sysmmu_iova_t iova)
 533 {
 534         unsigned long flags;
 535         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 536         struct sysmmu_drvdata *data = dev_get_drvdata(owner->sysmmu);
 537
 538         if (!IS_ERR(data->clk_master))
 539                 clk_enable(data->clk_master);
 540
 541         spin_lock_irqsave(&data->lock, flags);
 542         if (is_sysmmu_active(data))
 543                 __sysmmu_tlb_invalidate_flpdcache(data, iova);
 544         spin_unlock_irqrestore(&data->lock, flags);
 545
 546         if (!IS_ERR(data->clk_master))
 547                 clk_disable(data->clk_master);
 548 }
 549
 550 static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
 551                                         size_t size)
 552 {
 553         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 554         unsigned long flags;
 555         struct sysmmu_drvdata *data;
 556
 557         data = dev_get_drvdata(owner->sysmmu);
 558
 559         spin_lock_irqsave(&data->lock, flags);
 560         if (is_sysmmu_active(data)) {
 561                 unsigned int num_inv = 1;
 562
 563                 if (!IS_ERR(data->clk_master))
 564                         clk_enable(data->clk_master);
 565
 566                 /*
 567                  * L2TLB invalidation required
 568                  * 4KB page: 1 invalidation
 569                  * 64KB page: 16 invalidation
 570                  * 1MB page: 64 invalidation
 571                  * because it is set-associative TLB
 572                  * with 8-way and 64 sets.
 573                  * 1MB page can be cached in one of all sets.
 574                  * 64KB page can be one of 16 consecutive sets.
 575                  */
 576                 if (MMU_MAJ_VER(__raw_sysmmu_version(data)) == 2)
 577                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 578
 579                 if (sysmmu_block(data->sfrbase)) {
 580                         __sysmmu_tlb_invalidate_entry(
 581                                 data->sfrbase, iova, num_inv);
 582                         sysmmu_unblock(data->sfrbase);
 583                 }
 584                 if (!IS_ERR(data->clk_master))
 585                         clk_disable(data->clk_master);
 586         } else {
 587                 dev_dbg(dev, "disabled. Skipping TLB invalidation @ %#x\n",
 588                         iova);
 589         }
 590         spin_unlock_irqrestore(&data->lock, flags);
 591 }
 592
 593 void exynos_sysmmu_tlb_invalidate(struct device *dev)
 594 {
 595         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 596         unsigned long flags;
 597         struct sysmmu_drvdata *data;
 598
 599         data = dev_get_drvdata(owner->sysmmu);
 600
 601         spin_lock_irqsave(&data->lock, flags);
 602         if (is_sysmmu_active(data)) {
 603                 if (!IS_ERR(data->clk_master))
 604                         clk_enable(data->clk_master);
 605                 if (sysmmu_block(data->sfrbase)) {
 606                         __sysmmu_tlb_invalidate(data->sfrbase);
 607                         sysmmu_unblock(data->sfrbase);
 608                 }
 609                 if (!IS_ERR(data->clk_master))
 610                         clk_disable(data->clk_master);
 611         } else {
 612                 dev_dbg(dev, "disabled. Skipping TLB invalidation\n");
 613         }
 614         spin_unlock_irqrestore(&data->lock, flags);
 615 }
 616
 617 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 618 {
 619         int irq, ret;
 620         struct device *dev = &pdev->dev;
 621         struct sysmmu_drvdata *data;
 622         struct resource *res;
 623
 624         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 625         if (!data)
 626                 return -ENOMEM;
 627
 628         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 629         data->sfrbase = devm_ioremap_resource(dev, res);
 630         if (IS_ERR(data->sfrbase))
 631                 return PTR_ERR(data->sfrbase);
 632
 633         irq = platform_get_irq(pdev, 0);
 634         if (irq <= 0) {
 635                 dev_err(dev, "Unable to find IRQ resource\n");
 636                 return irq;
 637         }
 638
 639         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 640                                 dev_name(dev), data);
 641         if (ret) {
 642                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 643                 return ret;
 644         }
 645
 646         data->clk = devm_clk_get(dev, "sysmmu");
 647         if (IS_ERR(data->clk)) {
 648                 dev_err(dev, "Failed to get clock!\n");
 649                 return PTR_ERR(data->clk);
 650         } else  {
 651                 ret = clk_prepare(data->clk);
 652                 if (ret) {
 653                         dev_err(dev, "Failed to prepare clk\n");
 654                         return ret;
 655                 }
 656         }
 657
 658         data->clk_master = devm_clk_get(dev, "master");
 659         if (!IS_ERR(data->clk_master)) {
 660                 ret = clk_prepare(data->clk_master);
 661                 if (ret) {
 662                         clk_unprepare(data->clk);
 663                         dev_err(dev, "Failed to prepare master's clk\n");
 664                         return ret;
 665                 }
 666         }
 667
 668         data->sysmmu = dev;
 669         spin_lock_init(&data->lock);
 670
 671         platform_set_drvdata(pdev, data);
 672
 673         pm_runtime_enable(dev);
 674
 675         return 0;
 676 }
 677
 678 static const struct of_device_id sysmmu_of_match[] __initconst = {
 679         { .compatible   = "samsung,exynos-sysmmu", },
 680         { },
 681 };
 682
 683 static struct platform_driver exynos_sysmmu_driver __refdata = {
 684         .probe  = exynos_sysmmu_probe,
 685         .driver = {
 686                 .owner          = THIS_MODULE,
 687                 .name           = "exynos-sysmmu",
 688                 .of_match_table = sysmmu_of_match,
 689         }
 690 };
 691
 692 static inline void pgtable_flush(void *vastart, void *vaend)
 693 {
 694         dmac_flush_range(vastart, vaend);
 695         outer_flush_range(virt_to_phys(vastart),
 696                                 virt_to_phys(vaend));
 697 }
 698
 699 static int exynos_iommu_domain_init(struct iommu_domain *domain)
 700 {
 701         struct exynos_iommu_domain *priv;
 702         int i;
 703
 704         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 705         if (!priv)
 706                 return -ENOMEM;
 707
 708         priv->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 709         if (!priv->pgtable)
 710                 goto err_pgtable;
 711
 712         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 713         if (!priv->lv2entcnt)
 714                 goto err_counter;
 715
 716         /* w/a of System MMU v3.3 to prevent caching 1MiB mapping */
 717         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 718                 priv->pgtable[i + 0] = ZERO_LV2LINK;
 719                 priv->pgtable[i + 1] = ZERO_LV2LINK;
 720                 priv->pgtable[i + 2] = ZERO_LV2LINK;
 721                 priv->pgtable[i + 3] = ZERO_LV2LINK;
 722                 priv->pgtable[i + 4] = ZERO_LV2LINK;
 723                 priv->pgtable[i + 5] = ZERO_LV2LINK;
 724                 priv->pgtable[i + 6] = ZERO_LV2LINK;
 725                 priv->pgtable[i + 7] = ZERO_LV2LINK;
 726         }
 727
 728         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
 729
 730         spin_lock_init(&priv->lock);
 731         spin_lock_init(&priv->pgtablelock);
 732         INIT_LIST_HEAD(&priv->clients);
 733
 734         domain->geometry.aperture_start = 0;
 735         domain->geometry.aperture_end   = ~0UL;
 736         domain->geometry.force_aperture = true;
 737
 738         domain->priv = priv;
 739         return 0;
 740
 741 err_counter:
 742         free_pages((unsigned long)priv->pgtable, 2);
 743 err_pgtable:
 744         kfree(priv);
 745         return -ENOMEM;
 746 }
 747
 748 static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
 749 {
 750         struct exynos_iommu_domain *priv = domain->priv;
 751         struct exynos_iommu_owner *owner;
 752         unsigned long flags;
 753         int i;
 754
 755         WARN_ON(!list_empty(&priv->clients));
 756
 757         spin_lock_irqsave(&priv->lock, flags);
 758
 759         list_for_each_entry(owner, &priv->clients, client) {
 760                 while (!exynos_sysmmu_disable(owner->dev))
 761                         ; /* until System MMU is actually disabled */
 762         }
 763
 764         while (!list_empty(&priv->clients))
 765                 list_del_init(priv->clients.next);
 766
 767         spin_unlock_irqrestore(&priv->lock, flags);
 768
 769         for (i = 0; i < NUM_LV1ENTRIES; i++)
 770                 if (lv1ent_page(priv->pgtable + i))
 771                         kmem_cache_free(lv2table_kmem_cache,
 772                                 phys_to_virt(lv2table_base(priv->pgtable + i)));
 773
 774         free_pages((unsigned long)priv->pgtable, 2);
 775         free_pages((unsigned long)priv->lv2entcnt, 1);
 776         kfree(domain->priv);
 777         domain->priv = NULL;
 778 }
 779
 780 static int exynos_iommu_attach_device(struct iommu_domain *domain,
 781                                    struct device *dev)
 782 {
 783         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 784         struct exynos_iommu_domain *priv = domain->priv;
 785         phys_addr_t pagetable = virt_to_phys(priv->pgtable);
 786         unsigned long flags;
 787         int ret;
 788
 789         spin_lock_irqsave(&priv->lock, flags);
 790
 791         ret = __exynos_sysmmu_enable(dev, pagetable, domain);
 792         if (ret == 0) {
 793                 list_add_tail(&owner->client, &priv->clients);
 794                 owner->domain = domain;
 795         }
 796
 797         spin_unlock_irqrestore(&priv->lock, flags);
 798
 799         if (ret < 0) {
 800                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 801                                         __func__, &pagetable);
 802                 return ret;
 803         }
 804
 805         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 806                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 807
 808         return ret;
 809 }
 810
 811 static void exynos_iommu_detach_device(struct iommu_domain *domain,
 812                                     struct device *dev)
 813 {
 814         struct exynos_iommu_owner *owner;
 815         struct exynos_iommu_domain *priv = domain->priv;
 816         phys_addr_t pagetable = virt_to_phys(priv->pgtable);
 817         unsigned long flags;
 818
 819         spin_lock_irqsave(&priv->lock, flags);
 820
 821         list_for_each_entry(owner, &priv->clients, client) {
 822                 if (owner == dev->archdata.iommu) {
 823                         if (exynos_sysmmu_disable(dev)) {
 824                                 list_del_init(&owner->client);
 825                                 owner->domain = NULL;
 826                         }
 827                         break;
 828                 }
 829         }
 830
 831         spin_unlock_irqrestore(&priv->lock, flags);
 832
 833         if (owner == dev->archdata.iommu)
 834                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 835                                         __func__, &pagetable);
 836         else
 837                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 838 }
 839
 840 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *priv,
 841                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 842 {
 843         if (lv1ent_section(sent)) {
 844                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 845                 return ERR_PTR(-EADDRINUSE);
 846         }
 847
 848         if (lv1ent_fault(sent)) {
 849                 sysmmu_pte_t *pent;
 850                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 851
 852                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 853                 BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
 854                 if (!pent)
 855                         return ERR_PTR(-ENOMEM);
 856
 857                 *sent = mk_lv1ent_page(virt_to_phys(pent));
 858                 *pgcounter = NUM_LV2ENTRIES;
 859                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 860                 pgtable_flush(sent, sent + 1);
 861
 862                 /*
 863                  * If pretched SLPD is a fault SLPD in zero_l2_table, FLPD cache
 864                  * may caches the address of zero_l2_table. This function
 865                  * replaces the zero_l2_table with new L2 page table to write
 866                  * valid mappings.
 867                  * Accessing the valid area may cause page fault since FLPD
 868                  * cache may still caches zero_l2_table for the valid area
 869                  * instead of new L2 page table that have the mapping
 870                  * information of the valid area
 871                  * Thus any replacement of zero_l2_table with other valid L2
 872                  * page table must involve FLPD cache invalidation for System
 873                  * MMU v3.3.
 874                  * FLPD cache invalidation is performed with TLB invalidation
 875                  * by VPN without blocking. It is safe to invalidate TLB without
 876                  * blocking because the target address of TLB invalidation is
 877                  * not currently mapped.
 878                  */
 879                 if (need_flush_flpd_cache) {
 880                         struct exynos_iommu_owner *owner;
 881                         spin_lock(&priv->lock);
 882                         list_for_each_entry(owner, &priv->clients, client)
 883                                 sysmmu_tlb_invalidate_flpdcache(
 884                                                         owner->dev, iova);
 885                         spin_unlock(&priv->lock);
 886                 }
 887         }
 888
 889         return page_entry(sent, iova);
 890 }
 891
 892 static int lv1set_section(struct exynos_iommu_domain *priv,
 893                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 894                           phys_addr_t paddr, short *pgcnt)
 895 {
 896         if (lv1ent_section(sent)) {
 897                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 898                         iova);
 899                 return -EADDRINUSE;
 900         }
 901
 902         if (lv1ent_page(sent)) {
 903                 if (*pgcnt != NUM_LV2ENTRIES) {
 904                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 905                                 iova);
 906                         return -EADDRINUSE;
 907                 }
 908
 909                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 910                 *pgcnt = 0;
 911         }
 912
 913         *sent = mk_lv1ent_sect(paddr);
 914
 915         pgtable_flush(sent, sent + 1);
 916
 917         spin_lock(&priv->lock);
 918         if (lv1ent_page_zero(sent)) {
 919                 struct exynos_iommu_owner *owner;
 920                 /*
 921                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 922                  * entry by speculative prefetch of SLPD which has no mapping.
 923                  */
 924                 list_for_each_entry(owner, &priv->clients, client)
 925                         sysmmu_tlb_invalidate_flpdcache(owner->dev, iova);
 926         }
 927         spin_unlock(&priv->lock);
 928
 929         return 0;
 930 }
 931
 932 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 933                                                                 short *pgcnt)
 934 {
 935         if (size == SPAGE_SIZE) {
 936                 if (WARN_ON(!lv2ent_fault(pent)))
 937                         return -EADDRINUSE;
 938
 939                 *pent = mk_lv2ent_spage(paddr);
 940                 pgtable_flush(pent, pent + 1);
 941                 *pgcnt -= 1;
 942         } else { /* size == LPAGE_SIZE */
 943                 int i;
 944                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
 945                         if (WARN_ON(!lv2ent_fault(pent))) {
 946                                 if (i > 0)
 947                                         memset(pent - i, 0, sizeof(*pent) * i);
 948                                 return -EADDRINUSE;
 949                         }
 950
 951                         *pent = mk_lv2ent_lpage(paddr);
 952                 }
 953                 pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
 954                 *pgcnt -= SPAGES_PER_LPAGE;
 955         }
 956
 957         return 0;
 958 }
 959
 960 /*
 961  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
 962  *
 963  * System MMU v3.x have an advanced logic to improve address translation
 964  * performance with caching more page table entries by a page table walk.
 965  * However, the logic has a bug that caching fault page table entries and System
 966  * MMU reports page fault if the cached fault entry is hit even though the fault
 967  * entry is updated to a valid entry after the entry is cached.
 968  * To prevent caching fault page table entries which may be updated to valid
 969  * entries later, the virtual memory manager should care about the w/a about the
 970  * problem. The followings describe w/a.
 971  *
 972  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
 973  * in maximum to prevent misbehavior of System MMU 3.x. (w/a of h/w bug)
 974  *
 975  * Precisely, any start address of I/O virtual region must be aligned by
 976  * the following sizes for System MMU v3.1 and v3.2.
 977  * System MMU v3.1: 128KiB
 978  * System MMU v3.2: 256KiB
 979  *
 980  * Because System MMU v3.3 caches page table entries more aggressively, it needs
 981  * more w/a.
 982  * - Any two consecutive I/O virtual regions must be have a hole of larger size
 983  *   than or equal size to 128KiB.
 984  * - Start address of an I/O virtual region must be aligned by 128KiB.
 985  */
 986 static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova,
 987                          phys_addr_t paddr, size_t size, int prot)
 988 {
 989         struct exynos_iommu_domain *priv = domain->priv;
 990         sysmmu_pte_t *entry;
 991         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
 992         unsigned long flags;
 993         int ret = -ENOMEM;
 994
 995         BUG_ON(priv->pgtable == NULL);
 996
 997         spin_lock_irqsave(&priv->pgtablelock, flags);
 998
 999         entry = section_entry(priv->pgtable, iova);
1000
1001         if (size == SECT_SIZE) {
1002                 ret = lv1set_section(priv, entry, iova, paddr,
1003                                         &priv->lv2entcnt[lv1ent_offset(iova)]);
1004         } else {
1005                 sysmmu_pte_t *pent;
1006
1007                 pent = alloc_lv2entry(priv, entry, iova,
1008                                         &priv->lv2entcnt[lv1ent_offset(iova)]);
1009
1010                 if (IS_ERR(pent))
1011                         ret = PTR_ERR(pent);
1012                 else
1013                         ret = lv2set_page(pent, paddr, size,
1014                                         &priv->lv2entcnt[lv1ent_offset(iova)]);
1015         }
1016
1017         if (ret)
1018                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1019                         __func__, ret, size, iova);
1020
1021         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1022
1023         return ret;
1024 }
1025
1026 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *priv,
1027                                                 sysmmu_iova_t iova, size_t size)
1028 {
1029         struct exynos_iommu_owner *owner;
1030         unsigned long flags;
1031
1032         spin_lock_irqsave(&priv->lock, flags);
1033
1034         list_for_each_entry(owner, &priv->clients, client)
1035                 sysmmu_tlb_invalidate_entry(owner->dev, iova, size);
1036
1037         spin_unlock_irqrestore(&priv->lock, flags);
1038 }
1039
1040 static size_t exynos_iommu_unmap(struct iommu_domain *domain,
1041                                         unsigned long l_iova, size_t size)
1042 {
1043         struct exynos_iommu_domain *priv = domain->priv;
1044         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1045         sysmmu_pte_t *ent;
1046         size_t err_pgsize;
1047         unsigned long flags;
1048
1049         BUG_ON(priv->pgtable == NULL);
1050
1051         spin_lock_irqsave(&priv->pgtablelock, flags);
1052
1053         ent = section_entry(priv->pgtable, iova);
1054
1055         if (lv1ent_section(ent)) {
1056                 if (WARN_ON(size < SECT_SIZE)) {
1057                         err_pgsize = SECT_SIZE;
1058                         goto err;
1059                 }
1060
1061                 *ent = ZERO_LV2LINK; /* w/a for h/w bug in Sysmem MMU v3.3 */
1062                 pgtable_flush(ent, ent + 1);
1063                 size = SECT_SIZE;
1064                 goto done;
1065         }
1066
1067         if (unlikely(lv1ent_fault(ent))) {
1068                 if (size > SECT_SIZE)
1069                         size = SECT_SIZE;
1070                 goto done;
1071         }
1072
1073         /* lv1ent_page(sent) == true here */
1074
1075         ent = page_entry(ent, iova);
1076
1077         if (unlikely(lv2ent_fault(ent))) {
1078                 size = SPAGE_SIZE;
1079                 goto done;
1080         }
1081
1082         if (lv2ent_small(ent)) {
1083                 *ent = 0;
1084                 size = SPAGE_SIZE;
1085                 pgtable_flush(ent, ent + 1);
1086                 priv->lv2entcnt[lv1ent_offset(iova)] += 1;
1087                 goto done;
1088         }
1089
1090         /* lv1ent_large(ent) == true here */
1091         if (WARN_ON(size < LPAGE_SIZE)) {
1092                 err_pgsize = LPAGE_SIZE;
1093                 goto err;
1094         }
1095
1096         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1097         pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
1098
1099         size = LPAGE_SIZE;
1100         priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1101 done:
1102         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1103
1104         exynos_iommu_tlb_invalidate_entry(priv, iova, size);
1105
1106         return size;
1107 err:
1108         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1109
1110         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1111                 __func__, size, iova, err_pgsize);
1112
1113         return 0;
1114 }
1115
1116 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
1117                                           dma_addr_t iova)
1118 {
1119         struct exynos_iommu_domain *priv = domain->priv;
1120         sysmmu_pte_t *entry;
1121         unsigned long flags;
1122         phys_addr_t phys = 0;
1123
1124         spin_lock_irqsave(&priv->pgtablelock, flags);
1125
1126         entry = section_entry(priv->pgtable, iova);
1127
1128         if (lv1ent_section(entry)) {
1129                 phys = section_phys(entry) + section_offs(iova);
1130         } else if (lv1ent_page(entry)) {
1131                 entry = page_entry(entry, iova);
1132
1133                 if (lv2ent_large(entry))
1134                         phys = lpage_phys(entry) + lpage_offs(iova);
1135                 else if (lv2ent_small(entry))
1136                         phys = spage_phys(entry) + spage_offs(iova);
1137         }
1138
1139         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1140
1141         return phys;
1142 }
1143
1144 static int exynos_iommu_add_device(struct device *dev)
1145 {
1146         struct iommu_group *group;
1147         int ret;
1148
1149         group = iommu_group_get(dev);
1150
1151         if (!group) {
1152                 group = iommu_group_alloc();
1153                 if (IS_ERR(group)) {
1154                         dev_err(dev, "Failed to allocate IOMMU group\n");
1155                         return PTR_ERR(group);
1156                 }
1157         }
1158
1159         ret = iommu_group_add_device(group, dev);
1160         iommu_group_put(group);
1161
1162         return ret;
1163 }
1164
1165 static void exynos_iommu_remove_device(struct device *dev)
1166 {
1167         iommu_group_remove_device(dev);
1168 }
1169
1170 static struct iommu_ops exynos_iommu_ops = {
1171         .domain_init = exynos_iommu_domain_init,
1172         .domain_destroy = exynos_iommu_domain_destroy,
1173         .attach_dev = exynos_iommu_attach_device,
1174         .detach_dev = exynos_iommu_detach_device,
1175         .map = exynos_iommu_map,
1176         .unmap = exynos_iommu_unmap,
1177         .iova_to_phys = exynos_iommu_iova_to_phys,
1178         .add_device = exynos_iommu_add_device,
1179         .remove_device = exynos_iommu_remove_device,
1180         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1181 };
1182
1183 static int __init exynos_iommu_init(void)
1184 {
1185         int ret;
1186
1187         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1188                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1189         if (!lv2table_kmem_cache) {
1190                 pr_err("%s: Failed to create kmem cache\n", __func__);
1191                 return -ENOMEM;
1192         }
1193
1194         ret = platform_driver_register(&exynos_sysmmu_driver);
1195         if (ret) {
1196                 pr_err("%s: Failed to register driver\n", __func__);
1197                 goto err_reg_driver;
1198         }
1199
1200         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1201         if (zero_lv2_table == NULL) {
1202                 pr_err("%s: Failed to allocate zero level2 page table\n",
1203                         __func__);
1204                 ret = -ENOMEM;
1205                 goto err_zero_lv2;
1206         }
1207
1208         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1209         if (ret) {
1210                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1211                                                                 __func__);
1212                 goto err_set_iommu;
1213         }
1214
1215         return 0;
1216 err_set_iommu:
1217         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1218 err_zero_lv2:
1219         platform_driver_unregister(&exynos_sysmmu_driver);
1220 err_reg_driver:
1221         kmem_cache_destroy(lv2table_kmem_cache);
1222         return ret;
1223 }
1224 subsys_initcall(exynos_iommu_init);