drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 #ifdef CONFIG_BIG_ENDIAN
  58 #warning "revisit driver if we can enable big-endian ptes"
  59 #endif
  60
  61 /*
  62  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  63  * v5.0 introduced support for 36bit physical address space by shifting
  64  * all page entry values by 4 bits.
  65  * All SYSMMU controllers in the system support the address spaces of the same
  66  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  67  * value (0 or 4).
  68  */
  69 static short PG_ENT_SHIFT = -1;
  70 #define SYSMMU_PG_ENT_SHIFT 0
  71 #define SYSMMU_V5_PG_ENT_SHIFT 4
  72
  73 static const sysmmu_pte_t *LV1_PROT;
  74 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = {
  75         ((0 << 15) | (0 << 10)), /* no access */
  76         ((1 << 15) | (1 << 10)), /* IOMMU_READ only */
  77         ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
  78         ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
  79 };
  80 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = {
  81         (0 << 4), /* no access */
  82         (1 << 4), /* IOMMU_READ only */
  83         (2 << 4), /* IOMMU_WRITE only */
  84         (3 << 4), /* IOMMU_READ | IOMMU_WRITE */
  85 };
  86
  87 static const sysmmu_pte_t *LV2_PROT;
  88 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = {
  89         ((0 << 9) | (0 << 4)), /* no access */
  90         ((1 << 9) | (1 << 4)), /* IOMMU_READ only */
  91         ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
  92         ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
  93 };
  94 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = {
  95         (0 << 2), /* no access */
  96         (1 << 2), /* IOMMU_READ only */
  97         (2 << 2), /* IOMMU_WRITE only */
  98         (3 << 2), /* IOMMU_READ | IOMMU_WRITE */
  99 };
 100
 101 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE)
 102
 103 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
 104 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
 105 #define section_offs(iova) (iova & (SECT_SIZE - 1))
 106 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
 107 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
 108 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
 109 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
 110
 111 #define NUM_LV1ENTRIES 4096
 112 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
 113
 114 static u32 lv1ent_offset(sysmmu_iova_t iova)
 115 {
 116         return iova >> SECT_ORDER;
 117 }
 118
 119 static u32 lv2ent_offset(sysmmu_iova_t iova)
 120 {
 121         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
 122 }
 123
 124 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
 125 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
 126
 127 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
 128 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
 129
 130 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2)
 131 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
 132 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1)
 133 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2)
 134
 135 #define CTRL_ENABLE     0x5
 136 #define CTRL_BLOCK      0x7
 137 #define CTRL_DISABLE    0x0
 138
 139 #define CFG_LRU         0x1
 140 #define CFG_EAP         (1 << 2)
 141 #define CFG_QOS(n)      ((n & 0xF) << 7)
 142 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 143 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 144 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 145
 146 /* common registers */
 147 #define REG_MMU_CTRL            0x000
 148 #define REG_MMU_CFG             0x004
 149 #define REG_MMU_STATUS          0x008
 150 #define REG_MMU_VERSION         0x034
 151
 152 #define MMU_MAJ_VER(val)        ((val) >> 7)
 153 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 154 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 155
 156 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 157
 158 /* v1.x - v3.x registers */
 159 #define REG_MMU_FLUSH           0x00C
 160 #define REG_MMU_FLUSH_ENTRY     0x010
 161 #define REG_PT_BASE_ADDR        0x014
 162 #define REG_INT_STATUS          0x018
 163 #define REG_INT_CLEAR           0x01C
 164
 165 #define REG_PAGE_FAULT_ADDR     0x024
 166 #define REG_AW_FAULT_ADDR       0x028
 167 #define REG_AR_FAULT_ADDR       0x02C
 168 #define REG_DEFAULT_SLAVE_ADDR  0x030
 169
 170 /* v5.x registers */
 171 #define REG_V5_PT_BASE_PFN      0x00C
 172 #define REG_V5_MMU_FLUSH_ALL    0x010
 173 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 174 #define REG_V5_INT_STATUS       0x060
 175 #define REG_V5_INT_CLEAR        0x064
 176 #define REG_V5_FAULT_AR_VA      0x070
 177 #define REG_V5_FAULT_AW_VA      0x080
 178
 179 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 180
 181 static struct device *dma_dev;
 182 static struct kmem_cache *lv2table_kmem_cache;
 183 static sysmmu_pte_t *zero_lv2_table;
 184 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 185
 186 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 187 {
 188         return pgtable + lv1ent_offset(iova);
 189 }
 190
 191 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 192 {
 193         return (sysmmu_pte_t *)phys_to_virt(
 194                                 lv2table_base(sent)) + lv2ent_offset(iova);
 195 }
 196
 197 /*
 198  * IOMMU fault information register
 199  */
 200 struct sysmmu_fault_info {
 201         unsigned int bit;       /* bit number in STATUS register */
 202         unsigned short addr_reg; /* register to read VA fault address */
 203         const char *name;       /* human readable fault name */
 204         unsigned int type;      /* fault type for report_iommu_fault */
 205 };
 206
 207 static const struct sysmmu_fault_info sysmmu_faults[] = {
 208         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 209         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 210         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 211         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 212         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 213         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 214         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 215         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 216 };
 217
 218 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 219         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 220         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 221         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 222         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 223         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 224         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 225         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 226         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 227         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 228         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 229 };
 230
 231 /*
 232  * This structure is attached to dev.archdata.iommu of the master device
 233  * on device add, contains a list of SYSMMU controllers defined by device tree,
 234  * which are bound to given master device. It is usually referenced by 'owner'
 235  * pointer.
 236 */
 237 struct exynos_iommu_owner {
 238         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 239         struct iommu_domain *domain;    /* domain this device is attached */
 240         struct mutex rpm_lock;          /* for runtime pm of all sysmmus */
 241 };
 242
 243 /*
 244  * This structure exynos specific generalization of struct iommu_domain.
 245  * It contains list of SYSMMU controllers from all master devices, which has
 246  * been attached to this domain and page tables of IO address space defined by
 247  * it. It is usually referenced by 'domain' pointer.
 248  */
 249 struct exynos_iommu_domain {
 250         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 251         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 252         short *lv2entcnt;       /* free lv2 entry counter for each section */
 253         spinlock_t lock;        /* lock for modyfying list of clients */
 254         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 255         struct iommu_domain domain; /* generic domain data structure */
 256 };
 257
 258 /*
 259  * This structure hold all data of a single SYSMMU controller, this includes
 260  * hw resources like registers and clocks, pointers and list nodes to connect
 261  * it to all other structures, internal state and parameters read from device
 262  * tree. It is usually referenced by 'data' pointer.
 263  */
 264 struct sysmmu_drvdata {
 265         struct device *sysmmu;          /* SYSMMU controller device */
 266         struct device *master;          /* master device (owner) */
 267         void __iomem *sfrbase;          /* our registers */
 268         struct clk *clk;                /* SYSMMU's clock */
 269         struct clk *aclk;               /* SYSMMU's aclk clock */
 270         struct clk *pclk;               /* SYSMMU's pclk clock */
 271         struct clk *clk_master;         /* master's device clock */
 272         spinlock_t lock;                /* lock for modyfying state */
 273         bool active;                    /* current status */
 274         struct exynos_iommu_domain *domain; /* domain we belong to */
 275         struct list_head domain_node;   /* node for domain clients list */
 276         struct list_head owner_node;    /* node for owner controllers list */
 277         phys_addr_t pgtable;            /* assigned page table structure */
 278         unsigned int version;           /* our version */
 279
 280         struct iommu_device iommu;      /* IOMMU core handle */
 281 };
 282
 283 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 284 {
 285         return container_of(dom, struct exynos_iommu_domain, domain);
 286 }
 287
 288 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 289 {
 290         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 291 }
 292
 293 static bool sysmmu_block(struct sysmmu_drvdata *data)
 294 {
 295         int i = 120;
 296
 297         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 298         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 299                 --i;
 300
 301         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 302                 sysmmu_unblock(data);
 303                 return false;
 304         }
 305
 306         return true;
 307 }
 308
 309 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 310 {
 311         if (MMU_MAJ_VER(data->version) < 5)
 312                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 313         else
 314                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 315 }
 316
 317 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 318                                 sysmmu_iova_t iova, unsigned int num_inv)
 319 {
 320         unsigned int i;
 321
 322         for (i = 0; i < num_inv; i++) {
 323                 if (MMU_MAJ_VER(data->version) < 5)
 324                         writel((iova & SPAGE_MASK) | 1,
 325                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 326                 else
 327                         writel((iova & SPAGE_MASK) | 1,
 328                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 329                 iova += SPAGE_SIZE;
 330         }
 331 }
 332
 333 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 334 {
 335         if (MMU_MAJ_VER(data->version) < 5)
 336                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 337         else
 338                 writel(pgd >> PAGE_SHIFT,
 339                              data->sfrbase + REG_V5_PT_BASE_PFN);
 340
 341         __sysmmu_tlb_invalidate(data);
 342 }
 343
 344 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 345 {
 346         BUG_ON(clk_prepare_enable(data->clk_master));
 347         BUG_ON(clk_prepare_enable(data->clk));
 348         BUG_ON(clk_prepare_enable(data->pclk));
 349         BUG_ON(clk_prepare_enable(data->aclk));
 350 }
 351
 352 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 353 {
 354         clk_disable_unprepare(data->aclk);
 355         clk_disable_unprepare(data->pclk);
 356         clk_disable_unprepare(data->clk);
 357         clk_disable_unprepare(data->clk_master);
 358 }
 359
 360 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 361 {
 362         u32 ver;
 363
 364         __sysmmu_enable_clocks(data);
 365
 366         ver = readl(data->sfrbase + REG_MMU_VERSION);
 367
 368         /* controllers on some SoCs don't report proper version */
 369         if (ver == 0x80000001u)
 370                 data->version = MAKE_MMU_VER(1, 0);
 371         else
 372                 data->version = MMU_RAW_VER(ver);
 373
 374         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 375                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 376
 377         __sysmmu_disable_clocks(data);
 378 }
 379
 380 static void show_fault_information(struct sysmmu_drvdata *data,
 381                                    const struct sysmmu_fault_info *finfo,
 382                                    sysmmu_iova_t fault_addr)
 383 {
 384         sysmmu_pte_t *ent;
 385
 386         dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n",
 387                 dev_name(data->master), finfo->name, fault_addr);
 388         dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable);
 389         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 390         dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 391         if (lv1ent_page(ent)) {
 392                 ent = page_entry(ent, fault_addr);
 393                 dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 394         }
 395 }
 396
 397 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 398 {
 399         /* SYSMMU is in blocked state when interrupt occurred. */
 400         struct sysmmu_drvdata *data = dev_id;
 401         const struct sysmmu_fault_info *finfo;
 402         unsigned int i, n, itype;
 403         sysmmu_iova_t fault_addr = -1;
 404         unsigned short reg_status, reg_clear;
 405         int ret = -ENOSYS;
 406
 407         WARN_ON(!data->active);
 408
 409         if (MMU_MAJ_VER(data->version) < 5) {
 410                 reg_status = REG_INT_STATUS;
 411                 reg_clear = REG_INT_CLEAR;
 412                 finfo = sysmmu_faults;
 413                 n = ARRAY_SIZE(sysmmu_faults);
 414         } else {
 415                 reg_status = REG_V5_INT_STATUS;
 416                 reg_clear = REG_V5_INT_CLEAR;
 417                 finfo = sysmmu_v5_faults;
 418                 n = ARRAY_SIZE(sysmmu_v5_faults);
 419         }
 420
 421         spin_lock(&data->lock);
 422
 423         clk_enable(data->clk_master);
 424
 425         itype = __ffs(readl(data->sfrbase + reg_status));
 426         for (i = 0; i < n; i++, finfo++)
 427                 if (finfo->bit == itype)
 428                         break;
 429         /* unknown/unsupported fault */
 430         BUG_ON(i == n);
 431
 432         /* print debug message */
 433         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 434         show_fault_information(data, finfo, fault_addr);
 435
 436         if (data->domain)
 437                 ret = report_iommu_fault(&data->domain->domain,
 438                                         data->master, fault_addr, finfo->type);
 439         /* fault is not recovered by fault handler */
 440         BUG_ON(ret != 0);
 441
 442         writel(1 << itype, data->sfrbase + reg_clear);
 443
 444         sysmmu_unblock(data);
 445
 446         clk_disable(data->clk_master);
 447
 448         spin_unlock(&data->lock);
 449
 450         return IRQ_HANDLED;
 451 }
 452
 453 static void __sysmmu_disable(struct sysmmu_drvdata *data)
 454 {
 455         unsigned long flags;
 456
 457         clk_enable(data->clk_master);
 458
 459         spin_lock_irqsave(&data->lock, flags);
 460         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 461         writel(0, data->sfrbase + REG_MMU_CFG);
 462         data->active = false;
 463         spin_unlock_irqrestore(&data->lock, flags);
 464
 465         __sysmmu_disable_clocks(data);
 466 }
 467
 468 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 469 {
 470         unsigned int cfg;
 471
 472         if (data->version <= MAKE_MMU_VER(3, 1))
 473                 cfg = CFG_LRU | CFG_QOS(15);
 474         else if (data->version <= MAKE_MMU_VER(3, 2))
 475                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 476         else
 477                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 478
 479         cfg |= CFG_EAP; /* enable access protection bits check */
 480
 481         writel(cfg, data->sfrbase + REG_MMU_CFG);
 482 }
 483
 484 static void __sysmmu_enable(struct sysmmu_drvdata *data)
 485 {
 486         unsigned long flags;
 487
 488         __sysmmu_enable_clocks(data);
 489
 490         spin_lock_irqsave(&data->lock, flags);
 491         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 492         __sysmmu_init_config(data);
 493         __sysmmu_set_ptbase(data, data->pgtable);
 494         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 495         data->active = true;
 496         spin_unlock_irqrestore(&data->lock, flags);
 497
 498         /*
 499          * SYSMMU driver keeps master's clock enabled only for the short
 500          * time, while accessing the registers. For performing address
 501          * translation during DMA transaction it relies on the client
 502          * driver to enable it.
 503          */
 504         clk_disable(data->clk_master);
 505 }
 506
 507 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 508                                             sysmmu_iova_t iova)
 509 {
 510         unsigned long flags;
 511
 512         spin_lock_irqsave(&data->lock, flags);
 513         if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
 514                 clk_enable(data->clk_master);
 515                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 516                 clk_disable(data->clk_master);
 517         }
 518         spin_unlock_irqrestore(&data->lock, flags);
 519 }
 520
 521 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 522                                         sysmmu_iova_t iova, size_t size)
 523 {
 524         unsigned long flags;
 525
 526         spin_lock_irqsave(&data->lock, flags);
 527         if (data->active) {
 528                 unsigned int num_inv = 1;
 529
 530                 clk_enable(data->clk_master);
 531
 532                 /*
 533                  * L2TLB invalidation required
 534                  * 4KB page: 1 invalidation
 535                  * 64KB page: 16 invalidations
 536                  * 1MB page: 64 invalidations
 537                  * because it is set-associative TLB
 538                  * with 8-way and 64 sets.
 539                  * 1MB page can be cached in one of all sets.
 540                  * 64KB page can be one of 16 consecutive sets.
 541                  */
 542                 if (MMU_MAJ_VER(data->version) == 2)
 543                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 544
 545                 if (sysmmu_block(data)) {
 546                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 547                         sysmmu_unblock(data);
 548                 }
 549                 clk_disable(data->clk_master);
 550         }
 551         spin_unlock_irqrestore(&data->lock, flags);
 552 }
 553
 554 static struct iommu_ops exynos_iommu_ops;
 555
 556 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 557 {
 558         int irq, ret;
 559         struct device *dev = &pdev->dev;
 560         struct sysmmu_drvdata *data;
 561         struct resource *res;
 562
 563         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 564         if (!data)
 565                 return -ENOMEM;
 566
 567         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 568         data->sfrbase = devm_ioremap_resource(dev, res);
 569         if (IS_ERR(data->sfrbase))
 570                 return PTR_ERR(data->sfrbase);
 571
 572         irq = platform_get_irq(pdev, 0);
 573         if (irq <= 0) {
 574                 dev_err(dev, "Unable to find IRQ resource\n");
 575                 return irq;
 576         }
 577
 578         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 579                                 dev_name(dev), data);
 580         if (ret) {
 581                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 582                 return ret;
 583         }
 584
 585         data->clk = devm_clk_get(dev, "sysmmu");
 586         if (PTR_ERR(data->clk) == -ENOENT)
 587                 data->clk = NULL;
 588         else if (IS_ERR(data->clk))
 589                 return PTR_ERR(data->clk);
 590
 591         data->aclk = devm_clk_get(dev, "aclk");
 592         if (PTR_ERR(data->aclk) == -ENOENT)
 593                 data->aclk = NULL;
 594         else if (IS_ERR(data->aclk))
 595                 return PTR_ERR(data->aclk);
 596
 597         data->pclk = devm_clk_get(dev, "pclk");
 598         if (PTR_ERR(data->pclk) == -ENOENT)
 599                 data->pclk = NULL;
 600         else if (IS_ERR(data->pclk))
 601                 return PTR_ERR(data->pclk);
 602
 603         if (!data->clk && (!data->aclk || !data->pclk)) {
 604                 dev_err(dev, "Failed to get device clock(s)!\n");
 605                 return -ENOSYS;
 606         }
 607
 608         data->clk_master = devm_clk_get(dev, "master");
 609         if (PTR_ERR(data->clk_master) == -ENOENT)
 610                 data->clk_master = NULL;
 611         else if (IS_ERR(data->clk_master))
 612                 return PTR_ERR(data->clk_master);
 613
 614         data->sysmmu = dev;
 615         spin_lock_init(&data->lock);
 616
 617         ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
 618                                      dev_name(data->sysmmu));
 619         if (ret)
 620                 return ret;
 621
 622         iommu_device_set_ops(&data->iommu, &exynos_iommu_ops);
 623         iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode);
 624
 625         ret = iommu_device_register(&data->iommu);
 626         if (ret)
 627                 return ret;
 628
 629         platform_set_drvdata(pdev, data);
 630
 631         __sysmmu_get_version(data);
 632         if (PG_ENT_SHIFT < 0) {
 633                 if (MMU_MAJ_VER(data->version) < 5) {
 634                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 635                         LV1_PROT = SYSMMU_LV1_PROT;
 636                         LV2_PROT = SYSMMU_LV2_PROT;
 637                 } else {
 638                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 639                         LV1_PROT = SYSMMU_V5_LV1_PROT;
 640                         LV2_PROT = SYSMMU_V5_LV2_PROT;
 641                 }
 642         }
 643
 644         pm_runtime_enable(dev);
 645
 646         return 0;
 647 }
 648
 649 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev)
 650 {
 651         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 652         struct device *master = data->master;
 653
 654         if (master) {
 655                 struct exynos_iommu_owner *owner = master->archdata.iommu;
 656
 657                 mutex_lock(&owner->rpm_lock);
 658                 if (data->domain) {
 659                         dev_dbg(data->sysmmu, "saving state\n");
 660                         __sysmmu_disable(data);
 661                 }
 662                 mutex_unlock(&owner->rpm_lock);
 663         }
 664         return 0;
 665 }
 666
 667 static int __maybe_unused exynos_sysmmu_resume(struct device *dev)
 668 {
 669         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 670         struct device *master = data->master;
 671
 672         if (master) {
 673                 struct exynos_iommu_owner *owner = master->archdata.iommu;
 674
 675                 mutex_lock(&owner->rpm_lock);
 676                 if (data->domain) {
 677                         dev_dbg(data->sysmmu, "restoring state\n");
 678                         __sysmmu_enable(data);
 679                 }
 680                 mutex_unlock(&owner->rpm_lock);
 681         }
 682         return 0;
 683 }
 684
 685 static const struct dev_pm_ops sysmmu_pm_ops = {
 686         SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL)
 687         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 688                                 pm_runtime_force_resume)
 689 };
 690
 691 static const struct of_device_id sysmmu_of_match[] __initconst = {
 692         { .compatible   = "samsung,exynos-sysmmu", },
 693         { },
 694 };
 695
 696 static struct platform_driver exynos_sysmmu_driver __refdata = {
 697         .probe  = exynos_sysmmu_probe,
 698         .driver = {
 699                 .name           = "exynos-sysmmu",
 700                 .of_match_table = sysmmu_of_match,
 701                 .pm             = &sysmmu_pm_ops,
 702                 .suppress_bind_attrs = true,
 703         }
 704 };
 705
 706 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 707 {
 708         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 709                                 DMA_TO_DEVICE);
 710         *ent = cpu_to_le32(val);
 711         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 712                                    DMA_TO_DEVICE);
 713 }
 714
 715 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 716 {
 717         struct exynos_iommu_domain *domain;
 718         dma_addr_t handle;
 719         int i;
 720
 721         /* Check if correct PTE offsets are initialized */
 722         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 723
 724         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 725         if (!domain)
 726                 return NULL;
 727
 728         if (type == IOMMU_DOMAIN_DMA) {
 729                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 730                         goto err_pgtable;
 731         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 732                 goto err_pgtable;
 733         }
 734
 735         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 736         if (!domain->pgtable)
 737                 goto err_dma_cookie;
 738
 739         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 740         if (!domain->lv2entcnt)
 741                 goto err_counter;
 742
 743         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 744         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 745                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 746                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 747                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 748                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 749                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 750                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 751                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 752                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 753         }
 754
 755         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 756                                 DMA_TO_DEVICE);
 757         /* For mapping page table entries we rely on dma == phys */
 758         BUG_ON(handle != virt_to_phys(domain->pgtable));
 759         if (dma_mapping_error(dma_dev, handle))
 760                 goto err_lv2ent;
 761
 762         spin_lock_init(&domain->lock);
 763         spin_lock_init(&domain->pgtablelock);
 764         INIT_LIST_HEAD(&domain->clients);
 765
 766         domain->domain.geometry.aperture_start = 0;
 767         domain->domain.geometry.aperture_end   = ~0UL;
 768         domain->domain.geometry.force_aperture = true;
 769
 770         return &domain->domain;
 771
 772 err_lv2ent:
 773         free_pages((unsigned long)domain->lv2entcnt, 1);
 774 err_counter:
 775         free_pages((unsigned long)domain->pgtable, 2);
 776 err_dma_cookie:
 777         if (type == IOMMU_DOMAIN_DMA)
 778                 iommu_put_dma_cookie(&domain->domain);
 779 err_pgtable:
 780         kfree(domain);
 781         return NULL;
 782 }
 783
 784 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 785 {
 786         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 787         struct sysmmu_drvdata *data, *next;
 788         unsigned long flags;
 789         int i;
 790
 791         WARN_ON(!list_empty(&domain->clients));
 792
 793         spin_lock_irqsave(&domain->lock, flags);
 794
 795         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 796                 spin_lock(&data->lock);
 797                 __sysmmu_disable(data);
 798                 data->pgtable = 0;
 799                 data->domain = NULL;
 800                 list_del_init(&data->domain_node);
 801                 spin_unlock(&data->lock);
 802         }
 803
 804         spin_unlock_irqrestore(&domain->lock, flags);
 805
 806         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 807                 iommu_put_dma_cookie(iommu_domain);
 808
 809         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 810                          DMA_TO_DEVICE);
 811
 812         for (i = 0; i < NUM_LV1ENTRIES; i++)
 813                 if (lv1ent_page(domain->pgtable + i)) {
 814                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 815
 816                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 817                                          DMA_TO_DEVICE);
 818                         kmem_cache_free(lv2table_kmem_cache,
 819                                         phys_to_virt(base));
 820                 }
 821
 822         free_pages((unsigned long)domain->pgtable, 2);
 823         free_pages((unsigned long)domain->lv2entcnt, 1);
 824         kfree(domain);
 825 }
 826
 827 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 828                                     struct device *dev)
 829 {
 830         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 831         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 832         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 833         struct sysmmu_drvdata *data, *next;
 834         unsigned long flags;
 835
 836         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 837                 return;
 838
 839         mutex_lock(&owner->rpm_lock);
 840
 841         list_for_each_entry(data, &owner->controllers, owner_node) {
 842                 pm_runtime_get_noresume(data->sysmmu);
 843                 if (pm_runtime_active(data->sysmmu))
 844                         __sysmmu_disable(data);
 845                 pm_runtime_put(data->sysmmu);
 846         }
 847
 848         spin_lock_irqsave(&domain->lock, flags);
 849         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 850                 spin_lock(&data->lock);
 851                 data->pgtable = 0;
 852                 data->domain = NULL;
 853                 list_del_init(&data->domain_node);
 854                 spin_unlock(&data->lock);
 855         }
 856         owner->domain = NULL;
 857         spin_unlock_irqrestore(&domain->lock, flags);
 858
 859         mutex_unlock(&owner->rpm_lock);
 860
 861         dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__,
 862                 &pagetable);
 863 }
 864
 865 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 866                                    struct device *dev)
 867 {
 868         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 869         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 870         struct sysmmu_drvdata *data;
 871         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 872         unsigned long flags;
 873
 874         if (!has_sysmmu(dev))
 875                 return -ENODEV;
 876
 877         if (owner->domain)
 878                 exynos_iommu_detach_device(owner->domain, dev);
 879
 880         mutex_lock(&owner->rpm_lock);
 881
 882         spin_lock_irqsave(&domain->lock, flags);
 883         list_for_each_entry(data, &owner->controllers, owner_node) {
 884                 spin_lock(&data->lock);
 885                 data->pgtable = pagetable;
 886                 data->domain = domain;
 887                 list_add_tail(&data->domain_node, &domain->clients);
 888                 spin_unlock(&data->lock);
 889         }
 890         owner->domain = iommu_domain;
 891         spin_unlock_irqrestore(&domain->lock, flags);
 892
 893         list_for_each_entry(data, &owner->controllers, owner_node) {
 894                 pm_runtime_get_noresume(data->sysmmu);
 895                 if (pm_runtime_active(data->sysmmu))
 896                         __sysmmu_enable(data);
 897                 pm_runtime_put(data->sysmmu);
 898         }
 899
 900         mutex_unlock(&owner->rpm_lock);
 901
 902         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__,
 903                 &pagetable);
 904
 905         return 0;
 906 }
 907
 908 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 909                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 910 {
 911         if (lv1ent_section(sent)) {
 912                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 913                 return ERR_PTR(-EADDRINUSE);
 914         }
 915
 916         if (lv1ent_fault(sent)) {
 917                 dma_addr_t handle;
 918                 sysmmu_pte_t *pent;
 919                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 920
 921                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 922                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 923                 if (!pent)
 924                         return ERR_PTR(-ENOMEM);
 925
 926                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 927                 kmemleak_ignore(pent);
 928                 *pgcounter = NUM_LV2ENTRIES;
 929                 handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE,
 930                                         DMA_TO_DEVICE);
 931                 if (dma_mapping_error(dma_dev, handle)) {
 932                         kmem_cache_free(lv2table_kmem_cache, pent);
 933                         return ERR_PTR(-EADDRINUSE);
 934                 }
 935
 936                 /*
 937                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 938                  * FLPD cache may cache the address of zero_l2_table. This
 939                  * function replaces the zero_l2_table with new L2 page table
 940                  * to write valid mappings.
 941                  * Accessing the valid area may cause page fault since FLPD
 942                  * cache may still cache zero_l2_table for the valid area
 943                  * instead of new L2 page table that has the mapping
 944                  * information of the valid area.
 945                  * Thus any replacement of zero_l2_table with other valid L2
 946                  * page table must involve FLPD cache invalidation for System
 947                  * MMU v3.3.
 948                  * FLPD cache invalidation is performed with TLB invalidation
 949                  * by VPN without blocking. It is safe to invalidate TLB without
 950                  * blocking because the target address of TLB invalidation is
 951                  * not currently mapped.
 952                  */
 953                 if (need_flush_flpd_cache) {
 954                         struct sysmmu_drvdata *data;
 955
 956                         spin_lock(&domain->lock);
 957                         list_for_each_entry(data, &domain->clients, domain_node)
 958                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 959                         spin_unlock(&domain->lock);
 960                 }
 961         }
 962
 963         return page_entry(sent, iova);
 964 }
 965
 966 static int lv1set_section(struct exynos_iommu_domain *domain,
 967                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 968                           phys_addr_t paddr, int prot, short *pgcnt)
 969 {
 970         if (lv1ent_section(sent)) {
 971                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 972                         iova);
 973                 return -EADDRINUSE;
 974         }
 975
 976         if (lv1ent_page(sent)) {
 977                 if (*pgcnt != NUM_LV2ENTRIES) {
 978                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 979                                 iova);
 980                         return -EADDRINUSE;
 981                 }
 982
 983                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 984                 *pgcnt = 0;
 985         }
 986
 987         update_pte(sent, mk_lv1ent_sect(paddr, prot));
 988
 989         spin_lock(&domain->lock);
 990         if (lv1ent_page_zero(sent)) {
 991                 struct sysmmu_drvdata *data;
 992                 /*
 993                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 994                  * entry by speculative prefetch of SLPD which has no mapping.
 995                  */
 996                 list_for_each_entry(data, &domain->clients, domain_node)
 997                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 998         }
 999         spin_unlock(&domain->lock);
1000
1001         return 0;
1002 }
1003
1004 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
1005                        int prot, short *pgcnt)
1006 {
1007         if (size == SPAGE_SIZE) {
1008                 if (WARN_ON(!lv2ent_fault(pent)))
1009                         return -EADDRINUSE;
1010
1011                 update_pte(pent, mk_lv2ent_spage(paddr, prot));
1012                 *pgcnt -= 1;
1013         } else { /* size == LPAGE_SIZE */
1014                 int i;
1015                 dma_addr_t pent_base = virt_to_phys(pent);
1016
1017                 dma_sync_single_for_cpu(dma_dev, pent_base,
1018                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1019                                         DMA_TO_DEVICE);
1020                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1021                         if (WARN_ON(!lv2ent_fault(pent))) {
1022                                 if (i > 0)
1023                                         memset(pent - i, 0, sizeof(*pent) * i);
1024                                 return -EADDRINUSE;
1025                         }
1026
1027                         *pent = mk_lv2ent_lpage(paddr, prot);
1028                 }
1029                 dma_sync_single_for_device(dma_dev, pent_base,
1030                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1031                                            DMA_TO_DEVICE);
1032                 *pgcnt -= SPAGES_PER_LPAGE;
1033         }
1034
1035         return 0;
1036 }
1037
1038 /*
1039  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1040  *
1041  * System MMU v3.x has advanced logic to improve address translation
1042  * performance with caching more page table entries by a page table walk.
1043  * However, the logic has a bug that while caching faulty page table entries,
1044  * System MMU reports page fault if the cached fault entry is hit even though
1045  * the fault entry is updated to a valid entry after the entry is cached.
1046  * To prevent caching faulty page table entries which may be updated to valid
1047  * entries later, the virtual memory manager should care about the workaround
1048  * for the problem. The following describes the workaround.
1049  *
1050  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1051  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1052  *
1053  * Precisely, any start address of I/O virtual region must be aligned with
1054  * the following sizes for System MMU v3.1 and v3.2.
1055  * System MMU v3.1: 128KiB
1056  * System MMU v3.2: 256KiB
1057  *
1058  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1059  * more workarounds.
1060  * - Any two consecutive I/O virtual regions must have a hole of size larger
1061  *   than or equal to 128KiB.
1062  * - Start address of an I/O virtual region must be aligned by 128KiB.
1063  */
1064 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1065                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1066                             int prot)
1067 {
1068         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1069         sysmmu_pte_t *entry;
1070         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1071         unsigned long flags;
1072         int ret = -ENOMEM;
1073
1074         BUG_ON(domain->pgtable == NULL);
1075         prot &= SYSMMU_SUPPORTED_PROT_BITS;
1076
1077         spin_lock_irqsave(&domain->pgtablelock, flags);
1078
1079         entry = section_entry(domain->pgtable, iova);
1080
1081         if (size == SECT_SIZE) {
1082                 ret = lv1set_section(domain, entry, iova, paddr, prot,
1083                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1084         } else {
1085                 sysmmu_pte_t *pent;
1086
1087                 pent = alloc_lv2entry(domain, entry, iova,
1088                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1089
1090                 if (IS_ERR(pent))
1091                         ret = PTR_ERR(pent);
1092                 else
1093                         ret = lv2set_page(pent, paddr, size, prot,
1094                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1095         }
1096
1097         if (ret)
1098                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1099                         __func__, ret, size, iova);
1100
1101         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1102
1103         return ret;
1104 }
1105
1106 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1107                                               sysmmu_iova_t iova, size_t size)
1108 {
1109         struct sysmmu_drvdata *data;
1110         unsigned long flags;
1111
1112         spin_lock_irqsave(&domain->lock, flags);
1113
1114         list_for_each_entry(data, &domain->clients, domain_node)
1115                 sysmmu_tlb_invalidate_entry(data, iova, size);
1116
1117         spin_unlock_irqrestore(&domain->lock, flags);
1118 }
1119
1120 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1121                                  unsigned long l_iova, size_t size)
1122 {
1123         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1124         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1125         sysmmu_pte_t *ent;
1126         size_t err_pgsize;
1127         unsigned long flags;
1128
1129         BUG_ON(domain->pgtable == NULL);
1130
1131         spin_lock_irqsave(&domain->pgtablelock, flags);
1132
1133         ent = section_entry(domain->pgtable, iova);
1134
1135         if (lv1ent_section(ent)) {
1136                 if (WARN_ON(size < SECT_SIZE)) {
1137                         err_pgsize = SECT_SIZE;
1138                         goto err;
1139                 }
1140
1141                 /* workaround for h/w bug in System MMU v3.3 */
1142                 update_pte(ent, ZERO_LV2LINK);
1143                 size = SECT_SIZE;
1144                 goto done;
1145         }
1146
1147         if (unlikely(lv1ent_fault(ent))) {
1148                 if (size > SECT_SIZE)
1149                         size = SECT_SIZE;
1150                 goto done;
1151         }
1152
1153         /* lv1ent_page(sent) == true here */
1154
1155         ent = page_entry(ent, iova);
1156
1157         if (unlikely(lv2ent_fault(ent))) {
1158                 size = SPAGE_SIZE;
1159                 goto done;
1160         }
1161
1162         if (lv2ent_small(ent)) {
1163                 update_pte(ent, 0);
1164                 size = SPAGE_SIZE;
1165                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1166                 goto done;
1167         }
1168
1169         /* lv1ent_large(ent) == true here */
1170         if (WARN_ON(size < LPAGE_SIZE)) {
1171                 err_pgsize = LPAGE_SIZE;
1172                 goto err;
1173         }
1174
1175         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1176                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1177                                 DMA_TO_DEVICE);
1178         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1179         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1180                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1181                                    DMA_TO_DEVICE);
1182         size = LPAGE_SIZE;
1183         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1184 done:
1185         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1186
1187         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1188
1189         return size;
1190 err:
1191         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1192
1193         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1194                 __func__, size, iova, err_pgsize);
1195
1196         return 0;
1197 }
1198
1199 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1200                                           dma_addr_t iova)
1201 {
1202         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1203         sysmmu_pte_t *entry;
1204         unsigned long flags;
1205         phys_addr_t phys = 0;
1206
1207         spin_lock_irqsave(&domain->pgtablelock, flags);
1208
1209         entry = section_entry(domain->pgtable, iova);
1210
1211         if (lv1ent_section(entry)) {
1212                 phys = section_phys(entry) + section_offs(iova);
1213         } else if (lv1ent_page(entry)) {
1214                 entry = page_entry(entry, iova);
1215
1216                 if (lv2ent_large(entry))
1217                         phys = lpage_phys(entry) + lpage_offs(iova);
1218                 else if (lv2ent_small(entry))
1219                         phys = spage_phys(entry) + spage_offs(iova);
1220         }
1221
1222         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1223
1224         return phys;
1225 }
1226
1227 static struct iommu_group *get_device_iommu_group(struct device *dev)
1228 {
1229         struct iommu_group *group;
1230
1231         group = iommu_group_get(dev);
1232         if (!group)
1233                 group = iommu_group_alloc();
1234
1235         return group;
1236 }
1237
1238 static int exynos_iommu_add_device(struct device *dev)
1239 {
1240         struct iommu_group *group;
1241
1242         if (!has_sysmmu(dev))
1243                 return -ENODEV;
1244
1245         group = iommu_group_get_for_dev(dev);
1246
1247         if (IS_ERR(group))
1248                 return PTR_ERR(group);
1249
1250         iommu_group_put(group);
1251
1252         return 0;
1253 }
1254
1255 static void exynos_iommu_remove_device(struct device *dev)
1256 {
1257         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1258
1259         if (!has_sysmmu(dev))
1260                 return;
1261
1262         if (owner->domain) {
1263                 struct iommu_group *group = iommu_group_get(dev);
1264
1265                 if (group) {
1266                         WARN_ON(owner->domain !=
1267                                 iommu_group_default_domain(group));
1268                         exynos_iommu_detach_device(owner->domain, dev);
1269                         iommu_group_put(group);
1270                 }
1271         }
1272         iommu_group_remove_device(dev);
1273 }
1274
1275 static int exynos_iommu_of_xlate(struct device *dev,
1276                                  struct of_phandle_args *spec)
1277 {
1278         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1279         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1280         struct sysmmu_drvdata *data, *entry;
1281
1282         if (!sysmmu)
1283                 return -ENODEV;
1284
1285         data = platform_get_drvdata(sysmmu);
1286         if (!data)
1287                 return -ENODEV;
1288
1289         if (!owner) {
1290                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1291                 if (!owner)
1292                         return -ENOMEM;
1293
1294                 INIT_LIST_HEAD(&owner->controllers);
1295                 mutex_init(&owner->rpm_lock);
1296                 dev->archdata.iommu = owner;
1297         }
1298
1299         list_for_each_entry(entry, &owner->controllers, owner_node)
1300                 if (entry == data)
1301                         return 0;
1302
1303         list_add_tail(&data->owner_node, &owner->controllers);
1304         data->master = dev;
1305
1306         /*
1307          * SYSMMU will be runtime activated via device link (dependency) to its
1308          * master device, so there are no direct calls to pm_runtime_get/put
1309          * in this driver.
1310          */
1311         device_link_add(dev, data->sysmmu, DL_FLAG_PM_RUNTIME);
1312
1313         return 0;
1314 }
1315
1316 static struct iommu_ops exynos_iommu_ops = {
1317         .domain_alloc = exynos_iommu_domain_alloc,
1318         .domain_free = exynos_iommu_domain_free,
1319         .attach_dev = exynos_iommu_attach_device,
1320         .detach_dev = exynos_iommu_detach_device,
1321         .map = exynos_iommu_map,
1322         .unmap = exynos_iommu_unmap,
1323         .map_sg = default_iommu_map_sg,
1324         .iova_to_phys = exynos_iommu_iova_to_phys,
1325         .device_group = get_device_iommu_group,
1326         .add_device = exynos_iommu_add_device,
1327         .remove_device = exynos_iommu_remove_device,
1328         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1329         .of_xlate = exynos_iommu_of_xlate,
1330 };
1331
1332 static bool init_done;
1333
1334 static int __init exynos_iommu_init(void)
1335 {
1336         int ret;
1337
1338         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1339                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1340         if (!lv2table_kmem_cache) {
1341                 pr_err("%s: Failed to create kmem cache\n", __func__);
1342                 return -ENOMEM;
1343         }
1344
1345         ret = platform_driver_register(&exynos_sysmmu_driver);
1346         if (ret) {
1347                 pr_err("%s: Failed to register driver\n", __func__);
1348                 goto err_reg_driver;
1349         }
1350
1351         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1352         if (zero_lv2_table == NULL) {
1353                 pr_err("%s: Failed to allocate zero level2 page table\n",
1354                         __func__);
1355                 ret = -ENOMEM;
1356                 goto err_zero_lv2;
1357         }
1358
1359         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1360         if (ret) {
1361                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1362                                                                 __func__);
1363                 goto err_set_iommu;
1364         }
1365
1366         init_done = true;
1367
1368         return 0;
1369 err_set_iommu:
1370         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1371 err_zero_lv2:
1372         platform_driver_unregister(&exynos_sysmmu_driver);
1373 err_reg_driver:
1374         kmem_cache_destroy(lv2table_kmem_cache);
1375         return ret;
1376 }
1377
1378 static int __init exynos_iommu_of_setup(struct device_node *np)
1379 {
1380         struct platform_device *pdev;
1381
1382         if (!init_done)
1383                 exynos_iommu_init();
1384
1385         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1386         if (!pdev)
1387                 return -ENODEV;
1388
1389         /*
1390          * use the first registered sysmmu device for performing
1391          * dma mapping operations on iommu page tables (cpu cache flush)
1392          */
1393         if (!dma_dev)
1394                 dma_dev = &pdev->dev;
1395
1396         return 0;
1397 }
1398
1399 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1400                  exynos_iommu_of_setup);