drivers/iommu/exynos-iommu.c

   1 /* linux/drivers/iommu/exynos_iommu.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  12 #define DEBUG
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/iommu.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/of.h>
  23 #include <linux/of_iommu.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/slab.h>
  28 #include <linux/dma-iommu.h>
  29
  30 typedef u32 sysmmu_iova_t;
  31 typedef u32 sysmmu_pte_t;
  32
  33 /* We do not consider super section mapping (16MB) */
  34 #define SECT_ORDER 20
  35 #define LPAGE_ORDER 16
  36 #define SPAGE_ORDER 12
  37
  38 #define SECT_SIZE (1 << SECT_ORDER)
  39 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  40 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  41
  42 #define SECT_MASK (~(SECT_SIZE - 1))
  43 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  44 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  45
  46 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  47                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  48 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  49 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  50 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  51                           ((*(sent) & 3) == 1))
  52 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  53
  54 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  55 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  56 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  57
  58 static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
  59 {
  60         return iova & (size - 1);
  61 }
  62
  63 #define section_phys(sent) (*(sent) & SECT_MASK)
  64 #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
  65 #define lpage_phys(pent) (*(pent) & LPAGE_MASK)
  66 #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
  67 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  68 #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
  69
  70 #define NUM_LV1ENTRIES 4096
  71 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  72
  73 static u32 lv1ent_offset(sysmmu_iova_t iova)
  74 {
  75         return iova >> SECT_ORDER;
  76 }
  77
  78 static u32 lv2ent_offset(sysmmu_iova_t iova)
  79 {
  80         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  81 }
  82
  83 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  84 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  85
  86 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  87
  88 #define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
  89
  90 #define mk_lv1ent_sect(pa) ((pa) | 2)
  91 #define mk_lv1ent_page(pa) ((pa) | 1)
  92 #define mk_lv2ent_lpage(pa) ((pa) | 1)
  93 #define mk_lv2ent_spage(pa) ((pa) | 2)
  94
  95 #define CTRL_ENABLE     0x5
  96 #define CTRL_BLOCK      0x7
  97 #define CTRL_DISABLE    0x0
  98
  99 #define CFG_LRU         0x1
 100 #define CFG_QOS(n)      ((n & 0xF) << 7)
 101 #define CFG_MASK        0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
 102 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 103 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 104 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 105
 106 #define REG_MMU_CTRL            0x000
 107 #define REG_MMU_CFG             0x004
 108 #define REG_MMU_STATUS          0x008
 109 #define REG_MMU_FLUSH           0x00C
 110 #define REG_MMU_FLUSH_ENTRY     0x010
 111 #define REG_PT_BASE_ADDR        0x014
 112 #define REG_INT_STATUS          0x018
 113 #define REG_INT_CLEAR           0x01C
 114
 115 #define REG_PAGE_FAULT_ADDR     0x024
 116 #define REG_AW_FAULT_ADDR       0x028
 117 #define REG_AR_FAULT_ADDR       0x02C
 118 #define REG_DEFAULT_SLAVE_ADDR  0x030
 119
 120 #define REG_MMU_VERSION         0x034
 121
 122 #define MMU_MAJ_VER(val)        ((val) >> 7)
 123 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 124 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 125
 126 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 127
 128 #define REG_PB0_SADDR           0x04C
 129 #define REG_PB0_EADDR           0x050
 130 #define REG_PB1_SADDR           0x054
 131 #define REG_PB1_EADDR           0x058
 132
 133 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 134
 135 static struct device *dma_dev;
 136 static struct kmem_cache *lv2table_kmem_cache;
 137 static sysmmu_pte_t *zero_lv2_table;
 138 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 139
 140 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 141 {
 142         return pgtable + lv1ent_offset(iova);
 143 }
 144
 145 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 146 {
 147         return (sysmmu_pte_t *)phys_to_virt(
 148                                 lv2table_base(sent)) + lv2ent_offset(iova);
 149 }
 150
 151 enum exynos_sysmmu_inttype {
 152         SYSMMU_PAGEFAULT,
 153         SYSMMU_AR_MULTIHIT,
 154         SYSMMU_AW_MULTIHIT,
 155         SYSMMU_BUSERROR,
 156         SYSMMU_AR_SECURITY,
 157         SYSMMU_AR_ACCESS,
 158         SYSMMU_AW_SECURITY,
 159         SYSMMU_AW_PROTECTION, /* 7 */
 160         SYSMMU_FAULT_UNKNOWN,
 161         SYSMMU_FAULTS_NUM
 162 };
 163
 164 static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
 165         REG_PAGE_FAULT_ADDR,
 166         REG_AR_FAULT_ADDR,
 167         REG_AW_FAULT_ADDR,
 168         REG_DEFAULT_SLAVE_ADDR,
 169         REG_AR_FAULT_ADDR,
 170         REG_AR_FAULT_ADDR,
 171         REG_AW_FAULT_ADDR,
 172         REG_AW_FAULT_ADDR
 173 };
 174
 175 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
 176         "PAGE FAULT",
 177         "AR MULTI-HIT FAULT",
 178         "AW MULTI-HIT FAULT",
 179         "BUS ERROR",
 180         "AR SECURITY PROTECTION FAULT",
 181         "AR ACCESS PROTECTION FAULT",
 182         "AW SECURITY PROTECTION FAULT",
 183         "AW ACCESS PROTECTION FAULT",
 184         "UNKNOWN FAULT"
 185 };
 186
 187 /*
 188  * This structure is attached to dev.archdata.iommu of the master device
 189  * on device add, contains a list of SYSMMU controllers defined by device tree,
 190  * which are bound to given master device. It is usually referenced by 'owner'
 191  * pointer.
 192 */
 193 struct exynos_iommu_owner {
 194         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 195 };
 196
 197 /*
 198  * This structure exynos specific generalization of struct iommu_domain.
 199  * It contains list of SYSMMU controllers from all master devices, which has
 200  * been attached to this domain and page tables of IO address space defined by
 201  * it. It is usually referenced by 'domain' pointer.
 202  */
 203 struct exynos_iommu_domain {
 204         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 205         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 206         short *lv2entcnt;       /* free lv2 entry counter for each section */
 207         spinlock_t lock;        /* lock for modyfying list of clients */
 208         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 209         struct iommu_domain domain; /* generic domain data structure */
 210 };
 211
 212 /*
 213  * This structure hold all data of a single SYSMMU controller, this includes
 214  * hw resources like registers and clocks, pointers and list nodes to connect
 215  * it to all other structures, internal state and parameters read from device
 216  * tree. It is usually referenced by 'data' pointer.
 217  */
 218 struct sysmmu_drvdata {
 219         struct device *sysmmu;          /* SYSMMU controller device */
 220         struct device *master;          /* master device (owner) */
 221         void __iomem *sfrbase;          /* our registers */
 222         struct clk *clk;                /* SYSMMU's clock */
 223         struct clk *clk_master;         /* master's device clock */
 224         int activations;                /* number of calls to sysmmu_enable */
 225         spinlock_t lock;                /* lock for modyfying state */
 226         struct exynos_iommu_domain *domain; /* domain we belong to */
 227         struct list_head domain_node;   /* node for domain clients list */
 228         struct list_head owner_node;    /* node for owner controllers list */
 229         phys_addr_t pgtable;            /* assigned page table structure */
 230         unsigned int version;           /* our version */
 231 };
 232
 233 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 234 {
 235         return container_of(dom, struct exynos_iommu_domain, domain);
 236 }
 237
 238 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 239 {
 240         /* return true if the System MMU was not active previously
 241            and it needs to be initialized */
 242         return ++data->activations == 1;
 243 }
 244
 245 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 246 {
 247         /* return true if the System MMU is needed to be disabled */
 248         BUG_ON(data->activations < 1);
 249         return --data->activations == 0;
 250 }
 251
 252 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 253 {
 254         return data->activations > 0;
 255 }
 256
 257 static void sysmmu_unblock(void __iomem *sfrbase)
 258 {
 259         __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
 260 }
 261
 262 static bool sysmmu_block(void __iomem *sfrbase)
 263 {
 264         int i = 120;
 265
 266         __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
 267         while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
 268                 --i;
 269
 270         if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
 271                 sysmmu_unblock(sfrbase);
 272                 return false;
 273         }
 274
 275         return true;
 276 }
 277
 278 static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
 279 {
 280         __raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
 281 }
 282
 283 static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
 284                                 sysmmu_iova_t iova, unsigned int num_inv)
 285 {
 286         unsigned int i;
 287
 288         for (i = 0; i < num_inv; i++) {
 289                 __raw_writel((iova & SPAGE_MASK) | 1,
 290                                 sfrbase + REG_MMU_FLUSH_ENTRY);
 291                 iova += SPAGE_SIZE;
 292         }
 293 }
 294
 295 static void __sysmmu_set_ptbase(void __iomem *sfrbase,
 296                                        phys_addr_t pgd)
 297 {
 298         __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
 299
 300         __sysmmu_tlb_invalidate(sfrbase);
 301 }
 302
 303 static void show_fault_information(const char *name,
 304                 enum exynos_sysmmu_inttype itype,
 305                 phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
 306 {
 307         sysmmu_pte_t *ent;
 308
 309         if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
 310                 itype = SYSMMU_FAULT_UNKNOWN;
 311
 312         pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
 313                 sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
 314
 315         ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
 316         pr_err("\tLv1 entry: %#x\n", *ent);
 317
 318         if (lv1ent_page(ent)) {
 319                 ent = page_entry(ent, fault_addr);
 320                 pr_err("\t Lv2 entry: %#x\n", *ent);
 321         }
 322 }
 323
 324 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 325 {
 326         /* SYSMMU is in blocked state when interrupt occurred. */
 327         struct sysmmu_drvdata *data = dev_id;
 328         enum exynos_sysmmu_inttype itype;
 329         sysmmu_iova_t addr = -1;
 330         int ret = -ENOSYS;
 331
 332         WARN_ON(!is_sysmmu_active(data));
 333
 334         spin_lock(&data->lock);
 335
 336         clk_enable(data->clk_master);
 337
 338         itype = (enum exynos_sysmmu_inttype)
 339                 __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
 340         if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
 341                 itype = SYSMMU_FAULT_UNKNOWN;
 342         else
 343                 addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
 344
 345         if (itype == SYSMMU_FAULT_UNKNOWN) {
 346                 pr_err("%s: Fault is not occurred by System MMU '%s'!\n",
 347                         __func__, dev_name(data->sysmmu));
 348                 pr_err("%s: Please check if IRQ is correctly configured.\n",
 349                         __func__);
 350                 BUG();
 351         } else {
 352                 unsigned int base =
 353                                 __raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
 354                 show_fault_information(dev_name(data->sysmmu),
 355                                         itype, base, addr);
 356                 if (data->domain)
 357                         ret = report_iommu_fault(&data->domain->domain,
 358                                         data->master, addr, itype);
 359         }
 360
 361         /* fault is not recovered by fault handler */
 362         BUG_ON(ret != 0);
 363
 364         __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
 365
 366         sysmmu_unblock(data->sfrbase);
 367
 368         clk_disable(data->clk_master);
 369
 370         spin_unlock(&data->lock);
 371
 372         return IRQ_HANDLED;
 373 }
 374
 375 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 376 {
 377         clk_enable(data->clk_master);
 378
 379         __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 380         __raw_writel(0, data->sfrbase + REG_MMU_CFG);
 381
 382         clk_disable(data->clk);
 383         clk_disable(data->clk_master);
 384 }
 385
 386 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 387 {
 388         bool disabled;
 389         unsigned long flags;
 390
 391         spin_lock_irqsave(&data->lock, flags);
 392
 393         disabled = set_sysmmu_inactive(data);
 394
 395         if (disabled) {
 396                 data->pgtable = 0;
 397                 data->domain = NULL;
 398
 399                 __sysmmu_disable_nocount(data);
 400
 401                 dev_dbg(data->sysmmu, "Disabled\n");
 402         } else  {
 403                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 404                                         data->activations);
 405         }
 406
 407         spin_unlock_irqrestore(&data->lock, flags);
 408
 409         return disabled;
 410 }
 411
 412 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 413 {
 414         unsigned int cfg = CFG_LRU | CFG_QOS(15);
 415         unsigned int ver;
 416
 417         ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
 418         if (MMU_MAJ_VER(ver) == 3) {
 419                 if (MMU_MIN_VER(ver) >= 2) {
 420                         cfg |= CFG_FLPDCACHE;
 421                         if (MMU_MIN_VER(ver) == 3) {
 422                                 cfg |= CFG_ACGEN;
 423                                 cfg &= ~CFG_LRU;
 424                         } else {
 425                                 cfg |= CFG_SYSSEL;
 426                         }
 427                 }
 428         }
 429
 430         __raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
 431         data->version = ver;
 432 }
 433
 434 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 435 {
 436         clk_enable(data->clk_master);
 437         clk_enable(data->clk);
 438
 439         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 440
 441         __sysmmu_init_config(data);
 442
 443         __sysmmu_set_ptbase(data->sfrbase, data->pgtable);
 444
 445         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 446
 447         clk_disable(data->clk_master);
 448 }
 449
 450 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 451                            struct exynos_iommu_domain *domain)
 452 {
 453         int ret = 0;
 454         unsigned long flags;
 455
 456         spin_lock_irqsave(&data->lock, flags);
 457         if (set_sysmmu_active(data)) {
 458                 data->pgtable = pgtable;
 459                 data->domain = domain;
 460
 461                 __sysmmu_enable_nocount(data);
 462
 463                 dev_dbg(data->sysmmu, "Enabled\n");
 464         } else {
 465                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 466
 467                 dev_dbg(data->sysmmu, "already enabled\n");
 468         }
 469
 470         if (WARN_ON(ret < 0))
 471                 set_sysmmu_inactive(data); /* decrement count */
 472
 473         spin_unlock_irqrestore(&data->lock, flags);
 474
 475         return ret;
 476 }
 477
 478 static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 479                                               sysmmu_iova_t iova)
 480 {
 481         if (data->version == MAKE_MMU_VER(3, 3))
 482                 __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY);
 483 }
 484
 485 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 486                                             sysmmu_iova_t iova)
 487 {
 488         unsigned long flags;
 489
 490         clk_enable(data->clk_master);
 491
 492         spin_lock_irqsave(&data->lock, flags);
 493         if (is_sysmmu_active(data))
 494                 __sysmmu_tlb_invalidate_flpdcache(data, iova);
 495         spin_unlock_irqrestore(&data->lock, flags);
 496
 497         clk_disable(data->clk_master);
 498 }
 499
 500 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 501                                         sysmmu_iova_t iova, size_t size)
 502 {
 503         unsigned long flags;
 504
 505         spin_lock_irqsave(&data->lock, flags);
 506         if (is_sysmmu_active(data)) {
 507                 unsigned int num_inv = 1;
 508
 509                 clk_enable(data->clk_master);
 510
 511                 /*
 512                  * L2TLB invalidation required
 513                  * 4KB page: 1 invalidation
 514                  * 64KB page: 16 invalidations
 515                  * 1MB page: 64 invalidations
 516                  * because it is set-associative TLB
 517                  * with 8-way and 64 sets.
 518                  * 1MB page can be cached in one of all sets.
 519                  * 64KB page can be one of 16 consecutive sets.
 520                  */
 521                 if (MMU_MAJ_VER(data->version) == 2)
 522                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 523
 524                 if (sysmmu_block(data->sfrbase)) {
 525                         __sysmmu_tlb_invalidate_entry(
 526                                 data->sfrbase, iova, num_inv);
 527                         sysmmu_unblock(data->sfrbase);
 528                 }
 529                 clk_disable(data->clk_master);
 530         } else {
 531                 dev_dbg(data->master,
 532                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 533         }
 534         spin_unlock_irqrestore(&data->lock, flags);
 535 }
 536
 537 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 538 {
 539         int irq, ret;
 540         struct device *dev = &pdev->dev;
 541         struct sysmmu_drvdata *data;
 542         struct resource *res;
 543
 544         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 545         if (!data)
 546                 return -ENOMEM;
 547
 548         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 549         data->sfrbase = devm_ioremap_resource(dev, res);
 550         if (IS_ERR(data->sfrbase))
 551                 return PTR_ERR(data->sfrbase);
 552
 553         irq = platform_get_irq(pdev, 0);
 554         if (irq <= 0) {
 555                 dev_err(dev, "Unable to find IRQ resource\n");
 556                 return irq;
 557         }
 558
 559         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 560                                 dev_name(dev), data);
 561         if (ret) {
 562                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 563                 return ret;
 564         }
 565
 566         data->clk = devm_clk_get(dev, "sysmmu");
 567         if (IS_ERR(data->clk)) {
 568                 dev_err(dev, "Failed to get clock!\n");
 569                 return PTR_ERR(data->clk);
 570         } else  {
 571                 ret = clk_prepare(data->clk);
 572                 if (ret) {
 573                         dev_err(dev, "Failed to prepare clk\n");
 574                         return ret;
 575                 }
 576         }
 577
 578         data->clk_master = devm_clk_get(dev, "master");
 579         if (!IS_ERR(data->clk_master)) {
 580                 ret = clk_prepare(data->clk_master);
 581                 if (ret) {
 582                         clk_unprepare(data->clk);
 583                         dev_err(dev, "Failed to prepare master's clk\n");
 584                         return ret;
 585                 }
 586         } else {
 587                 data->clk_master = NULL;
 588         }
 589
 590         data->sysmmu = dev;
 591         spin_lock_init(&data->lock);
 592
 593         platform_set_drvdata(pdev, data);
 594
 595         pm_runtime_enable(dev);
 596
 597         return 0;
 598 }
 599
 600 #ifdef CONFIG_PM_SLEEP
 601 static int exynos_sysmmu_suspend(struct device *dev)
 602 {
 603         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 604
 605         dev_dbg(dev, "suspend\n");
 606         if (is_sysmmu_active(data)) {
 607                 __sysmmu_disable_nocount(data);
 608                 pm_runtime_put(dev);
 609         }
 610         return 0;
 611 }
 612
 613 static int exynos_sysmmu_resume(struct device *dev)
 614 {
 615         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 616
 617         dev_dbg(dev, "resume\n");
 618         if (is_sysmmu_active(data)) {
 619                 pm_runtime_get_sync(dev);
 620                 __sysmmu_enable_nocount(data);
 621         }
 622         return 0;
 623 }
 624 #endif
 625
 626 static const struct dev_pm_ops sysmmu_pm_ops = {
 627         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 628 };
 629
 630 static const struct of_device_id sysmmu_of_match[] __initconst = {
 631         { .compatible   = "samsung,exynos-sysmmu", },
 632         { },
 633 };
 634
 635 static struct platform_driver exynos_sysmmu_driver __refdata = {
 636         .probe  = exynos_sysmmu_probe,
 637         .driver = {
 638                 .name           = "exynos-sysmmu",
 639                 .of_match_table = sysmmu_of_match,
 640                 .pm             = &sysmmu_pm_ops,
 641         }
 642 };
 643
 644 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 645 {
 646         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 647                                 DMA_TO_DEVICE);
 648         *ent = val;
 649         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 650                                    DMA_TO_DEVICE);
 651 }
 652
 653 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 654 {
 655         struct exynos_iommu_domain *domain;
 656         dma_addr_t handle;
 657         int i;
 658
 659
 660         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 661         if (!domain)
 662                 return NULL;
 663
 664         if (type == IOMMU_DOMAIN_DMA) {
 665                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 666                         goto err_pgtable;
 667         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 668                 goto err_pgtable;
 669         }
 670
 671         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 672         if (!domain->pgtable)
 673                 goto err_dma_cookie;
 674
 675         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 676         if (!domain->lv2entcnt)
 677                 goto err_counter;
 678
 679         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 680         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 681                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 682                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 683                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 684                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 685                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 686                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 687                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 688                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 689         }
 690
 691         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 692                                 DMA_TO_DEVICE);
 693         /* For mapping page table entries we rely on dma == phys */
 694         BUG_ON(handle != virt_to_phys(domain->pgtable));
 695
 696         spin_lock_init(&domain->lock);
 697         spin_lock_init(&domain->pgtablelock);
 698         INIT_LIST_HEAD(&domain->clients);
 699
 700         domain->domain.geometry.aperture_start = 0;
 701         domain->domain.geometry.aperture_end   = ~0UL;
 702         domain->domain.geometry.force_aperture = true;
 703
 704         return &domain->domain;
 705
 706 err_counter:
 707         free_pages((unsigned long)domain->pgtable, 2);
 708 err_dma_cookie:
 709         if (type == IOMMU_DOMAIN_DMA)
 710                 iommu_put_dma_cookie(&domain->domain);
 711 err_pgtable:
 712         kfree(domain);
 713         return NULL;
 714 }
 715
 716 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 717 {
 718         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 719         struct sysmmu_drvdata *data, *next;
 720         unsigned long flags;
 721         int i;
 722
 723         WARN_ON(!list_empty(&domain->clients));
 724
 725         spin_lock_irqsave(&domain->lock, flags);
 726
 727         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 728                 if (__sysmmu_disable(data))
 729                         data->master = NULL;
 730                 list_del_init(&data->domain_node);
 731         }
 732
 733         spin_unlock_irqrestore(&domain->lock, flags);
 734
 735         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 736                 iommu_put_dma_cookie(iommu_domain);
 737
 738         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 739                          DMA_TO_DEVICE);
 740
 741         for (i = 0; i < NUM_LV1ENTRIES; i++)
 742                 if (lv1ent_page(domain->pgtable + i)) {
 743                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 744
 745                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 746                                          DMA_TO_DEVICE);
 747                         kmem_cache_free(lv2table_kmem_cache,
 748                                         phys_to_virt(base));
 749                 }
 750
 751         free_pages((unsigned long)domain->pgtable, 2);
 752         free_pages((unsigned long)domain->lv2entcnt, 1);
 753         kfree(domain);
 754 }
 755
 756 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 757                                    struct device *dev)
 758 {
 759         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 760         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 761         struct sysmmu_drvdata *data;
 762         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 763         unsigned long flags;
 764         int ret = -ENODEV;
 765
 766         if (!has_sysmmu(dev))
 767                 return -ENODEV;
 768
 769         list_for_each_entry(data, &owner->controllers, owner_node) {
 770                 pm_runtime_get_sync(data->sysmmu);
 771                 ret = __sysmmu_enable(data, pagetable, domain);
 772                 if (ret >= 0) {
 773                         data->master = dev;
 774
 775                         spin_lock_irqsave(&domain->lock, flags);
 776                         list_add_tail(&data->domain_node, &domain->clients);
 777                         spin_unlock_irqrestore(&domain->lock, flags);
 778                 }
 779         }
 780
 781         if (ret < 0) {
 782                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 783                                         __func__, &pagetable);
 784                 return ret;
 785         }
 786
 787         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 788                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 789
 790         return ret;
 791 }
 792
 793 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 794                                     struct device *dev)
 795 {
 796         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 797         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 798         struct sysmmu_drvdata *data, *next;
 799         unsigned long flags;
 800         bool found = false;
 801
 802         if (!has_sysmmu(dev))
 803                 return;
 804
 805         spin_lock_irqsave(&domain->lock, flags);
 806         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 807                 if (data->master == dev) {
 808                         if (__sysmmu_disable(data)) {
 809                                 data->master = NULL;
 810                                 list_del_init(&data->domain_node);
 811                         }
 812                         pm_runtime_put(data->sysmmu);
 813                         found = true;
 814                 }
 815         }
 816         spin_unlock_irqrestore(&domain->lock, flags);
 817
 818         if (found)
 819                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 820                                         __func__, &pagetable);
 821         else
 822                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 823 }
 824
 825 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 826                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 827 {
 828         if (lv1ent_section(sent)) {
 829                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 830                 return ERR_PTR(-EADDRINUSE);
 831         }
 832
 833         if (lv1ent_fault(sent)) {
 834                 sysmmu_pte_t *pent;
 835                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 836
 837                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 838                 BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
 839                 if (!pent)
 840                         return ERR_PTR(-ENOMEM);
 841
 842                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 843                 kmemleak_ignore(pent);
 844                 *pgcounter = NUM_LV2ENTRIES;
 845                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 846
 847                 /*
 848                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 849                  * FLPD cache may cache the address of zero_l2_table. This
 850                  * function replaces the zero_l2_table with new L2 page table
 851                  * to write valid mappings.
 852                  * Accessing the valid area may cause page fault since FLPD
 853                  * cache may still cache zero_l2_table for the valid area
 854                  * instead of new L2 page table that has the mapping
 855                  * information of the valid area.
 856                  * Thus any replacement of zero_l2_table with other valid L2
 857                  * page table must involve FLPD cache invalidation for System
 858                  * MMU v3.3.
 859                  * FLPD cache invalidation is performed with TLB invalidation
 860                  * by VPN without blocking. It is safe to invalidate TLB without
 861                  * blocking because the target address of TLB invalidation is
 862                  * not currently mapped.
 863                  */
 864                 if (need_flush_flpd_cache) {
 865                         struct sysmmu_drvdata *data;
 866
 867                         spin_lock(&domain->lock);
 868                         list_for_each_entry(data, &domain->clients, domain_node)
 869                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 870                         spin_unlock(&domain->lock);
 871                 }
 872         }
 873
 874         return page_entry(sent, iova);
 875 }
 876
 877 static int lv1set_section(struct exynos_iommu_domain *domain,
 878                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 879                           phys_addr_t paddr, short *pgcnt)
 880 {
 881         if (lv1ent_section(sent)) {
 882                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 883                         iova);
 884                 return -EADDRINUSE;
 885         }
 886
 887         if (lv1ent_page(sent)) {
 888                 if (*pgcnt != NUM_LV2ENTRIES) {
 889                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 890                                 iova);
 891                         return -EADDRINUSE;
 892                 }
 893
 894                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 895                 *pgcnt = 0;
 896         }
 897
 898         update_pte(sent, mk_lv1ent_sect(paddr));
 899
 900         spin_lock(&domain->lock);
 901         if (lv1ent_page_zero(sent)) {
 902                 struct sysmmu_drvdata *data;
 903                 /*
 904                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 905                  * entry by speculative prefetch of SLPD which has no mapping.
 906                  */
 907                 list_for_each_entry(data, &domain->clients, domain_node)
 908                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 909         }
 910         spin_unlock(&domain->lock);
 911
 912         return 0;
 913 }
 914
 915 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 916                                                                 short *pgcnt)
 917 {
 918         if (size == SPAGE_SIZE) {
 919                 if (WARN_ON(!lv2ent_fault(pent)))
 920                         return -EADDRINUSE;
 921
 922                 update_pte(pent, mk_lv2ent_spage(paddr));
 923                 *pgcnt -= 1;
 924         } else { /* size == LPAGE_SIZE */
 925                 int i;
 926                 dma_addr_t pent_base = virt_to_phys(pent);
 927
 928                 dma_sync_single_for_cpu(dma_dev, pent_base,
 929                                         sizeof(*pent) * SPAGES_PER_LPAGE,
 930                                         DMA_TO_DEVICE);
 931                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
 932                         if (WARN_ON(!lv2ent_fault(pent))) {
 933                                 if (i > 0)
 934                                         memset(pent - i, 0, sizeof(*pent) * i);
 935                                 return -EADDRINUSE;
 936                         }
 937
 938                         *pent = mk_lv2ent_lpage(paddr);
 939                 }
 940                 dma_sync_single_for_device(dma_dev, pent_base,
 941                                            sizeof(*pent) * SPAGES_PER_LPAGE,
 942                                            DMA_TO_DEVICE);
 943                 *pgcnt -= SPAGES_PER_LPAGE;
 944         }
 945
 946         return 0;
 947 }
 948
 949 /*
 950  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
 951  *
 952  * System MMU v3.x has advanced logic to improve address translation
 953  * performance with caching more page table entries by a page table walk.
 954  * However, the logic has a bug that while caching faulty page table entries,
 955  * System MMU reports page fault if the cached fault entry is hit even though
 956  * the fault entry is updated to a valid entry after the entry is cached.
 957  * To prevent caching faulty page table entries which may be updated to valid
 958  * entries later, the virtual memory manager should care about the workaround
 959  * for the problem. The following describes the workaround.
 960  *
 961  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
 962  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
 963  *
 964  * Precisely, any start address of I/O virtual region must be aligned with
 965  * the following sizes for System MMU v3.1 and v3.2.
 966  * System MMU v3.1: 128KiB
 967  * System MMU v3.2: 256KiB
 968  *
 969  * Because System MMU v3.3 caches page table entries more aggressively, it needs
 970  * more workarounds.
 971  * - Any two consecutive I/O virtual regions must have a hole of size larger
 972  *   than or equal to 128KiB.
 973  * - Start address of an I/O virtual region must be aligned by 128KiB.
 974  */
 975 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
 976                             unsigned long l_iova, phys_addr_t paddr, size_t size,
 977                             int prot)
 978 {
 979         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 980         sysmmu_pte_t *entry;
 981         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
 982         unsigned long flags;
 983         int ret = -ENOMEM;
 984
 985         BUG_ON(domain->pgtable == NULL);
 986
 987         spin_lock_irqsave(&domain->pgtablelock, flags);
 988
 989         entry = section_entry(domain->pgtable, iova);
 990
 991         if (size == SECT_SIZE) {
 992                 ret = lv1set_section(domain, entry, iova, paddr,
 993                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
 994         } else {
 995                 sysmmu_pte_t *pent;
 996
 997                 pent = alloc_lv2entry(domain, entry, iova,
 998                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
 999
1000                 if (IS_ERR(pent))
1001                         ret = PTR_ERR(pent);
1002                 else
1003                         ret = lv2set_page(pent, paddr, size,
1004                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1005         }
1006
1007         if (ret)
1008                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1009                         __func__, ret, size, iova);
1010
1011         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1012
1013         return ret;
1014 }
1015
1016 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1017                                               sysmmu_iova_t iova, size_t size)
1018 {
1019         struct sysmmu_drvdata *data;
1020         unsigned long flags;
1021
1022         spin_lock_irqsave(&domain->lock, flags);
1023
1024         list_for_each_entry(data, &domain->clients, domain_node)
1025                 sysmmu_tlb_invalidate_entry(data, iova, size);
1026
1027         spin_unlock_irqrestore(&domain->lock, flags);
1028 }
1029
1030 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1031                                  unsigned long l_iova, size_t size)
1032 {
1033         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1034         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1035         sysmmu_pte_t *ent;
1036         size_t err_pgsize;
1037         unsigned long flags;
1038
1039         BUG_ON(domain->pgtable == NULL);
1040
1041         spin_lock_irqsave(&domain->pgtablelock, flags);
1042
1043         ent = section_entry(domain->pgtable, iova);
1044
1045         if (lv1ent_section(ent)) {
1046                 if (WARN_ON(size < SECT_SIZE)) {
1047                         err_pgsize = SECT_SIZE;
1048                         goto err;
1049                 }
1050
1051                 /* workaround for h/w bug in System MMU v3.3 */
1052                 update_pte(ent, ZERO_LV2LINK);
1053                 size = SECT_SIZE;
1054                 goto done;
1055         }
1056
1057         if (unlikely(lv1ent_fault(ent))) {
1058                 if (size > SECT_SIZE)
1059                         size = SECT_SIZE;
1060                 goto done;
1061         }
1062
1063         /* lv1ent_page(sent) == true here */
1064
1065         ent = page_entry(ent, iova);
1066
1067         if (unlikely(lv2ent_fault(ent))) {
1068                 size = SPAGE_SIZE;
1069                 goto done;
1070         }
1071
1072         if (lv2ent_small(ent)) {
1073                 update_pte(ent, 0);
1074                 size = SPAGE_SIZE;
1075                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1076                 goto done;
1077         }
1078
1079         /* lv1ent_large(ent) == true here */
1080         if (WARN_ON(size < LPAGE_SIZE)) {
1081                 err_pgsize = LPAGE_SIZE;
1082                 goto err;
1083         }
1084
1085         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1086                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1087                                 DMA_TO_DEVICE);
1088         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1089         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1090                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1091                                    DMA_TO_DEVICE);
1092         size = LPAGE_SIZE;
1093         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1094 done:
1095         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1096
1097         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1098
1099         return size;
1100 err:
1101         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1102
1103         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1104                 __func__, size, iova, err_pgsize);
1105
1106         return 0;
1107 }
1108
1109 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1110                                           dma_addr_t iova)
1111 {
1112         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1113         sysmmu_pte_t *entry;
1114         unsigned long flags;
1115         phys_addr_t phys = 0;
1116
1117         spin_lock_irqsave(&domain->pgtablelock, flags);
1118
1119         entry = section_entry(domain->pgtable, iova);
1120
1121         if (lv1ent_section(entry)) {
1122                 phys = section_phys(entry) + section_offs(iova);
1123         } else if (lv1ent_page(entry)) {
1124                 entry = page_entry(entry, iova);
1125
1126                 if (lv2ent_large(entry))
1127                         phys = lpage_phys(entry) + lpage_offs(iova);
1128                 else if (lv2ent_small(entry))
1129                         phys = spage_phys(entry) + spage_offs(iova);
1130         }
1131
1132         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1133
1134         return phys;
1135 }
1136
1137 static struct iommu_group *get_device_iommu_group(struct device *dev)
1138 {
1139         struct iommu_group *group;
1140
1141         group = iommu_group_get(dev);
1142         if (!group)
1143                 group = iommu_group_alloc();
1144
1145         return group;
1146 }
1147
1148 static int exynos_iommu_add_device(struct device *dev)
1149 {
1150         struct iommu_group *group;
1151
1152         if (!has_sysmmu(dev))
1153                 return -ENODEV;
1154
1155         group = iommu_group_get_for_dev(dev);
1156
1157         if (IS_ERR(group))
1158                 return PTR_ERR(group);
1159
1160         iommu_group_put(group);
1161
1162         return 0;
1163 }
1164
1165 static void exynos_iommu_remove_device(struct device *dev)
1166 {
1167         if (!has_sysmmu(dev))
1168                 return;
1169
1170         iommu_group_remove_device(dev);
1171 }
1172
1173 static int exynos_iommu_of_xlate(struct device *dev,
1174                                  struct of_phandle_args *spec)
1175 {
1176         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1177         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1178         struct sysmmu_drvdata *data;
1179
1180         if (!sysmmu)
1181                 return -ENODEV;
1182
1183         data = platform_get_drvdata(sysmmu);
1184         if (!data)
1185                 return -ENODEV;
1186
1187         if (!owner) {
1188                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1189                 if (!owner)
1190                         return -ENOMEM;
1191
1192                 INIT_LIST_HEAD(&owner->controllers);
1193                 dev->archdata.iommu = owner;
1194         }
1195
1196         list_add_tail(&data->owner_node, &owner->controllers);
1197         return 0;
1198 }
1199
1200 static struct iommu_ops exynos_iommu_ops = {
1201         .domain_alloc = exynos_iommu_domain_alloc,
1202         .domain_free = exynos_iommu_domain_free,
1203         .attach_dev = exynos_iommu_attach_device,
1204         .detach_dev = exynos_iommu_detach_device,
1205         .map = exynos_iommu_map,
1206         .unmap = exynos_iommu_unmap,
1207         .map_sg = default_iommu_map_sg,
1208         .iova_to_phys = exynos_iommu_iova_to_phys,
1209         .device_group = get_device_iommu_group,
1210         .add_device = exynos_iommu_add_device,
1211         .remove_device = exynos_iommu_remove_device,
1212         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1213         .of_xlate = exynos_iommu_of_xlate,
1214 };
1215
1216 static bool init_done;
1217
1218 static int __init exynos_iommu_init(void)
1219 {
1220         int ret;
1221
1222         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1223                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1224         if (!lv2table_kmem_cache) {
1225                 pr_err("%s: Failed to create kmem cache\n", __func__);
1226                 return -ENOMEM;
1227         }
1228
1229         ret = platform_driver_register(&exynos_sysmmu_driver);
1230         if (ret) {
1231                 pr_err("%s: Failed to register driver\n", __func__);
1232                 goto err_reg_driver;
1233         }
1234
1235         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1236         if (zero_lv2_table == NULL) {
1237                 pr_err("%s: Failed to allocate zero level2 page table\n",
1238                         __func__);
1239                 ret = -ENOMEM;
1240                 goto err_zero_lv2;
1241         }
1242
1243         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1244         if (ret) {
1245                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1246                                                                 __func__);
1247                 goto err_set_iommu;
1248         }
1249
1250         init_done = true;
1251
1252         return 0;
1253 err_set_iommu:
1254         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1255 err_zero_lv2:
1256         platform_driver_unregister(&exynos_sysmmu_driver);
1257 err_reg_driver:
1258         kmem_cache_destroy(lv2table_kmem_cache);
1259         return ret;
1260 }
1261
1262 static int __init exynos_iommu_of_setup(struct device_node *np)
1263 {
1264         struct platform_device *pdev;
1265
1266         if (!init_done)
1267                 exynos_iommu_init();
1268
1269         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1270         if (IS_ERR(pdev))
1271                 return PTR_ERR(pdev);
1272
1273         /*
1274          * use the first registered sysmmu device for performing
1275          * dma mapping operations on iommu page tables (cpu cache flush)
1276          */
1277         if (!dma_dev)
1278                 dma_dev = &pdev->dev;
1279
1280         of_iommu_set_ops(np, &exynos_iommu_ops);
1281         return 0;
1282 }
1283
1284 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1285                  exynos_iommu_of_setup);