drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 /*
  58  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  59  * v5.0 introduced support for 36bit physical address space by shifting
  60  * all page entry values by 4 bits.
  61  * All SYSMMU controllers in the system support the address spaces of the same
  62  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  63  * value (0 or 4).
  64  */
  65 static short PG_ENT_SHIFT = -1;
  66 #define SYSMMU_PG_ENT_SHIFT 0
  67 #define SYSMMU_V5_PG_ENT_SHIFT 4
  68
  69 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
  70 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
  71 #define section_offs(iova) (iova & (SECT_SIZE - 1))
  72 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
  73 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
  74 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
  75 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
  76
  77 #define NUM_LV1ENTRIES 4096
  78 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  79
  80 static u32 lv1ent_offset(sysmmu_iova_t iova)
  81 {
  82         return iova >> SECT_ORDER;
  83 }
  84
  85 static u32 lv2ent_offset(sysmmu_iova_t iova)
  86 {
  87         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  88 }
  89
  90 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  91 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  92
  93 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  94 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
  95
  96 #define mk_lv1ent_sect(pa) ((pa >> PG_ENT_SHIFT) | 2)
  97 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
  98 #define mk_lv2ent_lpage(pa) ((pa >> PG_ENT_SHIFT) | 1)
  99 #define mk_lv2ent_spage(pa) ((pa >> PG_ENT_SHIFT) | 2)
 100
 101 #define CTRL_ENABLE     0x5
 102 #define CTRL_BLOCK      0x7
 103 #define CTRL_DISABLE    0x0
 104
 105 #define CFG_LRU         0x1
 106 #define CFG_QOS(n)      ((n & 0xF) << 7)
 107 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 108 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 109 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 110
 111 /* common registers */
 112 #define REG_MMU_CTRL            0x000
 113 #define REG_MMU_CFG             0x004
 114 #define REG_MMU_STATUS          0x008
 115 #define REG_MMU_VERSION         0x034
 116
 117 #define MMU_MAJ_VER(val)        ((val) >> 7)
 118 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 119 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 120
 121 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 122
 123 /* v1.x - v3.x registers */
 124 #define REG_MMU_FLUSH           0x00C
 125 #define REG_MMU_FLUSH_ENTRY     0x010
 126 #define REG_PT_BASE_ADDR        0x014
 127 #define REG_INT_STATUS          0x018
 128 #define REG_INT_CLEAR           0x01C
 129
 130 #define REG_PAGE_FAULT_ADDR     0x024
 131 #define REG_AW_FAULT_ADDR       0x028
 132 #define REG_AR_FAULT_ADDR       0x02C
 133 #define REG_DEFAULT_SLAVE_ADDR  0x030
 134
 135 /* v5.x registers */
 136 #define REG_V5_PT_BASE_PFN      0x00C
 137 #define REG_V5_MMU_FLUSH_ALL    0x010
 138 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 139 #define REG_V5_INT_STATUS       0x060
 140 #define REG_V5_INT_CLEAR        0x064
 141 #define REG_V5_FAULT_AR_VA      0x070
 142 #define REG_V5_FAULT_AW_VA      0x080
 143
 144 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 145
 146 static struct device *dma_dev;
 147 static struct kmem_cache *lv2table_kmem_cache;
 148 static sysmmu_pte_t *zero_lv2_table;
 149 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 150
 151 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 152 {
 153         return pgtable + lv1ent_offset(iova);
 154 }
 155
 156 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 157 {
 158         return (sysmmu_pte_t *)phys_to_virt(
 159                                 lv2table_base(sent)) + lv2ent_offset(iova);
 160 }
 161
 162 /*
 163  * IOMMU fault information register
 164  */
 165 struct sysmmu_fault_info {
 166         unsigned int bit;       /* bit number in STATUS register */
 167         unsigned short addr_reg; /* register to read VA fault address */
 168         const char *name;       /* human readable fault name */
 169         unsigned int type;      /* fault type for report_iommu_fault */
 170 };
 171
 172 static const struct sysmmu_fault_info sysmmu_faults[] = {
 173         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 174         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 175         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 176         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 177         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 178         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 179         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 180         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 181 };
 182
 183 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 184         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 185         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 186         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 187         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 188         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 189         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 190         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 191         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 192         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 193         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 194 };
 195
 196 /*
 197  * This structure is attached to dev.archdata.iommu of the master device
 198  * on device add, contains a list of SYSMMU controllers defined by device tree,
 199  * which are bound to given master device. It is usually referenced by 'owner'
 200  * pointer.
 201 */
 202 struct exynos_iommu_owner {
 203         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 204         struct iommu_domain *domain;    /* domain this device is attached */
 205 };
 206
 207 /*
 208  * This structure exynos specific generalization of struct iommu_domain.
 209  * It contains list of SYSMMU controllers from all master devices, which has
 210  * been attached to this domain and page tables of IO address space defined by
 211  * it. It is usually referenced by 'domain' pointer.
 212  */
 213 struct exynos_iommu_domain {
 214         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 215         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 216         short *lv2entcnt;       /* free lv2 entry counter for each section */
 217         spinlock_t lock;        /* lock for modyfying list of clients */
 218         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 219         struct iommu_domain domain; /* generic domain data structure */
 220 };
 221
 222 /*
 223  * This structure hold all data of a single SYSMMU controller, this includes
 224  * hw resources like registers and clocks, pointers and list nodes to connect
 225  * it to all other structures, internal state and parameters read from device
 226  * tree. It is usually referenced by 'data' pointer.
 227  */
 228 struct sysmmu_drvdata {
 229         struct device *sysmmu;          /* SYSMMU controller device */
 230         struct device *master;          /* master device (owner) */
 231         void __iomem *sfrbase;          /* our registers */
 232         struct clk *clk;                /* SYSMMU's clock */
 233         struct clk *aclk;               /* SYSMMU's aclk clock */
 234         struct clk *pclk;               /* SYSMMU's pclk clock */
 235         struct clk *clk_master;         /* master's device clock */
 236         int activations;                /* number of calls to sysmmu_enable */
 237         spinlock_t lock;                /* lock for modyfying state */
 238         struct exynos_iommu_domain *domain; /* domain we belong to */
 239         struct list_head domain_node;   /* node for domain clients list */
 240         struct list_head owner_node;    /* node for owner controllers list */
 241         phys_addr_t pgtable;            /* assigned page table structure */
 242         unsigned int version;           /* our version */
 243 };
 244
 245 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 246 {
 247         return container_of(dom, struct exynos_iommu_domain, domain);
 248 }
 249
 250 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 251 {
 252         /* return true if the System MMU was not active previously
 253            and it needs to be initialized */
 254         return ++data->activations == 1;
 255 }
 256
 257 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 258 {
 259         /* return true if the System MMU is needed to be disabled */
 260         BUG_ON(data->activations < 1);
 261         return --data->activations == 0;
 262 }
 263
 264 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 265 {
 266         return data->activations > 0;
 267 }
 268
 269 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 270 {
 271         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 272 }
 273
 274 static bool sysmmu_block(struct sysmmu_drvdata *data)
 275 {
 276         int i = 120;
 277
 278         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 279         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 280                 --i;
 281
 282         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 283                 sysmmu_unblock(data);
 284                 return false;
 285         }
 286
 287         return true;
 288 }
 289
 290 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 291 {
 292         if (MMU_MAJ_VER(data->version) < 5)
 293                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 294         else
 295                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 296 }
 297
 298 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 299                                 sysmmu_iova_t iova, unsigned int num_inv)
 300 {
 301         unsigned int i;
 302
 303         for (i = 0; i < num_inv; i++) {
 304                 if (MMU_MAJ_VER(data->version) < 5)
 305                         writel((iova & SPAGE_MASK) | 1,
 306                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 307                 else
 308                         writel((iova & SPAGE_MASK) | 1,
 309                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 310                 iova += SPAGE_SIZE;
 311         }
 312 }
 313
 314 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 315 {
 316         if (MMU_MAJ_VER(data->version) < 5)
 317                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 318         else
 319                 writel(pgd >> PAGE_SHIFT,
 320                              data->sfrbase + REG_V5_PT_BASE_PFN);
 321
 322         __sysmmu_tlb_invalidate(data);
 323 }
 324
 325 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 326 {
 327         BUG_ON(clk_prepare_enable(data->clk_master));
 328         BUG_ON(clk_prepare_enable(data->clk));
 329         BUG_ON(clk_prepare_enable(data->pclk));
 330         BUG_ON(clk_prepare_enable(data->aclk));
 331 }
 332
 333 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 334 {
 335         clk_disable_unprepare(data->aclk);
 336         clk_disable_unprepare(data->pclk);
 337         clk_disable_unprepare(data->clk);
 338         clk_disable_unprepare(data->clk_master);
 339 }
 340
 341 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 342 {
 343         u32 ver;
 344
 345         __sysmmu_enable_clocks(data);
 346
 347         ver = readl(data->sfrbase + REG_MMU_VERSION);
 348
 349         /* controllers on some SoCs don't report proper version */
 350         if (ver == 0x80000001u)
 351                 data->version = MAKE_MMU_VER(1, 0);
 352         else
 353                 data->version = MMU_RAW_VER(ver);
 354
 355         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 356                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 357
 358         __sysmmu_disable_clocks(data);
 359 }
 360
 361 static void show_fault_information(struct sysmmu_drvdata *data,
 362                                    const struct sysmmu_fault_info *finfo,
 363                                    sysmmu_iova_t fault_addr)
 364 {
 365         sysmmu_pte_t *ent;
 366
 367         dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
 368                 finfo->name, fault_addr, &data->pgtable);
 369         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 370         dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 371         if (lv1ent_page(ent)) {
 372                 ent = page_entry(ent, fault_addr);
 373                 dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 374         }
 375 }
 376
 377 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 378 {
 379         /* SYSMMU is in blocked state when interrupt occurred. */
 380         struct sysmmu_drvdata *data = dev_id;
 381         const struct sysmmu_fault_info *finfo;
 382         unsigned int i, n, itype;
 383         sysmmu_iova_t fault_addr = -1;
 384         unsigned short reg_status, reg_clear;
 385         int ret = -ENOSYS;
 386
 387         WARN_ON(!is_sysmmu_active(data));
 388
 389         if (MMU_MAJ_VER(data->version) < 5) {
 390                 reg_status = REG_INT_STATUS;
 391                 reg_clear = REG_INT_CLEAR;
 392                 finfo = sysmmu_faults;
 393                 n = ARRAY_SIZE(sysmmu_faults);
 394         } else {
 395                 reg_status = REG_V5_INT_STATUS;
 396                 reg_clear = REG_V5_INT_CLEAR;
 397                 finfo = sysmmu_v5_faults;
 398                 n = ARRAY_SIZE(sysmmu_v5_faults);
 399         }
 400
 401         spin_lock(&data->lock);
 402
 403         clk_enable(data->clk_master);
 404
 405         itype = __ffs(readl(data->sfrbase + reg_status));
 406         for (i = 0; i < n; i++, finfo++)
 407                 if (finfo->bit == itype)
 408                         break;
 409         /* unknown/unsupported fault */
 410         BUG_ON(i == n);
 411
 412         /* print debug message */
 413         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 414         show_fault_information(data, finfo, fault_addr);
 415
 416         if (data->domain)
 417                 ret = report_iommu_fault(&data->domain->domain,
 418                                         data->master, fault_addr, finfo->type);
 419         /* fault is not recovered by fault handler */
 420         BUG_ON(ret != 0);
 421
 422         writel(1 << itype, data->sfrbase + reg_clear);
 423
 424         sysmmu_unblock(data);
 425
 426         clk_disable(data->clk_master);
 427
 428         spin_unlock(&data->lock);
 429
 430         return IRQ_HANDLED;
 431 }
 432
 433 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 434 {
 435         clk_enable(data->clk_master);
 436
 437         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 438         writel(0, data->sfrbase + REG_MMU_CFG);
 439
 440         __sysmmu_disable_clocks(data);
 441 }
 442
 443 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 444 {
 445         bool disabled;
 446         unsigned long flags;
 447
 448         spin_lock_irqsave(&data->lock, flags);
 449
 450         disabled = set_sysmmu_inactive(data);
 451
 452         if (disabled) {
 453                 data->pgtable = 0;
 454                 data->domain = NULL;
 455
 456                 __sysmmu_disable_nocount(data);
 457
 458                 dev_dbg(data->sysmmu, "Disabled\n");
 459         } else  {
 460                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 461                                         data->activations);
 462         }
 463
 464         spin_unlock_irqrestore(&data->lock, flags);
 465
 466         return disabled;
 467 }
 468
 469 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 470 {
 471         unsigned int cfg;
 472
 473         if (data->version <= MAKE_MMU_VER(3, 1))
 474                 cfg = CFG_LRU | CFG_QOS(15);
 475         else if (data->version <= MAKE_MMU_VER(3, 2))
 476                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 477         else
 478                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 479
 480         writel(cfg, data->sfrbase + REG_MMU_CFG);
 481 }
 482
 483 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 484 {
 485         __sysmmu_enable_clocks(data);
 486
 487         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 488
 489         __sysmmu_init_config(data);
 490
 491         __sysmmu_set_ptbase(data, data->pgtable);
 492
 493         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 494
 495         /*
 496          * SYSMMU driver keeps master's clock enabled only for the short
 497          * time, while accessing the registers. For performing address
 498          * translation during DMA transaction it relies on the client
 499          * driver to enable it.
 500          */
 501         clk_disable(data->clk_master);
 502 }
 503
 504 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 505                            struct exynos_iommu_domain *domain)
 506 {
 507         int ret = 0;
 508         unsigned long flags;
 509
 510         spin_lock_irqsave(&data->lock, flags);
 511         if (set_sysmmu_active(data)) {
 512                 data->pgtable = pgtable;
 513                 data->domain = domain;
 514
 515                 __sysmmu_enable_nocount(data);
 516
 517                 dev_dbg(data->sysmmu, "Enabled\n");
 518         } else {
 519                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 520
 521                 dev_dbg(data->sysmmu, "already enabled\n");
 522         }
 523
 524         if (WARN_ON(ret < 0))
 525                 set_sysmmu_inactive(data); /* decrement count */
 526
 527         spin_unlock_irqrestore(&data->lock, flags);
 528
 529         return ret;
 530 }
 531
 532 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 533                                             sysmmu_iova_t iova)
 534 {
 535         unsigned long flags;
 536
 537
 538         spin_lock_irqsave(&data->lock, flags);
 539         if (is_sysmmu_active(data) && data->version >= MAKE_MMU_VER(3, 3)) {
 540                 clk_enable(data->clk_master);
 541                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 542                 clk_disable(data->clk_master);
 543         }
 544         spin_unlock_irqrestore(&data->lock, flags);
 545
 546 }
 547
 548 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 549                                         sysmmu_iova_t iova, size_t size)
 550 {
 551         unsigned long flags;
 552
 553         spin_lock_irqsave(&data->lock, flags);
 554         if (is_sysmmu_active(data)) {
 555                 unsigned int num_inv = 1;
 556
 557                 clk_enable(data->clk_master);
 558
 559                 /*
 560                  * L2TLB invalidation required
 561                  * 4KB page: 1 invalidation
 562                  * 64KB page: 16 invalidations
 563                  * 1MB page: 64 invalidations
 564                  * because it is set-associative TLB
 565                  * with 8-way and 64 sets.
 566                  * 1MB page can be cached in one of all sets.
 567                  * 64KB page can be one of 16 consecutive sets.
 568                  */
 569                 if (MMU_MAJ_VER(data->version) == 2)
 570                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 571
 572                 if (sysmmu_block(data)) {
 573                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 574                         sysmmu_unblock(data);
 575                 }
 576                 clk_disable(data->clk_master);
 577         } else {
 578                 dev_dbg(data->master,
 579                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 580         }
 581         spin_unlock_irqrestore(&data->lock, flags);
 582 }
 583
 584 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 585 {
 586         int irq, ret;
 587         struct device *dev = &pdev->dev;
 588         struct sysmmu_drvdata *data;
 589         struct resource *res;
 590
 591         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 592         if (!data)
 593                 return -ENOMEM;
 594
 595         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 596         data->sfrbase = devm_ioremap_resource(dev, res);
 597         if (IS_ERR(data->sfrbase))
 598                 return PTR_ERR(data->sfrbase);
 599
 600         irq = platform_get_irq(pdev, 0);
 601         if (irq <= 0) {
 602                 dev_err(dev, "Unable to find IRQ resource\n");
 603                 return irq;
 604         }
 605
 606         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 607                                 dev_name(dev), data);
 608         if (ret) {
 609                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 610                 return ret;
 611         }
 612
 613         data->clk = devm_clk_get(dev, "sysmmu");
 614         if (PTR_ERR(data->clk) == -ENOENT)
 615                 data->clk = NULL;
 616         else if (IS_ERR(data->clk))
 617                 return PTR_ERR(data->clk);
 618
 619         data->aclk = devm_clk_get(dev, "aclk");
 620         if (PTR_ERR(data->aclk) == -ENOENT)
 621                 data->aclk = NULL;
 622         else if (IS_ERR(data->aclk))
 623                 return PTR_ERR(data->aclk);
 624
 625         data->pclk = devm_clk_get(dev, "pclk");
 626         if (PTR_ERR(data->pclk) == -ENOENT)
 627                 data->pclk = NULL;
 628         else if (IS_ERR(data->pclk))
 629                 return PTR_ERR(data->pclk);
 630
 631         if (!data->clk && (!data->aclk || !data->pclk)) {
 632                 dev_err(dev, "Failed to get device clock(s)!\n");
 633                 return -ENOSYS;
 634         }
 635
 636         data->clk_master = devm_clk_get(dev, "master");
 637         if (PTR_ERR(data->clk_master) == -ENOENT)
 638                 data->clk_master = NULL;
 639         else if (IS_ERR(data->clk_master))
 640                 return PTR_ERR(data->clk_master);
 641
 642         data->sysmmu = dev;
 643         spin_lock_init(&data->lock);
 644
 645         platform_set_drvdata(pdev, data);
 646
 647         __sysmmu_get_version(data);
 648         if (PG_ENT_SHIFT < 0) {
 649                 if (MMU_MAJ_VER(data->version) < 5)
 650                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 651                 else
 652                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 653         }
 654
 655         pm_runtime_enable(dev);
 656
 657         return 0;
 658 }
 659
 660 #ifdef CONFIG_PM_SLEEP
 661 static int exynos_sysmmu_suspend(struct device *dev)
 662 {
 663         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 664
 665         dev_dbg(dev, "suspend\n");
 666         if (is_sysmmu_active(data)) {
 667                 __sysmmu_disable_nocount(data);
 668                 pm_runtime_put(dev);
 669         }
 670         return 0;
 671 }
 672
 673 static int exynos_sysmmu_resume(struct device *dev)
 674 {
 675         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 676
 677         dev_dbg(dev, "resume\n");
 678         if (is_sysmmu_active(data)) {
 679                 pm_runtime_get_sync(dev);
 680                 __sysmmu_enable_nocount(data);
 681         }
 682         return 0;
 683 }
 684 #endif
 685
 686 static const struct dev_pm_ops sysmmu_pm_ops = {
 687         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 688 };
 689
 690 static const struct of_device_id sysmmu_of_match[] __initconst = {
 691         { .compatible   = "samsung,exynos-sysmmu", },
 692         { },
 693 };
 694
 695 static struct platform_driver exynos_sysmmu_driver __refdata = {
 696         .probe  = exynos_sysmmu_probe,
 697         .driver = {
 698                 .name           = "exynos-sysmmu",
 699                 .of_match_table = sysmmu_of_match,
 700                 .pm             = &sysmmu_pm_ops,
 701                 .suppress_bind_attrs = true,
 702         }
 703 };
 704
 705 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 706 {
 707         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 708                                 DMA_TO_DEVICE);
 709         *ent = val;
 710         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 711                                    DMA_TO_DEVICE);
 712 }
 713
 714 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 715 {
 716         struct exynos_iommu_domain *domain;
 717         dma_addr_t handle;
 718         int i;
 719
 720         /* Check if correct PTE offsets are initialized */
 721         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 722
 723         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 724         if (!domain)
 725                 return NULL;
 726
 727         if (type == IOMMU_DOMAIN_DMA) {
 728                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 729                         goto err_pgtable;
 730         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 731                 goto err_pgtable;
 732         }
 733
 734         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 735         if (!domain->pgtable)
 736                 goto err_dma_cookie;
 737
 738         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 739         if (!domain->lv2entcnt)
 740                 goto err_counter;
 741
 742         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 743         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 744                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 745                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 746                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 747                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 748                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 749                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 750                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 751                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 752         }
 753
 754         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 755                                 DMA_TO_DEVICE);
 756         /* For mapping page table entries we rely on dma == phys */
 757         BUG_ON(handle != virt_to_phys(domain->pgtable));
 758
 759         spin_lock_init(&domain->lock);
 760         spin_lock_init(&domain->pgtablelock);
 761         INIT_LIST_HEAD(&domain->clients);
 762
 763         domain->domain.geometry.aperture_start = 0;
 764         domain->domain.geometry.aperture_end   = ~0UL;
 765         domain->domain.geometry.force_aperture = true;
 766
 767         return &domain->domain;
 768
 769 err_counter:
 770         free_pages((unsigned long)domain->pgtable, 2);
 771 err_dma_cookie:
 772         if (type == IOMMU_DOMAIN_DMA)
 773                 iommu_put_dma_cookie(&domain->domain);
 774 err_pgtable:
 775         kfree(domain);
 776         return NULL;
 777 }
 778
 779 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 780 {
 781         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 782         struct sysmmu_drvdata *data, *next;
 783         unsigned long flags;
 784         int i;
 785
 786         WARN_ON(!list_empty(&domain->clients));
 787
 788         spin_lock_irqsave(&domain->lock, flags);
 789
 790         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 791                 if (__sysmmu_disable(data))
 792                         data->master = NULL;
 793                 list_del_init(&data->domain_node);
 794         }
 795
 796         spin_unlock_irqrestore(&domain->lock, flags);
 797
 798         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 799                 iommu_put_dma_cookie(iommu_domain);
 800
 801         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 802                          DMA_TO_DEVICE);
 803
 804         for (i = 0; i < NUM_LV1ENTRIES; i++)
 805                 if (lv1ent_page(domain->pgtable + i)) {
 806                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 807
 808                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 809                                          DMA_TO_DEVICE);
 810                         kmem_cache_free(lv2table_kmem_cache,
 811                                         phys_to_virt(base));
 812                 }
 813
 814         free_pages((unsigned long)domain->pgtable, 2);
 815         free_pages((unsigned long)domain->lv2entcnt, 1);
 816         kfree(domain);
 817 }
 818
 819 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 820                                     struct device *dev)
 821 {
 822         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 823         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 824         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 825         struct sysmmu_drvdata *data, *next;
 826         unsigned long flags;
 827         bool found = false;
 828
 829         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 830                 return;
 831
 832         spin_lock_irqsave(&domain->lock, flags);
 833         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 834                 if (data->master == dev) {
 835                         if (__sysmmu_disable(data)) {
 836                                 data->master = NULL;
 837                                 list_del_init(&data->domain_node);
 838                         }
 839                         pm_runtime_put(data->sysmmu);
 840                         found = true;
 841                 }
 842         }
 843         spin_unlock_irqrestore(&domain->lock, flags);
 844
 845         owner->domain = NULL;
 846
 847         if (found)
 848                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 849                                         __func__, &pagetable);
 850         else
 851                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 852 }
 853
 854 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 855                                    struct device *dev)
 856 {
 857         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 858         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 859         struct sysmmu_drvdata *data;
 860         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 861         unsigned long flags;
 862         int ret = -ENODEV;
 863
 864         if (!has_sysmmu(dev))
 865                 return -ENODEV;
 866
 867         if (owner->domain)
 868                 exynos_iommu_detach_device(owner->domain, dev);
 869
 870         list_for_each_entry(data, &owner->controllers, owner_node) {
 871                 pm_runtime_get_sync(data->sysmmu);
 872                 ret = __sysmmu_enable(data, pagetable, domain);
 873                 if (ret >= 0) {
 874                         data->master = dev;
 875
 876                         spin_lock_irqsave(&domain->lock, flags);
 877                         list_add_tail(&data->domain_node, &domain->clients);
 878                         spin_unlock_irqrestore(&domain->lock, flags);
 879                 }
 880         }
 881
 882         if (ret < 0) {
 883                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 884                                         __func__, &pagetable);
 885                 return ret;
 886         }
 887
 888         owner->domain = iommu_domain;
 889         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 890                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 891
 892         return ret;
 893 }
 894
 895 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 896                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 897 {
 898         if (lv1ent_section(sent)) {
 899                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 900                 return ERR_PTR(-EADDRINUSE);
 901         }
 902
 903         if (lv1ent_fault(sent)) {
 904                 sysmmu_pte_t *pent;
 905                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 906
 907                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 908                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 909                 if (!pent)
 910                         return ERR_PTR(-ENOMEM);
 911
 912                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 913                 kmemleak_ignore(pent);
 914                 *pgcounter = NUM_LV2ENTRIES;
 915                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 916
 917                 /*
 918                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 919                  * FLPD cache may cache the address of zero_l2_table. This
 920                  * function replaces the zero_l2_table with new L2 page table
 921                  * to write valid mappings.
 922                  * Accessing the valid area may cause page fault since FLPD
 923                  * cache may still cache zero_l2_table for the valid area
 924                  * instead of new L2 page table that has the mapping
 925                  * information of the valid area.
 926                  * Thus any replacement of zero_l2_table with other valid L2
 927                  * page table must involve FLPD cache invalidation for System
 928                  * MMU v3.3.
 929                  * FLPD cache invalidation is performed with TLB invalidation
 930                  * by VPN without blocking. It is safe to invalidate TLB without
 931                  * blocking because the target address of TLB invalidation is
 932                  * not currently mapped.
 933                  */
 934                 if (need_flush_flpd_cache) {
 935                         struct sysmmu_drvdata *data;
 936
 937                         spin_lock(&domain->lock);
 938                         list_for_each_entry(data, &domain->clients, domain_node)
 939                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 940                         spin_unlock(&domain->lock);
 941                 }
 942         }
 943
 944         return page_entry(sent, iova);
 945 }
 946
 947 static int lv1set_section(struct exynos_iommu_domain *domain,
 948                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 949                           phys_addr_t paddr, short *pgcnt)
 950 {
 951         if (lv1ent_section(sent)) {
 952                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 953                         iova);
 954                 return -EADDRINUSE;
 955         }
 956
 957         if (lv1ent_page(sent)) {
 958                 if (*pgcnt != NUM_LV2ENTRIES) {
 959                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 960                                 iova);
 961                         return -EADDRINUSE;
 962                 }
 963
 964                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 965                 *pgcnt = 0;
 966         }
 967
 968         update_pte(sent, mk_lv1ent_sect(paddr));
 969
 970         spin_lock(&domain->lock);
 971         if (lv1ent_page_zero(sent)) {
 972                 struct sysmmu_drvdata *data;
 973                 /*
 974                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 975                  * entry by speculative prefetch of SLPD which has no mapping.
 976                  */
 977                 list_for_each_entry(data, &domain->clients, domain_node)
 978                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 979         }
 980         spin_unlock(&domain->lock);
 981
 982         return 0;
 983 }
 984
 985 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 986                                                                 short *pgcnt)
 987 {
 988         if (size == SPAGE_SIZE) {
 989                 if (WARN_ON(!lv2ent_fault(pent)))
 990                         return -EADDRINUSE;
 991
 992                 update_pte(pent, mk_lv2ent_spage(paddr));
 993                 *pgcnt -= 1;
 994         } else { /* size == LPAGE_SIZE */
 995                 int i;
 996                 dma_addr_t pent_base = virt_to_phys(pent);
 997
 998                 dma_sync_single_for_cpu(dma_dev, pent_base,
 999                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1000                                         DMA_TO_DEVICE);
1001                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1002                         if (WARN_ON(!lv2ent_fault(pent))) {
1003                                 if (i > 0)
1004                                         memset(pent - i, 0, sizeof(*pent) * i);
1005                                 return -EADDRINUSE;
1006                         }
1007
1008                         *pent = mk_lv2ent_lpage(paddr);
1009                 }
1010                 dma_sync_single_for_device(dma_dev, pent_base,
1011                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1012                                            DMA_TO_DEVICE);
1013                 *pgcnt -= SPAGES_PER_LPAGE;
1014         }
1015
1016         return 0;
1017 }
1018
1019 /*
1020  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1021  *
1022  * System MMU v3.x has advanced logic to improve address translation
1023  * performance with caching more page table entries by a page table walk.
1024  * However, the logic has a bug that while caching faulty page table entries,
1025  * System MMU reports page fault if the cached fault entry is hit even though
1026  * the fault entry is updated to a valid entry after the entry is cached.
1027  * To prevent caching faulty page table entries which may be updated to valid
1028  * entries later, the virtual memory manager should care about the workaround
1029  * for the problem. The following describes the workaround.
1030  *
1031  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1032  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1033  *
1034  * Precisely, any start address of I/O virtual region must be aligned with
1035  * the following sizes for System MMU v3.1 and v3.2.
1036  * System MMU v3.1: 128KiB
1037  * System MMU v3.2: 256KiB
1038  *
1039  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1040  * more workarounds.
1041  * - Any two consecutive I/O virtual regions must have a hole of size larger
1042  *   than or equal to 128KiB.
1043  * - Start address of an I/O virtual region must be aligned by 128KiB.
1044  */
1045 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1046                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1047                             int prot)
1048 {
1049         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1050         sysmmu_pte_t *entry;
1051         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1052         unsigned long flags;
1053         int ret = -ENOMEM;
1054
1055         BUG_ON(domain->pgtable == NULL);
1056
1057         spin_lock_irqsave(&domain->pgtablelock, flags);
1058
1059         entry = section_entry(domain->pgtable, iova);
1060
1061         if (size == SECT_SIZE) {
1062                 ret = lv1set_section(domain, entry, iova, paddr,
1063                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1064         } else {
1065                 sysmmu_pte_t *pent;
1066
1067                 pent = alloc_lv2entry(domain, entry, iova,
1068                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1069
1070                 if (IS_ERR(pent))
1071                         ret = PTR_ERR(pent);
1072                 else
1073                         ret = lv2set_page(pent, paddr, size,
1074                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1075         }
1076
1077         if (ret)
1078                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1079                         __func__, ret, size, iova);
1080
1081         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1082
1083         return ret;
1084 }
1085
1086 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1087                                               sysmmu_iova_t iova, size_t size)
1088 {
1089         struct sysmmu_drvdata *data;
1090         unsigned long flags;
1091
1092         spin_lock_irqsave(&domain->lock, flags);
1093
1094         list_for_each_entry(data, &domain->clients, domain_node)
1095                 sysmmu_tlb_invalidate_entry(data, iova, size);
1096
1097         spin_unlock_irqrestore(&domain->lock, flags);
1098 }
1099
1100 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1101                                  unsigned long l_iova, size_t size)
1102 {
1103         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1104         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1105         sysmmu_pte_t *ent;
1106         size_t err_pgsize;
1107         unsigned long flags;
1108
1109         BUG_ON(domain->pgtable == NULL);
1110
1111         spin_lock_irqsave(&domain->pgtablelock, flags);
1112
1113         ent = section_entry(domain->pgtable, iova);
1114
1115         if (lv1ent_section(ent)) {
1116                 if (WARN_ON(size < SECT_SIZE)) {
1117                         err_pgsize = SECT_SIZE;
1118                         goto err;
1119                 }
1120
1121                 /* workaround for h/w bug in System MMU v3.3 */
1122                 update_pte(ent, ZERO_LV2LINK);
1123                 size = SECT_SIZE;
1124                 goto done;
1125         }
1126
1127         if (unlikely(lv1ent_fault(ent))) {
1128                 if (size > SECT_SIZE)
1129                         size = SECT_SIZE;
1130                 goto done;
1131         }
1132
1133         /* lv1ent_page(sent) == true here */
1134
1135         ent = page_entry(ent, iova);
1136
1137         if (unlikely(lv2ent_fault(ent))) {
1138                 size = SPAGE_SIZE;
1139                 goto done;
1140         }
1141
1142         if (lv2ent_small(ent)) {
1143                 update_pte(ent, 0);
1144                 size = SPAGE_SIZE;
1145                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1146                 goto done;
1147         }
1148
1149         /* lv1ent_large(ent) == true here */
1150         if (WARN_ON(size < LPAGE_SIZE)) {
1151                 err_pgsize = LPAGE_SIZE;
1152                 goto err;
1153         }
1154
1155         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1156                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1157                                 DMA_TO_DEVICE);
1158         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1159         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1160                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1161                                    DMA_TO_DEVICE);
1162         size = LPAGE_SIZE;
1163         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1164 done:
1165         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1166
1167         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1168
1169         return size;
1170 err:
1171         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1172
1173         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1174                 __func__, size, iova, err_pgsize);
1175
1176         return 0;
1177 }
1178
1179 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1180                                           dma_addr_t iova)
1181 {
1182         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1183         sysmmu_pte_t *entry;
1184         unsigned long flags;
1185         phys_addr_t phys = 0;
1186
1187         spin_lock_irqsave(&domain->pgtablelock, flags);
1188
1189         entry = section_entry(domain->pgtable, iova);
1190
1191         if (lv1ent_section(entry)) {
1192                 phys = section_phys(entry) + section_offs(iova);
1193         } else if (lv1ent_page(entry)) {
1194                 entry = page_entry(entry, iova);
1195
1196                 if (lv2ent_large(entry))
1197                         phys = lpage_phys(entry) + lpage_offs(iova);
1198                 else if (lv2ent_small(entry))
1199                         phys = spage_phys(entry) + spage_offs(iova);
1200         }
1201
1202         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1203
1204         return phys;
1205 }
1206
1207 static struct iommu_group *get_device_iommu_group(struct device *dev)
1208 {
1209         struct iommu_group *group;
1210
1211         group = iommu_group_get(dev);
1212         if (!group)
1213                 group = iommu_group_alloc();
1214
1215         return group;
1216 }
1217
1218 static int exynos_iommu_add_device(struct device *dev)
1219 {
1220         struct iommu_group *group;
1221
1222         if (!has_sysmmu(dev))
1223                 return -ENODEV;
1224
1225         group = iommu_group_get_for_dev(dev);
1226
1227         if (IS_ERR(group))
1228                 return PTR_ERR(group);
1229
1230         iommu_group_put(group);
1231
1232         return 0;
1233 }
1234
1235 static void exynos_iommu_remove_device(struct device *dev)
1236 {
1237         if (!has_sysmmu(dev))
1238                 return;
1239
1240         iommu_group_remove_device(dev);
1241 }
1242
1243 static int exynos_iommu_of_xlate(struct device *dev,
1244                                  struct of_phandle_args *spec)
1245 {
1246         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1247         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1248         struct sysmmu_drvdata *data;
1249
1250         if (!sysmmu)
1251                 return -ENODEV;
1252
1253         data = platform_get_drvdata(sysmmu);
1254         if (!data)
1255                 return -ENODEV;
1256
1257         if (!owner) {
1258                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1259                 if (!owner)
1260                         return -ENOMEM;
1261
1262                 INIT_LIST_HEAD(&owner->controllers);
1263                 dev->archdata.iommu = owner;
1264         }
1265
1266         list_add_tail(&data->owner_node, &owner->controllers);
1267         return 0;
1268 }
1269
1270 static struct iommu_ops exynos_iommu_ops = {
1271         .domain_alloc = exynos_iommu_domain_alloc,
1272         .domain_free = exynos_iommu_domain_free,
1273         .attach_dev = exynos_iommu_attach_device,
1274         .detach_dev = exynos_iommu_detach_device,
1275         .map = exynos_iommu_map,
1276         .unmap = exynos_iommu_unmap,
1277         .map_sg = default_iommu_map_sg,
1278         .iova_to_phys = exynos_iommu_iova_to_phys,
1279         .device_group = get_device_iommu_group,
1280         .add_device = exynos_iommu_add_device,
1281         .remove_device = exynos_iommu_remove_device,
1282         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1283         .of_xlate = exynos_iommu_of_xlate,
1284 };
1285
1286 static bool init_done;
1287
1288 static int __init exynos_iommu_init(void)
1289 {
1290         int ret;
1291
1292         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1293                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1294         if (!lv2table_kmem_cache) {
1295                 pr_err("%s: Failed to create kmem cache\n", __func__);
1296                 return -ENOMEM;
1297         }
1298
1299         ret = platform_driver_register(&exynos_sysmmu_driver);
1300         if (ret) {
1301                 pr_err("%s: Failed to register driver\n", __func__);
1302                 goto err_reg_driver;
1303         }
1304
1305         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1306         if (zero_lv2_table == NULL) {
1307                 pr_err("%s: Failed to allocate zero level2 page table\n",
1308                         __func__);
1309                 ret = -ENOMEM;
1310                 goto err_zero_lv2;
1311         }
1312
1313         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1314         if (ret) {
1315                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1316                                                                 __func__);
1317                 goto err_set_iommu;
1318         }
1319
1320         init_done = true;
1321
1322         return 0;
1323 err_set_iommu:
1324         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1325 err_zero_lv2:
1326         platform_driver_unregister(&exynos_sysmmu_driver);
1327 err_reg_driver:
1328         kmem_cache_destroy(lv2table_kmem_cache);
1329         return ret;
1330 }
1331
1332 static int __init exynos_iommu_of_setup(struct device_node *np)
1333 {
1334         struct platform_device *pdev;
1335
1336         if (!init_done)
1337                 exynos_iommu_init();
1338
1339         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1340         if (IS_ERR(pdev))
1341                 return PTR_ERR(pdev);
1342
1343         /*
1344          * use the first registered sysmmu device for performing
1345          * dma mapping operations on iommu page tables (cpu cache flush)
1346          */
1347         if (!dma_dev)
1348                 dma_dev = &pdev->dev;
1349
1350         of_iommu_set_ops(np, &exynos_iommu_ops);
1351         return 0;
1352 }
1353
1354 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1355                  exynos_iommu_of_setup);