2 * CPU-agnostic ARM page table allocator.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2014 ARM Limited
18 * Author: Will Deacon <will.deacon@arm.com>
21 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
23 #include <linux/iommu.h>
24 #include <linux/kernel.h>
25 #include <linux/sizes.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
30 #include <asm/barrier.h>
32 #include "io-pgtable.h"
34 #define ARM_LPAE_MAX_ADDR_BITS 48
35 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
36 #define ARM_LPAE_MAX_LEVELS 4
38 /* Struct accessors */
39 #define io_pgtable_to_data(x) \
40 container_of((x), struct arm_lpae_io_pgtable, iop)
42 #define io_pgtable_ops_to_data(x) \
43 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
46 * For consistency with the architecture, we always consider
47 * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
49 #define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
52 * Calculate the right shift amount to get to the portion describing level l
53 * in a virtual address mapped by the pagetable in d.
55 #define ARM_LPAE_LVL_SHIFT(l,d) \
56 ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
57 * (d)->bits_per_level) + (d)->pg_shift)
59 #define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift)
61 #define ARM_LPAE_PAGES_PER_PGD(d) \
62 DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d))
65 * Calculate the index at level l used to map virtual address a using the
68 #define ARM_LPAE_PGD_IDX(l,d) \
69 ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
71 #define ARM_LPAE_LVL_IDX(a,l,d) \
72 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
73 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
75 /* Calculate the block/page mapping size at level l for pagetable in d. */
76 #define ARM_LPAE_BLOCK_SIZE(l,d) \
77 (1 << (ilog2(sizeof(arm_lpae_iopte)) + \
78 ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
81 #define ARM_LPAE_PTE_TYPE_SHIFT 0
82 #define ARM_LPAE_PTE_TYPE_MASK 0x3
84 #define ARM_LPAE_PTE_TYPE_BLOCK 1
85 #define ARM_LPAE_PTE_TYPE_TABLE 3
86 #define ARM_LPAE_PTE_TYPE_PAGE 3
88 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
89 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
90 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
91 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
92 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
93 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
94 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
95 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
97 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
98 /* Ignore the contiguous bit for block splitting */
99 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
100 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
101 ARM_LPAE_PTE_ATTR_HI_MASK)
104 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
105 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
106 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
107 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
110 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
111 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
112 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
113 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
114 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
115 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
118 #define ARM_32_LPAE_TCR_EAE (1 << 31)
119 #define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
121 #define ARM_LPAE_TCR_EPD1 (1 << 23)
123 #define ARM_LPAE_TCR_TG0_4K (0 << 14)
124 #define ARM_LPAE_TCR_TG0_64K (1 << 14)
125 #define ARM_LPAE_TCR_TG0_16K (2 << 14)
127 #define ARM_LPAE_TCR_SH0_SHIFT 12
128 #define ARM_LPAE_TCR_SH0_MASK 0x3
129 #define ARM_LPAE_TCR_SH_NS 0
130 #define ARM_LPAE_TCR_SH_OS 2
131 #define ARM_LPAE_TCR_SH_IS 3
133 #define ARM_LPAE_TCR_ORGN0_SHIFT 10
134 #define ARM_LPAE_TCR_IRGN0_SHIFT 8
135 #define ARM_LPAE_TCR_RGN_MASK 0x3
136 #define ARM_LPAE_TCR_RGN_NC 0
137 #define ARM_LPAE_TCR_RGN_WBWA 1
138 #define ARM_LPAE_TCR_RGN_WT 2
139 #define ARM_LPAE_TCR_RGN_WB 3
141 #define ARM_LPAE_TCR_SL0_SHIFT 6
142 #define ARM_LPAE_TCR_SL0_MASK 0x3
144 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
145 #define ARM_LPAE_TCR_SZ_MASK 0xf
147 #define ARM_LPAE_TCR_PS_SHIFT 16
148 #define ARM_LPAE_TCR_PS_MASK 0x7
150 #define ARM_LPAE_TCR_IPS_SHIFT 32
151 #define ARM_LPAE_TCR_IPS_MASK 0x7
153 #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
154 #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
155 #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
156 #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
157 #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
158 #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
160 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
161 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
162 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
163 #define ARM_LPAE_MAIR_ATTR_NC 0x44
164 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
165 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
166 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
167 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
169 /* IOPTE accessors */
170 #define iopte_deref(pte,d) \
171 (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \
172 & ~(ARM_LPAE_GRANULE(d) - 1ULL)))
174 #define iopte_type(pte,l) \
175 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
177 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
179 #define iopte_leaf(pte,l) \
180 (l == (ARM_LPAE_MAX_LEVELS - 1) ? \
181 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
182 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
184 #define iopte_to_pfn(pte,d) \
185 (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift)
187 #define pfn_to_iopte(pfn,d) \
188 (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1))
190 struct arm_lpae_io_pgtable {
191 struct io_pgtable iop;
195 unsigned long pg_shift;
196 unsigned long bits_per_level;
201 typedef u64 arm_lpae_iopte;
203 static bool selftest_running = false;
205 static dma_addr_t __arm_lpae_dma_addr(void *pages)
207 return (dma_addr_t)virt_to_phys(pages);
210 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
211 struct io_pgtable_cfg *cfg)
213 struct device *dev = cfg->iommu_dev;
215 void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO);
220 if (!selftest_running) {
221 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
222 if (dma_mapping_error(dev, dma))
225 * We depend on the IOMMU being able to work with any physical
226 * address directly, so if the DMA layer suggests otherwise by
227 * translating or truncating them, that bodes very badly...
229 if (dma != virt_to_phys(pages))
236 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
237 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
239 free_pages_exact(pages, size);
243 static void __arm_lpae_free_pages(void *pages, size_t size,
244 struct io_pgtable_cfg *cfg)
246 if (!selftest_running)
247 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
248 size, DMA_TO_DEVICE);
249 free_pages_exact(pages, size);
252 static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
253 struct io_pgtable_cfg *cfg)
257 if (!selftest_running)
258 dma_sync_single_for_device(cfg->iommu_dev,
259 __arm_lpae_dma_addr(ptep),
260 sizeof(pte), DMA_TO_DEVICE);
263 static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
264 unsigned long iova, size_t size, int lvl,
265 arm_lpae_iopte *ptep);
267 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
268 unsigned long iova, phys_addr_t paddr,
269 arm_lpae_iopte prot, int lvl,
270 arm_lpae_iopte *ptep)
272 arm_lpae_iopte pte = prot;
273 struct io_pgtable_cfg *cfg = &data->iop.cfg;
275 if (iopte_leaf(*ptep, lvl)) {
276 /* We require an unmap first */
277 WARN_ON(!selftest_running);
279 } else if (iopte_type(*ptep, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
281 * We need to unmap and free the old table before
282 * overwriting it with a block entry.
284 arm_lpae_iopte *tblp;
285 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
287 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
288 if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz))
292 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
293 pte |= ARM_LPAE_PTE_NS;
295 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
296 pte |= ARM_LPAE_PTE_TYPE_PAGE;
298 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
300 pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
301 pte |= pfn_to_iopte(paddr >> data->pg_shift, data);
303 __arm_lpae_set_pte(ptep, pte, cfg);
307 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
308 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
309 int lvl, arm_lpae_iopte *ptep)
311 arm_lpae_iopte *cptep, pte;
312 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
313 struct io_pgtable_cfg *cfg = &data->iop.cfg;
315 /* Find our entry at the current level */
316 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
318 /* If we can install a leaf entry at this level, then do so */
319 if (size == block_size && (size & cfg->pgsize_bitmap))
320 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
322 /* We can't allocate tables at the final level */
323 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
326 /* Grab a pointer to the next level */
329 cptep = __arm_lpae_alloc_pages(ARM_LPAE_GRANULE(data),
334 pte = __pa(cptep) | ARM_LPAE_PTE_TYPE_TABLE;
335 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
336 pte |= ARM_LPAE_PTE_NSTABLE;
337 __arm_lpae_set_pte(ptep, pte, cfg);
339 cptep = iopte_deref(pte, data);
343 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
346 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
351 if (data->iop.fmt == ARM_64_LPAE_S1 ||
352 data->iop.fmt == ARM_32_LPAE_S1) {
353 pte = ARM_LPAE_PTE_AP_UNPRIV | ARM_LPAE_PTE_nG;
355 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
356 pte |= ARM_LPAE_PTE_AP_RDONLY;
358 if (prot & IOMMU_CACHE)
359 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
360 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
362 pte = ARM_LPAE_PTE_HAP_FAULT;
363 if (prot & IOMMU_READ)
364 pte |= ARM_LPAE_PTE_HAP_READ;
365 if (prot & IOMMU_WRITE)
366 pte |= ARM_LPAE_PTE_HAP_WRITE;
367 if (prot & IOMMU_CACHE)
368 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
370 pte |= ARM_LPAE_PTE_MEMATTR_NC;
373 if (prot & IOMMU_NOEXEC)
374 pte |= ARM_LPAE_PTE_XN;
379 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
380 phys_addr_t paddr, size_t size, int iommu_prot)
382 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
383 arm_lpae_iopte *ptep = data->pgd;
384 int ret, lvl = ARM_LPAE_START_LVL(data);
387 /* If no access, then nothing to do */
388 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
391 prot = arm_lpae_prot_to_pte(data, iommu_prot);
392 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
394 * Synchronise all PTE updates for the new mapping before there's
395 * a chance for anything to kick off a table walk for the new iova.
402 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
403 arm_lpae_iopte *ptep)
405 arm_lpae_iopte *start, *end;
406 unsigned long table_size;
408 if (lvl == ARM_LPAE_START_LVL(data))
409 table_size = data->pgd_size;
411 table_size = ARM_LPAE_GRANULE(data);
415 /* Only leaf entries at the last level */
416 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
419 end = (void *)ptep + table_size;
421 while (ptep != end) {
422 arm_lpae_iopte pte = *ptep++;
424 if (!pte || iopte_leaf(pte, lvl))
427 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
430 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
433 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
435 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
437 __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
441 static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
442 unsigned long iova, size_t size,
443 arm_lpae_iopte prot, int lvl,
444 arm_lpae_iopte *ptep, size_t blk_size)
446 unsigned long blk_start, blk_end;
447 phys_addr_t blk_paddr;
448 arm_lpae_iopte table = 0;
449 struct io_pgtable_cfg *cfg = &data->iop.cfg;
451 blk_start = iova & ~(blk_size - 1);
452 blk_end = blk_start + blk_size;
453 blk_paddr = iopte_to_pfn(*ptep, data) << data->pg_shift;
455 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) {
456 arm_lpae_iopte *tablep;
459 if (blk_start == iova)
462 /* __arm_lpae_map expects a pointer to the start of the table */
463 tablep = &table - ARM_LPAE_LVL_IDX(blk_start, lvl, data);
464 if (__arm_lpae_map(data, blk_start, blk_paddr, size, prot, lvl,
467 /* Free the table we allocated */
468 tablep = iopte_deref(table, data);
469 __arm_lpae_free_pgtable(data, lvl + 1, tablep);
471 return 0; /* Bytes unmapped */
475 __arm_lpae_set_pte(ptep, table, cfg);
476 iova &= ~(blk_size - 1);
477 cfg->tlb->tlb_add_flush(iova, blk_size, blk_size, true, data->iop.cookie);
481 static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
482 unsigned long iova, size_t size, int lvl,
483 arm_lpae_iopte *ptep)
486 const struct iommu_gather_ops *tlb = data->iop.cfg.tlb;
487 void *cookie = data->iop.cookie;
488 size_t blk_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
490 /* Something went horribly wrong and we ran out of page table */
491 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
494 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
499 /* If the size matches this level, we're in the right place */
500 if (size == blk_size) {
501 __arm_lpae_set_pte(ptep, 0, &data->iop.cfg);
503 if (!iopte_leaf(pte, lvl)) {
504 /* Also flush any partial walks */
505 tlb->tlb_add_flush(iova, size, ARM_LPAE_GRANULE(data),
507 tlb->tlb_sync(cookie);
508 ptep = iopte_deref(pte, data);
509 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
511 tlb->tlb_add_flush(iova, size, size, true, cookie);
515 } else if (iopte_leaf(pte, lvl)) {
517 * Insert a table at the next level to map the old region,
518 * minus the part we want to unmap
520 return arm_lpae_split_blk_unmap(data, iova, size,
521 iopte_prot(pte), lvl, ptep,
525 /* Keep on walkin' */
526 ptep = iopte_deref(pte, data);
527 return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
530 static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
534 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
535 struct io_pgtable *iop = &data->iop;
536 arm_lpae_iopte *ptep = data->pgd;
537 int lvl = ARM_LPAE_START_LVL(data);
539 unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep);
541 iop->cfg.tlb->tlb_sync(iop->cookie);
546 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
549 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
550 arm_lpae_iopte pte, *ptep = data->pgd;
551 int lvl = ARM_LPAE_START_LVL(data);
554 /* Valid IOPTE pointer? */
558 /* Grab the IOPTE we're interested in */
559 pte = *(ptep + ARM_LPAE_LVL_IDX(iova, lvl, data));
566 if (iopte_leaf(pte,lvl))
567 goto found_translation;
569 /* Take it to the next level */
570 ptep = iopte_deref(pte, data);
571 } while (++lvl < ARM_LPAE_MAX_LEVELS);
573 /* Ran out of page tables to walk */
577 iova &= (ARM_LPAE_GRANULE(data) - 1);
578 return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova;
581 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
583 unsigned long granule;
586 * We need to restrict the supported page sizes to match the
587 * translation regime for a particular granule. Aim to match
588 * the CPU page size if possible, otherwise prefer smaller sizes.
589 * While we're at it, restrict the block sizes to match the
592 if (cfg->pgsize_bitmap & PAGE_SIZE)
594 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
595 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
596 else if (cfg->pgsize_bitmap & PAGE_MASK)
597 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
603 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
606 cfg->pgsize_bitmap &= (SZ_16K | SZ_32M);
609 cfg->pgsize_bitmap &= (SZ_64K | SZ_512M);
612 cfg->pgsize_bitmap = 0;
616 static struct arm_lpae_io_pgtable *
617 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
619 unsigned long va_bits, pgd_bits;
620 struct arm_lpae_io_pgtable *data;
622 arm_lpae_restrict_pgsizes(cfg);
624 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
627 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
630 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
633 if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) {
634 dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n");
638 data = kmalloc(sizeof(*data), GFP_KERNEL);
642 data->pg_shift = __ffs(cfg->pgsize_bitmap);
643 data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
645 va_bits = cfg->ias - data->pg_shift;
646 data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
648 /* Calculate the actual size of our pgd (without concatenation) */
649 pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
650 data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
652 data->iop.ops = (struct io_pgtable_ops) {
654 .unmap = arm_lpae_unmap,
655 .iova_to_phys = arm_lpae_iova_to_phys,
661 static struct io_pgtable *
662 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
665 struct arm_lpae_io_pgtable *data = arm_lpae_alloc_pgtable(cfg);
671 reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
672 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
673 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
675 switch (ARM_LPAE_GRANULE(data)) {
677 reg |= ARM_LPAE_TCR_TG0_4K;
680 reg |= ARM_LPAE_TCR_TG0_16K;
683 reg |= ARM_LPAE_TCR_TG0_64K;
689 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
692 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
695 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
698 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
701 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
704 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
710 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
712 /* Disable speculative walks through TTBR1 */
713 reg |= ARM_LPAE_TCR_EPD1;
714 cfg->arm_lpae_s1_cfg.tcr = reg;
717 reg = (ARM_LPAE_MAIR_ATTR_NC
718 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
719 (ARM_LPAE_MAIR_ATTR_WBRWA
720 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
721 (ARM_LPAE_MAIR_ATTR_DEVICE
722 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
724 cfg->arm_lpae_s1_cfg.mair[0] = reg;
725 cfg->arm_lpae_s1_cfg.mair[1] = 0;
727 /* Looking good; allocate a pgd */
728 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
732 /* Ensure the empty pgd is visible before any actual TTBR write */
736 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
737 cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
745 static struct io_pgtable *
746 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
749 struct arm_lpae_io_pgtable *data = arm_lpae_alloc_pgtable(cfg);
755 * Concatenate PGDs at level 1 if possible in order to reduce
756 * the depth of the stage-2 walk.
758 if (data->levels == ARM_LPAE_MAX_LEVELS) {
759 unsigned long pgd_pages;
761 pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
762 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
763 data->pgd_size = pgd_pages << data->pg_shift;
769 reg = ARM_64_LPAE_S2_TCR_RES1 |
770 (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
771 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
772 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
774 sl = ARM_LPAE_START_LVL(data);
776 switch (ARM_LPAE_GRANULE(data)) {
778 reg |= ARM_LPAE_TCR_TG0_4K;
779 sl++; /* SL0 format is different for 4K granule size */
782 reg |= ARM_LPAE_TCR_TG0_16K;
785 reg |= ARM_LPAE_TCR_TG0_64K;
791 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
794 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
797 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
800 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
803 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
806 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
812 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
813 reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
814 cfg->arm_lpae_s2_cfg.vtcr = reg;
816 /* Allocate pgd pages */
817 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
821 /* Ensure the empty pgd is visible before any actual TTBR write */
825 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
833 static struct io_pgtable *
834 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
836 struct io_pgtable *iop;
838 if (cfg->ias > 32 || cfg->oas > 40)
841 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
842 iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
844 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
845 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
851 static struct io_pgtable *
852 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
854 struct io_pgtable *iop;
856 if (cfg->ias > 40 || cfg->oas > 40)
859 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
860 iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
862 cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
867 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
868 .alloc = arm_64_lpae_alloc_pgtable_s1,
869 .free = arm_lpae_free_pgtable,
872 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
873 .alloc = arm_64_lpae_alloc_pgtable_s2,
874 .free = arm_lpae_free_pgtable,
877 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
878 .alloc = arm_32_lpae_alloc_pgtable_s1,
879 .free = arm_lpae_free_pgtable,
882 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
883 .alloc = arm_32_lpae_alloc_pgtable_s2,
884 .free = arm_lpae_free_pgtable,
887 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
889 static struct io_pgtable_cfg *cfg_cookie;
891 static void dummy_tlb_flush_all(void *cookie)
893 WARN_ON(cookie != cfg_cookie);
896 static void dummy_tlb_add_flush(unsigned long iova, size_t size,
897 size_t granule, bool leaf, void *cookie)
899 WARN_ON(cookie != cfg_cookie);
900 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
903 static void dummy_tlb_sync(void *cookie)
905 WARN_ON(cookie != cfg_cookie);
908 static struct iommu_gather_ops dummy_tlb_ops __initdata = {
909 .tlb_flush_all = dummy_tlb_flush_all,
910 .tlb_add_flush = dummy_tlb_add_flush,
911 .tlb_sync = dummy_tlb_sync,
914 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
916 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
917 struct io_pgtable_cfg *cfg = &data->iop.cfg;
919 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
920 cfg->pgsize_bitmap, cfg->ias);
921 pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
922 data->levels, data->pgd_size, data->pg_shift,
923 data->bits_per_level, data->pgd);
926 #define __FAIL(ops, i) ({ \
927 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
928 arm_lpae_dump_ops(ops); \
929 selftest_running = false; \
933 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
935 static const enum io_pgtable_fmt fmts[] = {
943 struct io_pgtable_ops *ops;
945 selftest_running = true;
947 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
949 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
951 pr_err("selftest: failed to allocate io pgtable ops\n");
956 * Initial sanity checks.
957 * Empty page tables shouldn't provide any translations.
959 if (ops->iova_to_phys(ops, 42))
960 return __FAIL(ops, i);
962 if (ops->iova_to_phys(ops, SZ_1G + 42))
963 return __FAIL(ops, i);
965 if (ops->iova_to_phys(ops, SZ_2G + 42))
966 return __FAIL(ops, i);
969 * Distinct mappings of different granule sizes.
972 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
973 while (j != BITS_PER_LONG) {
976 if (ops->map(ops, iova, iova, size, IOMMU_READ |
980 return __FAIL(ops, i);
982 /* Overlapping mappings */
983 if (!ops->map(ops, iova, iova + size, size,
984 IOMMU_READ | IOMMU_NOEXEC))
985 return __FAIL(ops, i);
987 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
988 return __FAIL(ops, i);
992 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
996 size = 1UL << __ffs(cfg->pgsize_bitmap);
997 if (ops->unmap(ops, SZ_1G + size, size) != size)
998 return __FAIL(ops, i);
1000 /* Remap of partial unmap */
1001 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
1002 return __FAIL(ops, i);
1004 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1005 return __FAIL(ops, i);
1009 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
1010 while (j != BITS_PER_LONG) {
1013 if (ops->unmap(ops, iova, size) != size)
1014 return __FAIL(ops, i);
1016 if (ops->iova_to_phys(ops, iova + 42))
1017 return __FAIL(ops, i);
1019 /* Remap full block */
1020 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
1021 return __FAIL(ops, i);
1023 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1024 return __FAIL(ops, i);
1028 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
1031 free_io_pgtable_ops(ops);
1034 selftest_running = false;
1038 static int __init arm_lpae_do_selftests(void)
1040 static const unsigned long pgsize[] = {
1041 SZ_4K | SZ_2M | SZ_1G,
1046 static const unsigned int ias[] = {
1047 32, 36, 40, 42, 44, 48,
1050 int i, j, pass = 0, fail = 0;
1051 struct io_pgtable_cfg cfg = {
1052 .tlb = &dummy_tlb_ops,
1056 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1057 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1058 cfg.pgsize_bitmap = pgsize[i];
1060 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1062 if (arm_lpae_run_tests(&cfg))
1069 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1070 return fail ? -EFAULT : 0;
1072 subsys_initcall(arm_lpae_do_selftests);