2 * omap iommu: tlb and pagetable primitives
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/iommu.h>
22 #include <linux/mutex.h>
23 #include <linux/spinlock.h>
25 #include <asm/cacheflush.h>
27 #include <plat/iommu.h>
29 #include <plat/iopgtable.h>
31 #define for_each_iotlb_cr(obj, n, __i, cr) \
33 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
37 * struct omap_iommu_domain - omap iommu domain
38 * @pgtable: the page table
39 * @iommu_dev: an omap iommu device attached to this domain. only a single
40 * iommu device can be attached for now.
41 * @lock: domain lock, should be taken when attaching/detaching
43 struct omap_iommu_domain {
45 struct omap_iommu *iommu_dev;
49 /* accommodate the difference between omap1 and omap2/3 */
50 static const struct iommu_functions *arch_iommu;
52 static struct platform_driver omap_iommu_driver;
53 static struct kmem_cache *iopte_cachep;
56 * omap_install_iommu_arch - Install archtecure specific iommu functions
57 * @ops: a pointer to architecture specific iommu functions
59 * There are several kind of iommu algorithm(tlb, pagetable) among
60 * omap series. This interface installs such an iommu algorighm.
62 int omap_install_iommu_arch(const struct iommu_functions *ops)
70 EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
73 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
74 * @ops: a pointer to architecture specific iommu functions
76 * This interface uninstalls the iommu algorighm installed previously.
78 void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
80 if (arch_iommu != ops)
81 pr_err("%s: not your arch\n", __func__);
85 EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
88 * omap_iommu_save_ctx - Save registers for pm off-mode support
91 void omap_iommu_save_ctx(struct omap_iommu *obj)
93 arch_iommu->save_ctx(obj);
95 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
98 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
101 void omap_iommu_restore_ctx(struct omap_iommu *obj)
103 arch_iommu->restore_ctx(obj);
105 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
108 * omap_iommu_arch_version - Return running iommu arch version
110 u32 omap_iommu_arch_version(void)
112 return arch_iommu->version;
114 EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
116 static int iommu_enable(struct omap_iommu *obj)
126 clk_enable(obj->clk);
128 err = arch_iommu->enable(obj);
130 clk_disable(obj->clk);
134 static void iommu_disable(struct omap_iommu *obj)
139 clk_enable(obj->clk);
141 arch_iommu->disable(obj);
143 clk_disable(obj->clk);
149 void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
153 arch_iommu->cr_to_e(cr, e);
155 EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
157 static inline int iotlb_cr_valid(struct cr_regs *cr)
162 return arch_iommu->cr_valid(cr);
165 static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
166 struct iotlb_entry *e)
171 return arch_iommu->alloc_cr(obj, e);
174 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
176 return arch_iommu->cr_to_virt(cr);
179 static u32 get_iopte_attr(struct iotlb_entry *e)
181 return arch_iommu->get_pte_attr(e);
184 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
186 return arch_iommu->fault_isr(obj, da);
189 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
193 val = iommu_read_reg(obj, MMU_LOCK);
195 l->base = MMU_LOCK_BASE(val);
196 l->vict = MMU_LOCK_VICT(val);
200 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
204 val = (l->base << MMU_LOCK_BASE_SHIFT);
205 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
207 iommu_write_reg(obj, val, MMU_LOCK);
210 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
212 arch_iommu->tlb_read_cr(obj, cr);
215 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
217 arch_iommu->tlb_load_cr(obj, cr);
219 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
220 iommu_write_reg(obj, 1, MMU_LD_TLB);
224 * iotlb_dump_cr - Dump an iommu tlb entry into buf
226 * @cr: contents of cam and ram register
227 * @buf: output buffer
229 static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
234 return arch_iommu->dump_cr(obj, cr, buf);
237 /* only used in iotlb iteration for-loop */
238 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
243 iotlb_lock_get(obj, &l);
245 iotlb_lock_set(obj, &l);
246 iotlb_read_cr(obj, &cr);
252 * load_iotlb_entry - Set an iommu tlb entry
254 * @e: an iommu tlb entry info
256 #ifdef PREFETCH_IOTLB
257 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
263 if (!obj || !obj->nr_tlb_entries || !e)
266 clk_enable(obj->clk);
268 iotlb_lock_get(obj, &l);
269 if (l.base == obj->nr_tlb_entries) {
270 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
278 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
279 if (!iotlb_cr_valid(&tmp))
282 if (i == obj->nr_tlb_entries) {
283 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
288 iotlb_lock_get(obj, &l);
291 iotlb_lock_set(obj, &l);
294 cr = iotlb_alloc_cr(obj, e);
296 clk_disable(obj->clk);
300 iotlb_load_cr(obj, cr);
305 /* increment victim for next tlb load */
306 if (++l.vict == obj->nr_tlb_entries)
308 iotlb_lock_set(obj, &l);
310 clk_disable(obj->clk);
314 #else /* !PREFETCH_IOTLB */
316 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
321 #endif /* !PREFETCH_IOTLB */
323 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
325 return load_iotlb_entry(obj, e);
329 * flush_iotlb_page - Clear an iommu tlb entry
331 * @da: iommu device virtual address
333 * Clear an iommu tlb entry which includes 'da' address.
335 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
340 clk_enable(obj->clk);
342 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
346 if (!iotlb_cr_valid(&cr))
349 start = iotlb_cr_to_virt(&cr);
350 bytes = iopgsz_to_bytes(cr.cam & 3);
352 if ((start <= da) && (da < start + bytes)) {
353 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
354 __func__, start, da, bytes);
355 iotlb_load_cr(obj, &cr);
356 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
359 clk_disable(obj->clk);
361 if (i == obj->nr_tlb_entries)
362 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
366 * flush_iotlb_all - Clear all iommu tlb entries
369 static void flush_iotlb_all(struct omap_iommu *obj)
373 clk_enable(obj->clk);
377 iotlb_lock_set(obj, &l);
379 iommu_write_reg(obj, 1, MMU_GFLUSH);
381 clk_disable(obj->clk);
384 #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
386 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
391 clk_enable(obj->clk);
393 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
395 clk_disable(obj->clk);
399 EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
402 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
405 struct iotlb_lock saved;
407 struct cr_regs *p = crs;
409 clk_enable(obj->clk);
410 iotlb_lock_get(obj, &saved);
412 for_each_iotlb_cr(obj, num, i, tmp) {
413 if (!iotlb_cr_valid(&tmp))
418 iotlb_lock_set(obj, &saved);
419 clk_disable(obj->clk);
425 * omap_dump_tlb_entries - dump cr arrays to given buffer
427 * @buf: output buffer
429 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
435 num = bytes / sizeof(*cr);
436 num = min(obj->nr_tlb_entries, num);
438 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
442 num = __dump_tlb_entries(obj, cr, num);
443 for (i = 0; i < num; i++)
444 p += iotlb_dump_cr(obj, cr + i, p);
449 EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
451 int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
453 return driver_for_each_device(&omap_iommu_driver.driver,
456 EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
458 #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
461 * H/W pagetable operations
463 static void flush_iopgd_range(u32 *first, u32 *last)
465 /* FIXME: L2 cache should be taken care of if it exists */
467 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
469 first += L1_CACHE_BYTES / sizeof(*first);
470 } while (first <= last);
473 static void flush_iopte_range(u32 *first, u32 *last)
475 /* FIXME: L2 cache should be taken care of if it exists */
477 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
479 first += L1_CACHE_BYTES / sizeof(*first);
480 } while (first <= last);
483 static void iopte_free(u32 *iopte)
485 /* Note: freed iopte's must be clean ready for re-use */
486 kmem_cache_free(iopte_cachep, iopte);
489 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
493 /* a table has already existed */
498 * do the allocation outside the page table lock
500 spin_unlock(&obj->page_table_lock);
501 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
502 spin_lock(&obj->page_table_lock);
506 return ERR_PTR(-ENOMEM);
508 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
509 flush_iopgd_range(iopgd, iopgd);
511 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
513 /* We raced, free the reduniovant table */
518 iopte = iopte_offset(iopgd, da);
521 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
522 __func__, da, iopgd, *iopgd, iopte, *iopte);
527 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
529 u32 *iopgd = iopgd_offset(obj, da);
531 if ((da | pa) & ~IOSECTION_MASK) {
532 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
533 __func__, da, pa, IOSECTION_SIZE);
537 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
538 flush_iopgd_range(iopgd, iopgd);
542 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
544 u32 *iopgd = iopgd_offset(obj, da);
547 if ((da | pa) & ~IOSUPER_MASK) {
548 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
549 __func__, da, pa, IOSUPER_SIZE);
553 for (i = 0; i < 16; i++)
554 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
555 flush_iopgd_range(iopgd, iopgd + 15);
559 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
561 u32 *iopgd = iopgd_offset(obj, da);
562 u32 *iopte = iopte_alloc(obj, iopgd, da);
565 return PTR_ERR(iopte);
567 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
568 flush_iopte_range(iopte, iopte);
570 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
571 __func__, da, pa, iopte, *iopte);
576 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
578 u32 *iopgd = iopgd_offset(obj, da);
579 u32 *iopte = iopte_alloc(obj, iopgd, da);
582 if ((da | pa) & ~IOLARGE_MASK) {
583 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
584 __func__, da, pa, IOLARGE_SIZE);
589 return PTR_ERR(iopte);
591 for (i = 0; i < 16; i++)
592 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
593 flush_iopte_range(iopte, iopte + 15);
598 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
600 int (*fn)(struct omap_iommu *, u32, u32, u32);
608 case MMU_CAM_PGSZ_16M:
609 fn = iopgd_alloc_super;
611 case MMU_CAM_PGSZ_1M:
612 fn = iopgd_alloc_section;
614 case MMU_CAM_PGSZ_64K:
615 fn = iopte_alloc_large;
617 case MMU_CAM_PGSZ_4K:
618 fn = iopte_alloc_page;
626 prot = get_iopte_attr(e);
628 spin_lock(&obj->page_table_lock);
629 err = fn(obj, e->da, e->pa, prot);
630 spin_unlock(&obj->page_table_lock);
636 * omap_iopgtable_store_entry - Make an iommu pte entry
638 * @e: an iommu tlb entry info
640 int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
644 flush_iotlb_page(obj, e->da);
645 err = iopgtable_store_entry_core(obj, e);
647 prefetch_iotlb_entry(obj, e);
650 EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
653 * iopgtable_lookup_entry - Lookup an iommu pte entry
655 * @da: iommu device virtual address
656 * @ppgd: iommu pgd entry pointer to be returned
657 * @ppte: iommu pte entry pointer to be returned
660 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
662 u32 *iopgd, *iopte = NULL;
664 iopgd = iopgd_offset(obj, da);
668 if (iopgd_is_table(*iopgd))
669 iopte = iopte_offset(iopgd, da);
675 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
678 u32 *iopgd = iopgd_offset(obj, da);
684 if (iopgd_is_table(*iopgd)) {
686 u32 *iopte = iopte_offset(iopgd, da);
689 if (*iopte & IOPTE_LARGE) {
691 /* rewind to the 1st entry */
692 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
695 memset(iopte, 0, nent * sizeof(*iopte));
696 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
699 * do table walk to check if this table is necessary or not
701 iopte = iopte_offset(iopgd, 0);
702 for (i = 0; i < PTRS_PER_IOPTE; i++)
707 nent = 1; /* for the next L1 entry */
710 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
712 /* rewind to the 1st entry */
713 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
717 memset(iopgd, 0, nent * sizeof(*iopgd));
718 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
724 * iopgtable_clear_entry - Remove an iommu pte entry
726 * @da: iommu device virtual address
728 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
732 spin_lock(&obj->page_table_lock);
734 bytes = iopgtable_clear_entry_core(obj, da);
735 flush_iotlb_page(obj, da);
737 spin_unlock(&obj->page_table_lock);
742 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
746 spin_lock(&obj->page_table_lock);
748 for (i = 0; i < PTRS_PER_IOPGD; i++) {
752 da = i << IOPGD_SHIFT;
753 iopgd = iopgd_offset(obj, da);
758 if (iopgd_is_table(*iopgd))
759 iopte_free(iopte_offset(iopgd, 0));
762 flush_iopgd_range(iopgd, iopgd);
765 flush_iotlb_all(obj);
767 spin_unlock(&obj->page_table_lock);
771 * Device IOMMU generic operations
773 static irqreturn_t iommu_fault_handler(int irq, void *data)
777 struct omap_iommu *obj = data;
778 struct iommu_domain *domain = obj->domain;
783 clk_enable(obj->clk);
784 errs = iommu_report_fault(obj, &da);
785 clk_disable(obj->clk);
789 /* Fault callback or TLB/PTE Dynamic loading */
790 if (!report_iommu_fault(domain, obj->dev, da, 0))
795 iopgd = iopgd_offset(obj, da);
797 if (!iopgd_is_table(*iopgd)) {
798 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
799 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
803 iopte = iopte_offset(iopgd, da);
805 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
806 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
812 static int device_match_by_alias(struct device *dev, void *data)
814 struct omap_iommu *obj = to_iommu(dev);
815 const char *name = data;
817 pr_debug("%s: %s %s\n", __func__, obj->name, name);
819 return strcmp(obj->name, name) == 0;
823 * omap_find_iommu_device() - find an omap iommu device by name
824 * @name: name of the iommu device
826 * The generic iommu API requires the caller to provide the device
827 * he wishes to attach to a certain iommu domain.
829 * Drivers generally should not bother with this as it should just
830 * be taken care of by the DMA-API using dev_archdata.
832 * This function is provided as an interim solution until the latter
833 * materializes, and omap3isp is fully migrated to the DMA-API.
835 struct device *omap_find_iommu_device(const char *name)
837 return driver_find_device(&omap_iommu_driver.driver, NULL,
839 device_match_by_alias);
841 EXPORT_SYMBOL_GPL(omap_find_iommu_device);
844 * omap_iommu_attach() - attach iommu device to an iommu domain
845 * @dev: target omap iommu device
848 static struct omap_iommu *omap_iommu_attach(struct device *dev, u32 *iopgd)
851 struct omap_iommu *obj = to_iommu(dev);
853 spin_lock(&obj->iommu_lock);
855 /* an iommu device can only be attached once */
856 if (++obj->refcount > 1) {
857 dev_err(dev, "%s: already attached!\n", obj->name);
863 err = iommu_enable(obj);
866 flush_iotlb_all(obj);
868 if (!try_module_get(obj->owner))
871 spin_unlock(&obj->iommu_lock);
873 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
877 if (obj->refcount == 1)
881 spin_unlock(&obj->iommu_lock);
886 * omap_iommu_detach - release iommu device
889 static void omap_iommu_detach(struct omap_iommu *obj)
891 if (!obj || IS_ERR(obj))
894 spin_lock(&obj->iommu_lock);
896 if (--obj->refcount == 0)
899 module_put(obj->owner);
903 spin_unlock(&obj->iommu_lock);
905 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
909 * OMAP Device MMU(IOMMU) detection
911 static int __devinit omap_iommu_probe(struct platform_device *pdev)
915 struct omap_iommu *obj;
916 struct resource *res;
917 struct iommu_platform_data *pdata = pdev->dev.platform_data;
919 if (pdev->num_resources != 2)
922 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
926 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
927 if (IS_ERR(obj->clk))
930 obj->nr_tlb_entries = pdata->nr_tlb_entries;
931 obj->name = pdata->name;
932 obj->dev = &pdev->dev;
933 obj->ctx = (void *)obj + sizeof(*obj);
934 obj->da_start = pdata->da_start;
935 obj->da_end = pdata->da_end;
937 spin_lock_init(&obj->iommu_lock);
938 mutex_init(&obj->mmap_lock);
939 spin_lock_init(&obj->page_table_lock);
940 INIT_LIST_HEAD(&obj->mmap);
942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 res = request_mem_region(res->start, resource_size(res),
949 dev_name(&pdev->dev));
955 obj->regbase = ioremap(res->start, resource_size(res));
961 irq = platform_get_irq(pdev, 0);
966 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
967 dev_name(&pdev->dev), obj);
970 platform_set_drvdata(pdev, obj);
972 dev_info(&pdev->dev, "%s registered\n", obj->name);
976 iounmap(obj->regbase);
978 release_mem_region(res->start, resource_size(res));
986 static int __devexit omap_iommu_remove(struct platform_device *pdev)
989 struct resource *res;
990 struct omap_iommu *obj = platform_get_drvdata(pdev);
992 platform_set_drvdata(pdev, NULL);
994 iopgtable_clear_entry_all(obj);
996 irq = platform_get_irq(pdev, 0);
998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
999 release_mem_region(res->start, resource_size(res));
1000 iounmap(obj->regbase);
1003 dev_info(&pdev->dev, "%s removed\n", obj->name);
1008 static struct platform_driver omap_iommu_driver = {
1009 .probe = omap_iommu_probe,
1010 .remove = __devexit_p(omap_iommu_remove),
1012 .name = "omap-iommu",
1016 static void iopte_cachep_ctor(void *iopte)
1018 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1021 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1022 phys_addr_t pa, int order, int prot)
1024 struct omap_iommu_domain *omap_domain = domain->priv;
1025 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1026 struct device *dev = oiommu->dev;
1027 size_t bytes = PAGE_SIZE << order;
1028 struct iotlb_entry e;
1032 /* we only support mapping a single iommu page for now */
1033 omap_pgsz = bytes_to_iopgsz(bytes);
1034 if (omap_pgsz < 0) {
1035 dev_err(dev, "invalid size to map: %d\n", bytes);
1039 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1041 flags = omap_pgsz | prot;
1043 iotlb_init_entry(&e, da, pa, flags);
1045 ret = omap_iopgtable_store_entry(oiommu, &e);
1047 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1052 static int omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1055 struct omap_iommu_domain *omap_domain = domain->priv;
1056 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1057 struct device *dev = oiommu->dev;
1060 dev_dbg(dev, "unmapping da 0x%lx order %d\n", da, order);
1062 unmap_size = iopgtable_clear_entry(oiommu, da);
1064 return unmap_size ? get_order(unmap_size) : -EINVAL;
1068 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1070 struct omap_iommu_domain *omap_domain = domain->priv;
1071 struct omap_iommu *oiommu;
1074 spin_lock(&omap_domain->lock);
1076 /* only a single device is supported per domain for now */
1077 if (omap_domain->iommu_dev) {
1078 dev_err(dev, "iommu domain is already attached\n");
1083 /* get a handle to and enable the omap iommu */
1084 oiommu = omap_iommu_attach(dev, omap_domain->pgtable);
1085 if (IS_ERR(oiommu)) {
1086 ret = PTR_ERR(oiommu);
1087 dev_err(dev, "can't get omap iommu: %d\n", ret);
1091 omap_domain->iommu_dev = oiommu;
1092 oiommu->domain = domain;
1095 spin_unlock(&omap_domain->lock);
1099 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1102 struct omap_iommu_domain *omap_domain = domain->priv;
1103 struct omap_iommu *oiommu = to_iommu(dev);
1105 spin_lock(&omap_domain->lock);
1107 /* only a single device is supported per domain for now */
1108 if (omap_domain->iommu_dev != oiommu) {
1109 dev_err(dev, "invalid iommu device\n");
1113 iopgtable_clear_entry_all(oiommu);
1115 omap_iommu_detach(oiommu);
1117 omap_domain->iommu_dev = NULL;
1120 spin_unlock(&omap_domain->lock);
1123 static int omap_iommu_domain_init(struct iommu_domain *domain)
1125 struct omap_iommu_domain *omap_domain;
1127 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1129 pr_err("kzalloc failed\n");
1133 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1134 if (!omap_domain->pgtable) {
1135 pr_err("kzalloc failed\n");
1140 * should never fail, but please keep this around to ensure
1141 * we keep the hardware happy
1143 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1145 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1146 spin_lock_init(&omap_domain->lock);
1148 domain->priv = omap_domain;
1158 /* assume device was already detached */
1159 static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1161 struct omap_iommu_domain *omap_domain = domain->priv;
1163 domain->priv = NULL;
1165 kfree(omap_domain->pgtable);
1169 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1172 struct omap_iommu_domain *omap_domain = domain->priv;
1173 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1174 struct device *dev = oiommu->dev;
1176 phys_addr_t ret = 0;
1178 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1181 if (iopte_is_small(*pte))
1182 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1183 else if (iopte_is_large(*pte))
1184 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1186 dev_err(dev, "bogus pte 0x%x", *pte);
1188 if (iopgd_is_section(*pgd))
1189 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1190 else if (iopgd_is_super(*pgd))
1191 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1193 dev_err(dev, "bogus pgd 0x%x", *pgd);
1199 static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1205 static struct iommu_ops omap_iommu_ops = {
1206 .domain_init = omap_iommu_domain_init,
1207 .domain_destroy = omap_iommu_domain_destroy,
1208 .attach_dev = omap_iommu_attach_dev,
1209 .detach_dev = omap_iommu_detach_dev,
1210 .map = omap_iommu_map,
1211 .unmap = omap_iommu_unmap,
1212 .iova_to_phys = omap_iommu_iova_to_phys,
1213 .domain_has_cap = omap_iommu_domain_has_cap,
1216 static int __init omap_iommu_init(void)
1218 struct kmem_cache *p;
1219 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1220 size_t align = 1 << 10; /* L2 pagetable alignement */
1222 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1228 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1230 return platform_driver_register(&omap_iommu_driver);
1232 module_init(omap_iommu_init);
1234 static void __exit omap_iommu_exit(void)
1236 kmem_cache_destroy(iopte_cachep);
1238 platform_driver_unregister(&omap_iommu_driver);
1240 module_exit(omap_iommu_exit);
1242 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1243 MODULE_ALIAS("platform:omap-iommu");
1244 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1245 MODULE_LICENSE("GPL v2");