8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
24 select IRQ_DOMAIN_HIERARCHY
28 select PCI_MSI_IRQ_DOMAIN
33 select IRQ_DOMAIN_HIERARCHY
34 select GENERIC_IRQ_CHIP
39 select MULTI_IRQ_HANDLER
43 default 4 if ARCH_S5PV210
47 The maximum number of VICs available in the system, for
52 select GENERIC_IRQ_CHIP
54 select MULTI_IRQ_HANDLER
59 select GENERIC_IRQ_CHIP
61 select MULTI_IRQ_HANDLER
70 select GENERIC_IRQ_CHIP
75 select GENERIC_IRQ_CHIP
80 select GENERIC_IRQ_CHIP
85 select GENERIC_IRQ_CHIP
90 select GENERIC_IRQ_CHIP
95 select GENERIC_IRQ_CHIP
98 config CLPS711X_IRQCHIP
100 depends on ARCH_CLPS711X
102 select MULTI_IRQ_HANDLER
112 select GENERIC_IRQ_CHIP
118 select MULTI_IRQ_HANDLER
122 select GENERIC_IRQ_CHIP
125 config RENESAS_INTC_IRQPIN
131 select GENERIC_IRQ_CHIP
139 Enables SysCfg Controlled IRQs on STi based platforms.
144 select GENERIC_IRQ_CHIP
146 config VERSATILE_FPGA_IRQ
150 config VERSATILE_FPGA_IRQ_NR
153 depends on VERSATILE_FPGA_IRQ
162 Support for a CROSSBAR ip that precedes the main interrupt controller.
163 The primary irqchip invokes the crossbar's callback which inturn allocates
164 a free irq and configures the IP. Thus the peripheral interrupts are
165 routed to one of the free irqchip interrupt lines.
168 tristate "Keystone 2 IRQ controller IP"
169 depends on ARCH_KEYSTONE
171 Support for Texas Instruments Keystone 2 IRQ controller IP which
172 is part of the Keystone 2 IPC mechanism
180 depends on MACH_INGENIC
183 config RENESAS_H8300H_INTC
187 config RENESAS_H8S_INTC
195 Enables the wakeup IRQs for IMX platforms with GPCv2 block
198 def_bool y if MACH_ASM9260 || ARCH_MXS