8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
24 select IRQ_DOMAIN_HIERARCHY
28 select PCI_MSI_IRQ_DOMAIN
30 config HISILICON_IRQ_MBIGEN
31 bool "Support mbigen interrupt controller"
33 depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
35 Enable the mbigen interrupt controller used on
41 select IRQ_DOMAIN_HIERARCHY
42 select GENERIC_IRQ_CHIP
47 select MULTI_IRQ_HANDLER
51 default 4 if ARCH_S5PV210
55 The maximum number of VICs available in the system, for
60 select GENERIC_IRQ_CHIP
62 select MULTI_IRQ_HANDLER
67 select GENERIC_IRQ_CHIP
69 select MULTI_IRQ_HANDLER
78 select GENERIC_IRQ_CHIP
83 select GENERIC_IRQ_CHIP
88 select GENERIC_IRQ_CHIP
93 select GENERIC_IRQ_CHIP
98 select GENERIC_IRQ_CHIP
103 select GENERIC_IRQ_CHIP
106 config CLPS711X_IRQCHIP
108 depends on ARCH_CLPS711X
110 select MULTI_IRQ_HANDLER
120 select GENERIC_IRQ_CHIP
126 select MULTI_IRQ_HANDLER
128 config RENESAS_INTC_IRQPIN
134 select GENERIC_IRQ_CHIP
142 Enables SysCfg Controlled IRQs on STi based platforms.
147 select GENERIC_IRQ_CHIP
149 config VERSATILE_FPGA_IRQ
153 config VERSATILE_FPGA_IRQ_NR
156 depends on VERSATILE_FPGA_IRQ
165 Support for a CROSSBAR ip that precedes the main interrupt controller.
166 The primary irqchip invokes the crossbar's callback which inturn allocates
167 a free irq and configures the IP. Thus the peripheral interrupts are
168 routed to one of the free irqchip interrupt lines.
171 tristate "Keystone 2 IRQ controller IP"
172 depends on ARCH_KEYSTONE
174 Support for Texas Instruments Keystone 2 IRQ controller IP which
175 is part of the Keystone 2 IPC mechanism
183 depends on MACH_INGENIC
186 config RENESAS_H8300H_INTC
190 config RENESAS_H8S_INTC
198 Enables the wakeup IRQs for IMX platforms with GPCv2 block
201 def_bool y if MACH_ASM9260 || ARCH_MXS