2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/cpu.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/irqdomain.h>
28 #include <linux/slab.h>
29 #include <linux/msi.h>
30 #include <asm/mach/arch.h>
31 #include <asm/exception.h>
32 #include <asm/smp_plat.h>
33 #include <asm/mach/irq.h>
37 /* Interrupt Controller Registers Map */
38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
41 #define ARMADA_370_XP_INT_CONTROL (0x00)
42 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
43 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
44 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
45 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
46 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
48 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
49 #define ARMADA_375_PPI_CAUSE (0x10)
51 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
52 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
53 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
55 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
57 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
59 #define IPI_DOORBELL_START (0)
60 #define IPI_DOORBELL_END (8)
61 #define IPI_DOORBELL_MASK 0xFF
62 #define PCI_MSI_DOORBELL_START (16)
63 #define PCI_MSI_DOORBELL_NR (16)
64 #define PCI_MSI_DOORBELL_END (32)
65 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
67 static void __iomem *per_cpu_int_base;
68 static void __iomem *main_int_base;
69 static struct irq_domain *armada_370_xp_mpic_domain;
71 static struct irq_domain *armada_370_xp_msi_domain;
72 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
73 static DEFINE_MUTEX(msi_used_lock);
74 static phys_addr_t msi_doorbell_addr;
79 * For shared global interrupts, mask/unmask global enable bit
80 * For CPU interrupts, mask/unmask the calling CPU's bit
82 static void armada_370_xp_irq_mask(struct irq_data *d)
84 irq_hw_number_t hwirq = irqd_to_hwirq(d);
86 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
87 writel(hwirq, main_int_base +
88 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
90 writel(hwirq, per_cpu_int_base +
91 ARMADA_370_XP_INT_SET_MASK_OFFS);
94 static void armada_370_xp_irq_unmask(struct irq_data *d)
96 irq_hw_number_t hwirq = irqd_to_hwirq(d);
98 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
99 writel(hwirq, main_int_base +
100 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
102 writel(hwirq, per_cpu_int_base +
103 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
106 #ifdef CONFIG_PCI_MSI
108 static int armada_370_xp_alloc_msi(void)
112 mutex_lock(&msi_used_lock);
113 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
114 if (hwirq >= PCI_MSI_DOORBELL_NR)
117 set_bit(hwirq, msi_used);
118 mutex_unlock(&msi_used_lock);
123 static void armada_370_xp_free_msi(int hwirq)
125 mutex_lock(&msi_used_lock);
126 if (!test_bit(hwirq, msi_used))
127 pr_err("trying to free unused MSI#%d\n", hwirq);
129 clear_bit(hwirq, msi_used);
130 mutex_unlock(&msi_used_lock);
133 static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
134 struct pci_dev *pdev,
135 struct msi_desc *desc)
140 /* We support MSI, but not MSI-X */
141 if (desc->msi_attrib.is_msix)
144 hwirq = armada_370_xp_alloc_msi();
148 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
150 armada_370_xp_free_msi(hwirq);
154 irq_set_msi_desc(virq, desc);
156 msg.address_lo = msi_doorbell_addr;
158 msg.data = 0xf00 | (hwirq + 16);
160 write_msi_msg(virq, &msg);
164 static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
167 struct irq_data *d = irq_get_irq_data(irq);
168 unsigned long hwirq = d->hwirq;
170 irq_dispose_mapping(irq);
171 armada_370_xp_free_msi(hwirq);
174 static struct irq_chip armada_370_xp_msi_irq_chip = {
175 .name = "armada_370_xp_msi_irq",
176 .irq_enable = unmask_msi_irq,
177 .irq_disable = mask_msi_irq,
178 .irq_mask = mask_msi_irq,
179 .irq_unmask = unmask_msi_irq,
182 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
185 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
187 set_irq_flags(virq, IRQF_VALID);
192 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
193 .map = armada_370_xp_msi_map,
196 static int armada_370_xp_msi_init(struct device_node *node,
197 phys_addr_t main_int_phys_base)
199 struct msi_chip *msi_chip;
203 msi_doorbell_addr = main_int_phys_base +
204 ARMADA_370_XP_SW_TRIG_INT_OFFS;
206 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
210 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
211 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
212 msi_chip->of_node = node;
214 armada_370_xp_msi_domain =
215 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
216 &armada_370_xp_msi_irq_ops,
218 if (!armada_370_xp_msi_domain) {
223 ret = of_pci_msi_chip_add(msi_chip);
225 irq_domain_remove(armada_370_xp_msi_domain);
230 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
231 | PCI_MSI_DOORBELL_MASK;
233 writel(reg, per_cpu_int_base +
234 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
236 /* Unmask IPI interrupt */
237 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
242 static inline int armada_370_xp_msi_init(struct device_node *node,
243 phys_addr_t main_int_phys_base)
250 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
252 static int armada_xp_set_affinity(struct irq_data *d,
253 const struct cpumask *mask_val, bool force)
255 irq_hw_number_t hwirq = irqd_to_hwirq(d);
256 unsigned long reg, mask;
259 /* Select a single core from the affinity mask which is online */
260 cpu = cpumask_any_and(mask_val, cpu_online_mask);
261 mask = 1UL << cpu_logical_map(cpu);
263 raw_spin_lock(&irq_controller_lock);
264 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
265 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
266 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
267 raw_spin_unlock(&irq_controller_lock);
273 static struct irq_chip armada_370_xp_irq_chip = {
274 .name = "armada_370_xp_irq",
275 .irq_mask = armada_370_xp_irq_mask,
276 .irq_mask_ack = armada_370_xp_irq_mask,
277 .irq_unmask = armada_370_xp_irq_unmask,
279 .irq_set_affinity = armada_xp_set_affinity,
283 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
284 unsigned int virq, irq_hw_number_t hw)
286 armada_370_xp_irq_mask(irq_get_irq_data(virq));
287 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
288 writel(hw, per_cpu_int_base +
289 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
291 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
292 irq_set_status_flags(virq, IRQ_LEVEL);
294 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
295 irq_set_percpu_devid(virq);
296 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
297 handle_percpu_devid_irq);
300 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
303 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
309 static void armada_mpic_send_doorbell(const struct cpumask *mask,
313 unsigned long map = 0;
315 /* Convert our logical CPU mask into a physical one. */
316 for_each_cpu(cpu, mask)
317 map |= 1 << cpu_logical_map(cpu);
320 * Ensure that stores to Normal memory are visible to the
321 * other CPUs before issuing the IPI.
326 writel((map << 8) | irq, main_int_base +
327 ARMADA_370_XP_SW_TRIG_INT_OFFS);
330 static void armada_xp_mpic_smp_cpu_init(void)
335 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
336 nr_irqs = (control >> 2) & 0x3ff;
338 for (i = 0; i < nr_irqs; i++)
339 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
341 /* Clear pending IPIs */
342 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
344 /* Enable first 8 IPIs */
345 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
346 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
348 /* Unmask IPI interrupt */
349 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
352 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
353 unsigned long action, void *hcpu)
355 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
356 armada_xp_mpic_smp_cpu_init();
360 static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
361 .notifier_call = armada_xp_mpic_secondary_init,
365 #endif /* CONFIG_SMP */
367 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
368 .map = armada_370_xp_mpic_irq_map,
369 .xlate = irq_domain_xlate_onecell,
372 #ifdef CONFIG_PCI_MSI
373 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
377 msimask = readl_relaxed(per_cpu_int_base +
378 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
379 & PCI_MSI_DOORBELL_MASK;
381 writel(~msimask, per_cpu_int_base +
382 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
384 for (msinr = PCI_MSI_DOORBELL_START;
385 msinr < PCI_MSI_DOORBELL_END; msinr++) {
388 if (!(msimask & BIT(msinr)))
392 irq = irq_find_mapping(armada_370_xp_msi_domain,
394 generic_handle_irq(irq);
397 handle_domain_irq(armada_370_xp_msi_domain,
403 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
406 static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
407 struct irq_desc *desc)
409 struct irq_chip *chip = irq_get_chip(irq);
410 unsigned long irqmap, irqn, irqsrc, cpuid;
411 unsigned int cascade_irq;
413 chained_irq_enter(chip, desc);
415 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
416 cpuid = cpu_logical_map(smp_processor_id());
418 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
419 irqsrc = readl_relaxed(main_int_base +
420 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
422 /* Check if the interrupt is not masked on current CPU.
423 * Test IRQ (0-1) and FIQ (8-9) mask bits.
425 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
429 armada_370_xp_handle_msi_irq(NULL, true);
433 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
434 generic_handle_irq(cascade_irq);
437 chained_irq_exit(chip, desc);
440 static void __exception_irq_entry
441 armada_370_xp_handle_irq(struct pt_regs *regs)
446 irqstat = readl_relaxed(per_cpu_int_base +
447 ARMADA_370_XP_CPU_INTACK_OFFS);
448 irqnr = irqstat & 0x3FF;
454 handle_domain_irq(armada_370_xp_mpic_domain,
461 armada_370_xp_handle_msi_irq(regs, false);
468 ipimask = readl_relaxed(per_cpu_int_base +
469 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
472 writel(~ipimask, per_cpu_int_base +
473 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
475 /* Handle all pending doorbells */
476 for (ipinr = IPI_DOORBELL_START;
477 ipinr < IPI_DOORBELL_END; ipinr++) {
478 if (ipimask & (0x1 << ipinr))
479 handle_IPI(ipinr, regs);
488 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
489 struct device_node *parent)
491 struct resource main_int_res, per_cpu_int_res;
492 int parent_irq, nr_irqs, i;
495 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
496 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
498 BUG_ON(!request_mem_region(main_int_res.start,
499 resource_size(&main_int_res),
501 BUG_ON(!request_mem_region(per_cpu_int_res.start,
502 resource_size(&per_cpu_int_res),
505 main_int_base = ioremap(main_int_res.start,
506 resource_size(&main_int_res));
507 BUG_ON(!main_int_base);
509 per_cpu_int_base = ioremap(per_cpu_int_res.start,
510 resource_size(&per_cpu_int_res));
511 BUG_ON(!per_cpu_int_base);
513 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
514 nr_irqs = (control >> 2) & 0x3ff;
516 for (i = 0; i < nr_irqs; i++)
517 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
519 armada_370_xp_mpic_domain =
520 irq_domain_add_linear(node, nr_irqs,
521 &armada_370_xp_mpic_irq_ops, NULL);
523 BUG_ON(!armada_370_xp_mpic_domain);
526 armada_xp_mpic_smp_cpu_init();
529 armada_370_xp_msi_init(node, main_int_res.start);
531 parent_irq = irq_of_parse_and_map(node, 0);
532 if (parent_irq <= 0) {
533 irq_set_default_host(armada_370_xp_mpic_domain);
534 set_handle_irq(armada_370_xp_handle_irq);
536 set_smp_cross_call(armada_mpic_send_doorbell);
537 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
540 irq_set_chained_handler(parent_irq,
541 armada_370_xp_mpic_handle_cascade_irq);
547 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);