2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/cpu.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/irqdomain.h>
28 #include <linux/slab.h>
29 #include <linux/msi.h>
30 #include <asm/mach/arch.h>
31 #include <asm/exception.h>
32 #include <asm/smp_plat.h>
33 #include <asm/mach/irq.h>
37 /* Interrupt Controller Registers Map */
38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
41 #define ARMADA_370_XP_INT_CONTROL (0x00)
42 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
43 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
44 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
45 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
47 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
48 #define ARMADA_375_PPI_CAUSE (0x10)
50 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
51 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
52 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
54 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
56 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
58 #define IPI_DOORBELL_START (0)
59 #define IPI_DOORBELL_END (8)
60 #define IPI_DOORBELL_MASK 0xFF
61 #define PCI_MSI_DOORBELL_START (16)
62 #define PCI_MSI_DOORBELL_NR (16)
63 #define PCI_MSI_DOORBELL_END (32)
64 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
66 static void __iomem *per_cpu_int_base;
67 static void __iomem *main_int_base;
68 static struct irq_domain *armada_370_xp_mpic_domain;
70 static struct irq_domain *armada_370_xp_msi_domain;
71 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
72 static DEFINE_MUTEX(msi_used_lock);
73 static phys_addr_t msi_doorbell_addr;
78 * For shared global interrupts, mask/unmask global enable bit
79 * For CPU interrupts, mask/unmask the calling CPU's bit
81 static void armada_370_xp_irq_mask(struct irq_data *d)
83 irq_hw_number_t hwirq = irqd_to_hwirq(d);
85 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
86 writel(hwirq, main_int_base +
87 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
89 writel(hwirq, per_cpu_int_base +
90 ARMADA_370_XP_INT_SET_MASK_OFFS);
93 static void armada_370_xp_irq_unmask(struct irq_data *d)
95 irq_hw_number_t hwirq = irqd_to_hwirq(d);
97 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
98 writel(hwirq, main_int_base +
99 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
101 writel(hwirq, per_cpu_int_base +
102 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
105 #ifdef CONFIG_PCI_MSI
107 static int armada_370_xp_alloc_msi(void)
111 mutex_lock(&msi_used_lock);
112 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
113 if (hwirq >= PCI_MSI_DOORBELL_NR)
116 set_bit(hwirq, msi_used);
117 mutex_unlock(&msi_used_lock);
122 static void armada_370_xp_free_msi(int hwirq)
124 mutex_lock(&msi_used_lock);
125 if (!test_bit(hwirq, msi_used))
126 pr_err("trying to free unused MSI#%d\n", hwirq);
128 clear_bit(hwirq, msi_used);
129 mutex_unlock(&msi_used_lock);
132 static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
133 struct pci_dev *pdev,
134 struct msi_desc *desc)
139 hwirq = armada_370_xp_alloc_msi();
143 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
145 armada_370_xp_free_msi(hwirq);
149 irq_set_msi_desc(virq, desc);
151 msg.address_lo = msi_doorbell_addr;
153 msg.data = 0xf00 | (hwirq + 16);
155 write_msi_msg(virq, &msg);
159 static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
162 struct irq_data *d = irq_get_irq_data(irq);
163 unsigned long hwirq = d->hwirq;
165 irq_dispose_mapping(irq);
166 armada_370_xp_free_msi(hwirq);
169 static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,
172 /* We support MSI, but not MSI-X */
173 if (type == PCI_CAP_ID_MSI)
178 static struct irq_chip armada_370_xp_msi_irq_chip = {
179 .name = "armada_370_xp_msi_irq",
180 .irq_enable = unmask_msi_irq,
181 .irq_disable = mask_msi_irq,
182 .irq_mask = mask_msi_irq,
183 .irq_unmask = unmask_msi_irq,
186 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
189 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
191 set_irq_flags(virq, IRQF_VALID);
196 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
197 .map = armada_370_xp_msi_map,
200 static int armada_370_xp_msi_init(struct device_node *node,
201 phys_addr_t main_int_phys_base)
203 struct msi_chip *msi_chip;
207 msi_doorbell_addr = main_int_phys_base +
208 ARMADA_370_XP_SW_TRIG_INT_OFFS;
210 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
214 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
215 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
216 msi_chip->check_device = armada_370_xp_check_msi_device;
217 msi_chip->of_node = node;
219 armada_370_xp_msi_domain =
220 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
221 &armada_370_xp_msi_irq_ops,
223 if (!armada_370_xp_msi_domain) {
228 ret = of_pci_msi_chip_add(msi_chip);
230 irq_domain_remove(armada_370_xp_msi_domain);
235 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
236 | PCI_MSI_DOORBELL_MASK;
238 writel(reg, per_cpu_int_base +
239 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
241 /* Unmask IPI interrupt */
242 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
247 static inline int armada_370_xp_msi_init(struct device_node *node,
248 phys_addr_t main_int_phys_base)
255 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
257 static int armada_xp_set_affinity(struct irq_data *d,
258 const struct cpumask *mask_val, bool force)
260 irq_hw_number_t hwirq = irqd_to_hwirq(d);
261 unsigned long reg, mask;
264 /* Select a single core from the affinity mask which is online */
265 cpu = cpumask_any_and(mask_val, cpu_online_mask);
266 mask = 1UL << cpu_logical_map(cpu);
268 raw_spin_lock(&irq_controller_lock);
269 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
270 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
271 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
272 raw_spin_unlock(&irq_controller_lock);
278 static struct irq_chip armada_370_xp_irq_chip = {
279 .name = "armada_370_xp_irq",
280 .irq_mask = armada_370_xp_irq_mask,
281 .irq_mask_ack = armada_370_xp_irq_mask,
282 .irq_unmask = armada_370_xp_irq_unmask,
284 .irq_set_affinity = armada_xp_set_affinity,
288 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
289 unsigned int virq, irq_hw_number_t hw)
291 armada_370_xp_irq_mask(irq_get_irq_data(virq));
292 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
293 writel(hw, per_cpu_int_base +
294 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
296 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
297 irq_set_status_flags(virq, IRQ_LEVEL);
299 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
300 irq_set_percpu_devid(virq);
301 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
302 handle_percpu_devid_irq);
305 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
308 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
314 static void armada_mpic_send_doorbell(const struct cpumask *mask,
318 unsigned long map = 0;
320 /* Convert our logical CPU mask into a physical one. */
321 for_each_cpu(cpu, mask)
322 map |= 1 << cpu_logical_map(cpu);
325 * Ensure that stores to Normal memory are visible to the
326 * other CPUs before issuing the IPI.
331 writel((map << 8) | irq, main_int_base +
332 ARMADA_370_XP_SW_TRIG_INT_OFFS);
335 static void armada_xp_mpic_smp_cpu_init(void)
340 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
341 nr_irqs = (control >> 2) & 0x3ff;
343 for (i = 0; i < nr_irqs; i++)
344 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
346 /* Clear pending IPIs */
347 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
349 /* Enable first 8 IPIs */
350 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
351 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
353 /* Unmask IPI interrupt */
354 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
357 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
358 unsigned long action, void *hcpu)
360 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
361 armada_xp_mpic_smp_cpu_init();
365 static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
366 .notifier_call = armada_xp_mpic_secondary_init,
370 #endif /* CONFIG_SMP */
372 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
373 .map = armada_370_xp_mpic_irq_map,
374 .xlate = irq_domain_xlate_onecell,
377 #ifdef CONFIG_PCI_MSI
378 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
382 msimask = readl_relaxed(per_cpu_int_base +
383 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
384 & PCI_MSI_DOORBELL_MASK;
386 writel(~msimask, per_cpu_int_base +
387 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
389 for (msinr = PCI_MSI_DOORBELL_START;
390 msinr < PCI_MSI_DOORBELL_END; msinr++) {
393 if (!(msimask & BIT(msinr)))
396 irq = irq_find_mapping(armada_370_xp_msi_domain,
400 generic_handle_irq(irq);
402 handle_IRQ(irq, regs);
406 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
409 static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
410 struct irq_desc *desc)
412 struct irq_chip *chip = irq_get_chip(irq);
413 unsigned long irqmap, irqn;
414 unsigned int cascade_irq;
416 chained_irq_enter(chip, desc);
418 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
420 if (irqmap & BIT(0)) {
421 armada_370_xp_handle_msi_irq(NULL, true);
425 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
426 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
427 generic_handle_irq(cascade_irq);
430 chained_irq_exit(chip, desc);
433 static void __exception_irq_entry
434 armada_370_xp_handle_irq(struct pt_regs *regs)
439 irqstat = readl_relaxed(per_cpu_int_base +
440 ARMADA_370_XP_CPU_INTACK_OFFS);
441 irqnr = irqstat & 0x3FF;
447 irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
449 handle_IRQ(irqnr, regs);
455 armada_370_xp_handle_msi_irq(regs, false);
462 ipimask = readl_relaxed(per_cpu_int_base +
463 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
466 writel(~ipimask, per_cpu_int_base +
467 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
469 /* Handle all pending doorbells */
470 for (ipinr = IPI_DOORBELL_START;
471 ipinr < IPI_DOORBELL_END; ipinr++) {
472 if (ipimask & (0x1 << ipinr))
473 handle_IPI(ipinr, regs);
482 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
483 struct device_node *parent)
485 struct resource main_int_res, per_cpu_int_res;
486 int parent_irq, nr_irqs, i;
489 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
490 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
492 BUG_ON(!request_mem_region(main_int_res.start,
493 resource_size(&main_int_res),
495 BUG_ON(!request_mem_region(per_cpu_int_res.start,
496 resource_size(&per_cpu_int_res),
499 main_int_base = ioremap(main_int_res.start,
500 resource_size(&main_int_res));
501 BUG_ON(!main_int_base);
503 per_cpu_int_base = ioremap(per_cpu_int_res.start,
504 resource_size(&per_cpu_int_res));
505 BUG_ON(!per_cpu_int_base);
507 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
508 nr_irqs = (control >> 2) & 0x3ff;
510 for (i = 0; i < nr_irqs; i++)
511 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
513 armada_370_xp_mpic_domain =
514 irq_domain_add_linear(node, nr_irqs,
515 &armada_370_xp_mpic_irq_ops, NULL);
517 BUG_ON(!armada_370_xp_mpic_domain);
520 armada_xp_mpic_smp_cpu_init();
523 armada_370_xp_msi_init(node, main_int_res.start);
525 parent_irq = irq_of_parse_and_map(node, 0);
526 if (parent_irq <= 0) {
527 irq_set_default_host(armada_370_xp_mpic_domain);
528 set_handle_irq(armada_370_xp_handle_irq);
530 set_smp_cross_call(armada_mpic_send_doorbell);
531 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
534 irq_set_chained_handler(parent_irq,
535 armada_370_xp_mpic_handle_cascade_irq);
541 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);