2 * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver
4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson
7 * Copyright (C) 2014 Free Electrons
9 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/init.h>
17 #include <linux/module.h>
19 #include <linux/bitmap.h>
20 #include <linux/types.h>
21 #include <linux/irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/err.h>
27 #include <linux/slab.h>
30 #include <asm/exception.h>
31 #include <asm/mach/irq.h>
33 #include "irq-atmel-aic-common.h"
36 /* Number of irq lines managed by AIC */
37 #define NR_AIC5_IRQS 128
39 #define AT91_AIC5_SSR 0x0
40 #define AT91_AIC5_INTSEL_MSK (0x7f << 0)
42 #define AT91_AIC5_SMR 0x4
44 #define AT91_AIC5_SVR 0x8
45 #define AT91_AIC5_IVR 0x10
46 #define AT91_AIC5_FVR 0x14
47 #define AT91_AIC5_ISR 0x18
49 #define AT91_AIC5_IPR0 0x20
50 #define AT91_AIC5_IPR1 0x24
51 #define AT91_AIC5_IPR2 0x28
52 #define AT91_AIC5_IPR3 0x2c
53 #define AT91_AIC5_IMR 0x30
54 #define AT91_AIC5_CISR 0x34
56 #define AT91_AIC5_IECR 0x40
57 #define AT91_AIC5_IDCR 0x44
58 #define AT91_AIC5_ICCR 0x48
59 #define AT91_AIC5_ISCR 0x4c
60 #define AT91_AIC5_EOICR 0x38
61 #define AT91_AIC5_SPU 0x3c
62 #define AT91_AIC5_DCR 0x6c
64 #define AT91_AIC5_FFER 0x50
65 #define AT91_AIC5_FFDR 0x54
66 #define AT91_AIC5_FFSR 0x58
68 static struct irq_domain *aic5_domain;
70 static asmlinkage void __exception_irq_entry
71 aic5_handle(struct pt_regs *regs)
73 struct irq_domain_chip_generic *dgc = aic5_domain->gc;
74 struct irq_chip_generic *gc = dgc->gc[0];
78 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR);
79 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR);
81 irqnr = irq_find_mapping(aic5_domain, irqnr);
84 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
86 handle_IRQ(irqnr, regs);
89 static void aic5_mask(struct irq_data *d)
91 struct irq_domain *domain = d->domain;
92 struct irq_domain_chip_generic *dgc = domain->gc;
93 struct irq_chip_generic *gc = dgc->gc[0];
95 /* Disable interrupt on AIC5 */
97 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
98 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
99 gc->mask_cache &= ~d->mask;
103 static void aic5_unmask(struct irq_data *d)
105 struct irq_domain *domain = d->domain;
106 struct irq_domain_chip_generic *dgc = domain->gc;
107 struct irq_chip_generic *gc = dgc->gc[0];
109 /* Enable interrupt on AIC5 */
111 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
112 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR);
113 gc->mask_cache |= d->mask;
117 static int aic5_retrigger(struct irq_data *d)
119 struct irq_domain *domain = d->domain;
120 struct irq_domain_chip_generic *dgc = domain->gc;
121 struct irq_chip_generic *gc = dgc->gc[0];
123 /* Enable interrupt on AIC5 */
125 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
126 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR);
132 static int aic5_set_type(struct irq_data *d, unsigned type)
134 struct irq_domain *domain = d->domain;
135 struct irq_domain_chip_generic *dgc = domain->gc;
136 struct irq_chip_generic *gc = dgc->gc[0];
141 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
142 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
143 ret = aic_common_set_type(d, type, &smr);
145 irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR);
152 static void aic5_suspend(struct irq_data *d)
154 struct irq_domain *domain = d->domain;
155 struct irq_domain_chip_generic *dgc = domain->gc;
156 struct irq_chip_generic *bgc = dgc->gc[0];
157 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
162 for (i = 0; i < dgc->irqs_per_chip; i++) {
164 if ((mask & gc->mask_cache) == (mask & gc->wake_active))
167 irq_reg_writel(i + gc->irq_base,
168 bgc->reg_base + AT91_AIC5_SSR);
169 if (mask & gc->wake_active)
170 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
172 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
177 static void aic5_resume(struct irq_data *d)
179 struct irq_domain *domain = d->domain;
180 struct irq_domain_chip_generic *dgc = domain->gc;
181 struct irq_chip_generic *bgc = dgc->gc[0];
182 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
187 for (i = 0; i < dgc->irqs_per_chip; i++) {
189 if ((mask & gc->mask_cache) == (mask & gc->wake_active))
192 irq_reg_writel(i + gc->irq_base,
193 bgc->reg_base + AT91_AIC5_SSR);
194 if (mask & gc->mask_cache)
195 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
197 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
202 static void aic5_pm_shutdown(struct irq_data *d)
204 struct irq_domain *domain = d->domain;
205 struct irq_domain_chip_generic *dgc = domain->gc;
206 struct irq_chip_generic *bgc = dgc->gc[0];
207 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
211 for (i = 0; i < dgc->irqs_per_chip; i++) {
212 irq_reg_writel(i + gc->irq_base,
213 bgc->reg_base + AT91_AIC5_SSR);
214 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
215 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
220 #define aic5_suspend NULL
221 #define aic5_resume NULL
222 #define aic5_pm_shutdown NULL
223 #endif /* CONFIG_PM */
225 static void __init aic5_hw_init(struct irq_domain *domain)
227 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
231 * Perform 8 End Of Interrupt Command to make sure AIC
232 * will not Lock out nIRQ
234 for (i = 0; i < 8; i++)
235 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
238 * Spurious Interrupt ID in Spurious Vector Register.
239 * When there is no current interrupt, the IRQ Vector Register
240 * reads the value stored in AIC_SPU
242 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU);
244 /* No debugging in AIC: Debug (Protect) Control Register */
245 irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR);
247 /* Disable and clear all interrupts initially */
248 for (i = 0; i < domain->revmap_size; i++) {
249 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR);
250 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR);
251 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
252 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR);
256 static int aic5_irq_domain_xlate(struct irq_domain *d,
257 struct device_node *ctrlr,
258 const u32 *intspec, unsigned int intsize,
259 irq_hw_number_t *out_hwirq,
260 unsigned int *out_type)
262 struct irq_domain_chip_generic *dgc = d->gc;
263 struct irq_chip_generic *gc;
270 ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
271 out_hwirq, out_type);
278 irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR);
279 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
280 ret = aic_common_set_priority(intspec[2], &smr);
282 irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);
288 static const struct irq_domain_ops aic5_irq_ops = {
289 .map = irq_map_generic_chip,
290 .xlate = aic5_irq_domain_xlate,
293 static void __init sama5d3_aic_irq_fixup(struct device_node *root)
295 aic_common_rtc_irq_fixup(root);
298 static const struct of_device_id __initdata aic5_irq_fixups[] = {
299 { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
303 static int __init aic5_of_init(struct device_node *node,
304 struct device_node *parent,
307 struct irq_chip_generic *gc;
308 struct irq_domain *domain;
312 if (nirqs > NR_AIC5_IRQS)
318 domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
321 return PTR_ERR(domain);
323 aic_common_irq_fixup(aic5_irq_fixups);
325 aic5_domain = domain;
326 nchips = aic5_domain->revmap_size / 32;
327 for (i = 0; i < nchips; i++) {
328 gc = irq_get_domain_generic_chip(domain, i * 32);
330 gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
331 gc->chip_types[0].chip.irq_mask = aic5_mask;
332 gc->chip_types[0].chip.irq_unmask = aic5_unmask;
333 gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
334 gc->chip_types[0].chip.irq_set_type = aic5_set_type;
335 gc->chip_types[0].chip.irq_suspend = aic5_suspend;
336 gc->chip_types[0].chip.irq_resume = aic5_resume;
337 gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
340 aic5_hw_init(domain);
341 set_handle_irq(aic5_handle);
346 #define NR_SAMA5D3_IRQS 50
348 static int __init sama5d3_aic5_of_init(struct device_node *node,
349 struct device_node *parent)
351 return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
353 IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);