2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/acpi.h>
19 #include <linux/cpu.h>
20 #include <linux/cpu_pm.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/percpu.h>
28 #include <linux/slab.h>
30 #include <linux/irqchip.h>
31 #include <linux/irqchip/arm-gic-v3.h>
33 #include <asm/cputype.h>
34 #include <asm/exception.h>
35 #include <asm/smp_plat.h>
38 #include "irq-gic-common.h"
40 struct redist_region {
41 void __iomem *redist_base;
42 phys_addr_t phys_base;
46 struct gic_chip_data {
47 void __iomem *dist_base;
48 struct redist_region *redist_regions;
50 struct irq_domain *domain;
52 u32 nr_redist_regions;
56 static struct gic_chip_data gic_data __read_mostly;
57 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
59 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
60 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
61 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
63 /* Our default, arbitrary priority value. Linux only uses one anyway. */
64 #define DEFAULT_PMR_VALUE 0xf0
66 static inline unsigned int gic_irq(struct irq_data *d)
71 static inline int gic_irq_in_rdist(struct irq_data *d)
73 return gic_irq(d) < 32;
76 static inline void __iomem *gic_dist_base(struct irq_data *d)
78 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
79 return gic_data_rdist_sgi_base();
81 if (d->hwirq <= 1023) /* SPI -> dist_base */
82 return gic_data.dist_base;
87 static void gic_do_wait_for_rwp(void __iomem *base)
89 u32 count = 1000000; /* 1s! */
91 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
94 pr_err_ratelimited("RWP timeout, gone fishing\n");
102 /* Wait for completion of a distributor change */
103 static void gic_dist_wait_for_rwp(void)
105 gic_do_wait_for_rwp(gic_data.dist_base);
108 /* Wait for completion of a redistributor change */
109 static void gic_redist_wait_for_rwp(void)
111 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
115 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);
117 static u64 __maybe_unused gic_read_iar(void)
119 if (static_branch_unlikely(&is_cavium_thunderx))
120 return gic_read_iar_cavium_thunderx();
122 return gic_read_iar_common();
126 static void gic_enable_redist(bool enable)
129 u32 count = 1000000; /* 1s! */
132 rbase = gic_data_rdist_rd_base();
134 val = readl_relaxed(rbase + GICR_WAKER);
136 /* Wake up this CPU redistributor */
137 val &= ~GICR_WAKER_ProcessorSleep;
139 val |= GICR_WAKER_ProcessorSleep;
140 writel_relaxed(val, rbase + GICR_WAKER);
142 if (!enable) { /* Check that GICR_WAKER is writeable */
143 val = readl_relaxed(rbase + GICR_WAKER);
144 if (!(val & GICR_WAKER_ProcessorSleep))
145 return; /* No PM support in this redistributor */
149 val = readl_relaxed(rbase + GICR_WAKER);
150 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
156 pr_err_ratelimited("redistributor failed to %s...\n",
157 enable ? "wakeup" : "sleep");
161 * Routines to disable, enable, EOI and route interrupts
163 static int gic_peek_irq(struct irq_data *d, u32 offset)
165 u32 mask = 1 << (gic_irq(d) % 32);
168 if (gic_irq_in_rdist(d))
169 base = gic_data_rdist_sgi_base();
171 base = gic_data.dist_base;
173 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
176 static void gic_poke_irq(struct irq_data *d, u32 offset)
178 u32 mask = 1 << (gic_irq(d) % 32);
179 void (*rwp_wait)(void);
182 if (gic_irq_in_rdist(d)) {
183 base = gic_data_rdist_sgi_base();
184 rwp_wait = gic_redist_wait_for_rwp;
186 base = gic_data.dist_base;
187 rwp_wait = gic_dist_wait_for_rwp;
190 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
194 static void gic_mask_irq(struct irq_data *d)
196 gic_poke_irq(d, GICD_ICENABLER);
199 static void gic_eoimode1_mask_irq(struct irq_data *d)
203 * When masking a forwarded interrupt, make sure it is
204 * deactivated as well.
206 * This ensures that an interrupt that is getting
207 * disabled/masked will not get "stuck", because there is
208 * noone to deactivate it (guest is being terminated).
210 if (irqd_is_forwarded_to_vcpu(d))
211 gic_poke_irq(d, GICD_ICACTIVER);
214 static void gic_unmask_irq(struct irq_data *d)
216 gic_poke_irq(d, GICD_ISENABLER);
219 static int gic_irq_set_irqchip_state(struct irq_data *d,
220 enum irqchip_irq_state which, bool val)
224 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
228 case IRQCHIP_STATE_PENDING:
229 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
232 case IRQCHIP_STATE_ACTIVE:
233 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
236 case IRQCHIP_STATE_MASKED:
237 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
244 gic_poke_irq(d, reg);
248 static int gic_irq_get_irqchip_state(struct irq_data *d,
249 enum irqchip_irq_state which, bool *val)
251 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
255 case IRQCHIP_STATE_PENDING:
256 *val = gic_peek_irq(d, GICD_ISPENDR);
259 case IRQCHIP_STATE_ACTIVE:
260 *val = gic_peek_irq(d, GICD_ISACTIVER);
263 case IRQCHIP_STATE_MASKED:
264 *val = !gic_peek_irq(d, GICD_ISENABLER);
274 static void gic_eoi_irq(struct irq_data *d)
276 gic_write_eoir(gic_irq(d));
279 static void gic_eoimode1_eoi_irq(struct irq_data *d)
282 * No need to deactivate an LPI, or an interrupt that
283 * is is getting forwarded to a vcpu.
285 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
287 gic_write_dir(gic_irq(d));
290 static int gic_set_type(struct irq_data *d, unsigned int type)
292 unsigned int irq = gic_irq(d);
293 void (*rwp_wait)(void);
296 /* Interrupt configuration for SGIs can't be changed */
300 /* SPIs have restrictions on the supported types */
301 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
302 type != IRQ_TYPE_EDGE_RISING)
305 if (gic_irq_in_rdist(d)) {
306 base = gic_data_rdist_sgi_base();
307 rwp_wait = gic_redist_wait_for_rwp;
309 base = gic_data.dist_base;
310 rwp_wait = gic_dist_wait_for_rwp;
313 return gic_configure_irq(irq, type, base, rwp_wait);
316 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
319 irqd_set_forwarded_to_vcpu(d);
321 irqd_clr_forwarded_to_vcpu(d);
325 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
329 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
330 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
331 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
332 MPIDR_AFFINITY_LEVEL(mpidr, 0));
337 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
342 irqnr = gic_read_iar();
344 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
347 if (static_key_true(&supports_deactivate))
348 gic_write_eoir(irqnr);
350 err = handle_domain_irq(gic_data.domain, irqnr, regs);
352 WARN_ONCE(true, "Unexpected interrupt received!\n");
353 if (static_key_true(&supports_deactivate)) {
355 gic_write_dir(irqnr);
357 gic_write_eoir(irqnr);
363 gic_write_eoir(irqnr);
364 if (static_key_true(&supports_deactivate))
365 gic_write_dir(irqnr);
367 handle_IPI(irqnr, regs);
369 WARN_ONCE(true, "Unexpected SGI received!\n");
373 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
376 static void __init gic_dist_init(void)
380 void __iomem *base = gic_data.dist_base;
382 /* Disable the distributor */
383 writel_relaxed(0, base + GICD_CTLR);
384 gic_dist_wait_for_rwp();
386 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
388 /* Enable distributor with ARE, Group1 */
389 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
393 * Set all global interrupts to the boot CPU only. ARE must be
396 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
397 for (i = 32; i < gic_data.irq_nr; i++)
398 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
401 static int gic_populate_rdist(void)
403 unsigned long mpidr = cpu_logical_map(smp_processor_id());
409 * Convert affinity to a 32bit value that can be matched to
410 * GICR_TYPER bits [63:32].
412 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
413 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
414 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
415 MPIDR_AFFINITY_LEVEL(mpidr, 0));
417 for (i = 0; i < gic_data.nr_redist_regions; i++) {
418 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
421 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
422 if (reg != GIC_PIDR2_ARCH_GICv3 &&
423 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
424 pr_warn("No redistributor present @%p\n", ptr);
429 typer = gic_read_typer(ptr + GICR_TYPER);
430 if ((typer >> 32) == aff) {
431 u64 offset = ptr - gic_data.redist_regions[i].redist_base;
432 gic_data_rdist_rd_base() = ptr;
433 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
434 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
435 smp_processor_id(), mpidr, i,
436 &gic_data_rdist()->phys_base);
440 if (gic_data.redist_regions[i].single_redist)
443 if (gic_data.redist_stride) {
444 ptr += gic_data.redist_stride;
446 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
447 if (typer & GICR_TYPER_VLPIS)
448 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
450 } while (!(typer & GICR_TYPER_LAST));
453 /* We couldn't even deal with ourselves... */
454 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
455 smp_processor_id(), mpidr);
459 static void gic_cpu_sys_reg_init(void)
462 * Need to check that the SRE bit has actually been set. If
463 * not, it means that SRE is disabled at EL2. We're going to
464 * die painfully, and there is nothing we can do about it.
466 * Kindly inform the luser.
468 if (!gic_enable_sre())
469 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
471 /* Set priority mask register */
472 gic_write_pmr(DEFAULT_PMR_VALUE);
474 if (static_key_true(&supports_deactivate)) {
475 /* EOI drops priority only (mode 1) */
476 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
478 /* EOI deactivates interrupt too (mode 0) */
479 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
482 /* ... and let's hit the road... */
486 static int gic_dist_supports_lpis(void)
488 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
491 static void gic_cpu_init(void)
495 /* Register ourselves with the rest of the world */
496 if (gic_populate_rdist())
499 gic_enable_redist(true);
501 rbase = gic_data_rdist_sgi_base();
503 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
505 /* Give LPIs a spin */
506 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
509 /* initialise system registers */
510 gic_cpu_sys_reg_init();
514 static int gic_secondary_init(struct notifier_block *nfb,
515 unsigned long action, void *hcpu)
517 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
523 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
524 * priority because the GIC needs to be up before the ARM generic timers.
526 static struct notifier_block gic_cpu_notifier = {
527 .notifier_call = gic_secondary_init,
531 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
532 unsigned long cluster_id)
535 unsigned long mpidr = cpu_logical_map(cpu);
538 while (cpu < nr_cpu_ids) {
540 * If we ever get a cluster of more than 16 CPUs, just
541 * scream and skip that CPU.
543 if (WARN_ON((mpidr & 0xff) >= 16))
546 tlist |= 1 << (mpidr & 0xf);
548 cpu = cpumask_next(cpu, mask);
549 if (cpu >= nr_cpu_ids)
552 mpidr = cpu_logical_map(cpu);
554 if (cluster_id != (mpidr & ~0xffUL)) {
564 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
565 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
566 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
568 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
572 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
573 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
574 irq << ICC_SGI1R_SGI_ID_SHIFT |
575 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
576 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
578 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
579 gic_write_sgi1r(val);
582 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
586 if (WARN_ON(irq >= 16))
590 * Ensure that stores to Normal memory are visible to the
591 * other CPUs before issuing the IPI.
595 for_each_cpu(cpu, mask) {
596 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL;
599 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
600 gic_send_sgi(cluster_id, tlist, irq);
603 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
607 static void gic_smp_init(void)
609 set_smp_cross_call(gic_raise_softirq);
610 register_cpu_notifier(&gic_cpu_notifier);
613 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
616 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
621 if (gic_irq_in_rdist(d))
624 /* If interrupt was enabled, disable it first */
625 enabled = gic_peek_irq(d, GICD_ISENABLER);
629 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
630 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
632 gic_write_irouter(val, reg);
635 * If the interrupt was enabled, enabled it again. Otherwise,
636 * just wait for the distributor to have digested our changes.
641 gic_dist_wait_for_rwp();
643 return IRQ_SET_MASK_OK_DONE;
646 #define gic_set_affinity NULL
647 #define gic_smp_init() do { } while(0)
651 static int gic_cpu_pm_notifier(struct notifier_block *self,
652 unsigned long cmd, void *v)
654 if (cmd == CPU_PM_EXIT) {
655 gic_enable_redist(true);
656 gic_cpu_sys_reg_init();
657 } else if (cmd == CPU_PM_ENTER) {
659 gic_enable_redist(false);
664 static struct notifier_block gic_cpu_pm_notifier_block = {
665 .notifier_call = gic_cpu_pm_notifier,
668 static void gic_cpu_pm_init(void)
670 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
674 static inline void gic_cpu_pm_init(void) { }
675 #endif /* CONFIG_CPU_PM */
677 static struct irq_chip gic_chip = {
679 .irq_mask = gic_mask_irq,
680 .irq_unmask = gic_unmask_irq,
681 .irq_eoi = gic_eoi_irq,
682 .irq_set_type = gic_set_type,
683 .irq_set_affinity = gic_set_affinity,
684 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
685 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
686 .flags = IRQCHIP_SET_TYPE_MASKED,
689 static struct irq_chip gic_eoimode1_chip = {
691 .irq_mask = gic_eoimode1_mask_irq,
692 .irq_unmask = gic_unmask_irq,
693 .irq_eoi = gic_eoimode1_eoi_irq,
694 .irq_set_type = gic_set_type,
695 .irq_set_affinity = gic_set_affinity,
696 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
697 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
698 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
699 .flags = IRQCHIP_SET_TYPE_MASKED,
702 #define GIC_ID_NR (1U << gic_data.rdists.id_bits)
704 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
707 struct irq_chip *chip = &gic_chip;
709 if (static_key_true(&supports_deactivate))
710 chip = &gic_eoimode1_chip;
712 /* SGIs are private to the core kernel */
716 if (hw >= gic_data.irq_nr && hw < 8192)
724 irq_set_percpu_devid(irq);
725 irq_domain_set_info(d, irq, hw, chip, d->host_data,
726 handle_percpu_devid_irq, NULL, NULL);
727 irq_set_status_flags(irq, IRQ_NOAUTOEN);
730 if (hw >= 32 && hw < gic_data.irq_nr) {
731 irq_domain_set_info(d, irq, hw, chip, d->host_data,
732 handle_fasteoi_irq, NULL, NULL);
736 if (hw >= 8192 && hw < GIC_ID_NR) {
737 if (!gic_dist_supports_lpis())
739 irq_domain_set_info(d, irq, hw, chip, d->host_data,
740 handle_fasteoi_irq, NULL, NULL);
746 static int gic_irq_domain_translate(struct irq_domain *d,
747 struct irq_fwspec *fwspec,
748 unsigned long *hwirq,
751 if (is_of_node(fwspec->fwnode)) {
752 if (fwspec->param_count < 3)
755 switch (fwspec->param[0]) {
757 *hwirq = fwspec->param[1] + 32;
760 *hwirq = fwspec->param[1] + 16;
762 case GIC_IRQ_TYPE_LPI: /* LPI */
763 *hwirq = fwspec->param[1];
769 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
773 if (is_fwnode_irqchip(fwspec->fwnode)) {
774 if(fwspec->param_count != 2)
777 *hwirq = fwspec->param[0];
778 *type = fwspec->param[1];
785 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
786 unsigned int nr_irqs, void *arg)
789 irq_hw_number_t hwirq;
790 unsigned int type = IRQ_TYPE_NONE;
791 struct irq_fwspec *fwspec = arg;
793 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
797 for (i = 0; i < nr_irqs; i++)
798 gic_irq_domain_map(domain, virq + i, hwirq + i);
803 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
804 unsigned int nr_irqs)
808 for (i = 0; i < nr_irqs; i++) {
809 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
810 irq_set_handler(virq + i, NULL);
811 irq_domain_reset_irq_data(d);
815 static const struct irq_domain_ops gic_irq_domain_ops = {
816 .translate = gic_irq_domain_translate,
817 .alloc = gic_irq_domain_alloc,
818 .free = gic_irq_domain_free,
821 static void gicv3_enable_quirks(void)
824 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))
825 static_branch_enable(&is_cavium_thunderx);
829 static int __init gic_init_bases(void __iomem *dist_base,
830 struct redist_region *rdist_regs,
831 u32 nr_redist_regions,
833 struct fwnode_handle *handle)
835 struct device_node *node;
840 if (!is_hyp_mode_available())
841 static_key_slow_dec(&supports_deactivate);
843 if (static_key_true(&supports_deactivate))
844 pr_info("GIC: Using split EOI/Deactivate mode\n");
846 gic_data.dist_base = dist_base;
847 gic_data.redist_regions = rdist_regs;
848 gic_data.nr_redist_regions = nr_redist_regions;
849 gic_data.redist_stride = redist_stride;
851 gicv3_enable_quirks();
854 * Find out how many interrupts are supported.
855 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
857 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
858 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
859 gic_irqs = GICD_TYPER_IRQS(typer);
862 gic_data.irq_nr = gic_irqs;
864 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
866 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
868 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
873 set_handle_irq(gic_handle_irq);
875 node = to_of_node(handle);
876 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
877 node) /* Temp hack to prevent ITS init for ACPI */
878 its_init(node, &gic_data.rdists, gic_data.domain);
889 irq_domain_remove(gic_data.domain);
890 free_percpu(gic_data.rdists.rdist);
894 static int __init gic_validate_dist_version(void __iomem *dist_base)
896 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
898 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
904 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
906 void __iomem *dist_base;
907 struct redist_region *rdist_regs;
909 u32 nr_redist_regions;
912 dist_base = of_iomap(node, 0);
914 pr_err("%s: unable to map gic dist registers\n",
919 err = gic_validate_dist_version(dist_base);
921 pr_err("%s: no distributor detected, giving up\n",
926 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
927 nr_redist_regions = 1;
929 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
935 for (i = 0; i < nr_redist_regions; i++) {
939 ret = of_address_to_resource(node, 1 + i, &res);
940 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
941 if (ret || !rdist_regs[i].redist_base) {
942 pr_err("%s: couldn't map region %d\n",
945 goto out_unmap_rdist;
947 rdist_regs[i].phys_base = res.start;
950 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
953 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
954 redist_stride, &node->fwnode);
959 for (i = 0; i < nr_redist_regions; i++)
960 if (rdist_regs[i].redist_base)
961 iounmap(rdist_regs[i].redist_base);
968 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
971 static void __iomem *dist_base;
972 static struct redist_region *redist_regs __initdata;
973 static u32 nr_redist_regions __initdata;
974 static bool single_redist;
977 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
979 static int count = 0;
981 redist_regs[count].phys_base = phys_base;
982 redist_regs[count].redist_base = redist_base;
983 redist_regs[count].single_redist = single_redist;
988 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
989 const unsigned long end)
991 struct acpi_madt_generic_redistributor *redist =
992 (struct acpi_madt_generic_redistributor *)header;
993 void __iomem *redist_base;
995 redist_base = ioremap(redist->base_address, redist->length);
997 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1001 gic_acpi_register_redist(redist->base_address, redist_base);
1006 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
1007 const unsigned long end)
1009 struct acpi_madt_generic_interrupt *gicc =
1010 (struct acpi_madt_generic_interrupt *)header;
1011 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1012 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1013 void __iomem *redist_base;
1015 redist_base = ioremap(gicc->gicr_base_address, size);
1019 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1023 static int __init gic_acpi_collect_gicr_base(void)
1025 acpi_tbl_entry_handler redist_parser;
1026 enum acpi_madt_type type;
1028 if (single_redist) {
1029 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1030 redist_parser = gic_acpi_parse_madt_gicc;
1032 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1033 redist_parser = gic_acpi_parse_madt_redist;
1036 /* Collect redistributor base addresses in GICR entries */
1037 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1040 pr_info("No valid GICR entries exist\n");
1044 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
1045 const unsigned long end)
1047 /* Subtable presence means that redist exists, that's it */
1051 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
1052 const unsigned long end)
1054 struct acpi_madt_generic_interrupt *gicc =
1055 (struct acpi_madt_generic_interrupt *)header;
1058 * If GICC is enabled and has valid gicr base address, then it means
1059 * GICR base is presented via GICC
1061 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1067 static int __init gic_acpi_count_gicr_regions(void)
1072 * Count how many redistributor regions we have. It is not allowed
1073 * to mix redistributor description, GICR and GICC subtables have to be
1074 * mutually exclusive.
1076 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1077 gic_acpi_match_gicr, 0);
1079 single_redist = false;
1083 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1084 gic_acpi_match_gicc, 0);
1086 single_redist = true;
1091 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1092 struct acpi_probe_entry *ape)
1094 struct acpi_madt_generic_distributor *dist;
1097 dist = (struct acpi_madt_generic_distributor *)header;
1098 if (dist->version != ape->driver_data)
1101 /* We need to do that exercise anyway, the sooner the better */
1102 count = gic_acpi_count_gicr_regions();
1106 nr_redist_regions = count;
1110 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1113 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1115 struct acpi_madt_generic_distributor *dist;
1116 struct fwnode_handle *domain_handle;
1119 /* Get distributor base address */
1120 dist = (struct acpi_madt_generic_distributor *)header;
1121 dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE);
1123 pr_err("Unable to map GICD registers\n");
1127 err = gic_validate_dist_version(dist_base);
1129 pr_err("No distributor detected at @%p, giving up", dist_base);
1130 goto out_dist_unmap;
1133 redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions,
1137 goto out_dist_unmap;
1140 err = gic_acpi_collect_gicr_base();
1142 goto out_redist_unmap;
1144 domain_handle = irq_domain_alloc_fwnode(dist_base);
1145 if (!domain_handle) {
1147 goto out_redist_unmap;
1150 err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
1153 goto out_fwhandle_free;
1155 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1159 irq_domain_free_fwnode(domain_handle);
1161 for (i = 0; i < nr_redist_regions; i++)
1162 if (redist_regs[i].redist_base)
1163 iounmap(redist_regs[i].redist_base);
1169 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1170 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1172 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1173 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1175 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1176 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,