2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/err.h>
28 #include <linux/module.h>
29 #include <linux/list.h>
30 #include <linux/smp.h>
31 #include <linux/cpu.h>
32 #include <linux/cpu_pm.h>
33 #include <linux/cpumask.h>
36 #include <linux/of_address.h>
37 #include <linux/of_irq.h>
38 #include <linux/irqdomain.h>
39 #include <linux/interrupt.h>
40 #include <linux/percpu.h>
41 #include <linux/slab.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
45 #include <asm/cputype.h>
47 #include <asm/exception.h>
48 #include <asm/smp_plat.h>
53 void __iomem *common_base;
54 void __percpu * __iomem *percpu_base;
57 struct gic_chip_data {
58 union gic_base dist_base;
59 union gic_base cpu_base;
61 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
62 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
63 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
64 u32 __percpu *saved_ppi_enable;
65 u32 __percpu *saved_ppi_conf;
67 struct irq_domain *domain;
68 unsigned int gic_irqs;
69 #ifdef CONFIG_GIC_NON_BANKED
70 void __iomem *(*get_base)(union gic_base *);
74 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
77 * The GIC mapping of CPU interfaces does not necessarily match
78 * the logical CPU numbering. Let's use a mapping as returned
81 #define NR_GIC_CPU_IF 8
82 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
85 * Supported arch specific GIC irq extension.
86 * Default make them NULL.
88 struct irq_chip gic_arch_extn = {
92 .irq_retrigger = NULL,
101 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
103 #ifdef CONFIG_GIC_NON_BANKED
104 static void __iomem *gic_get_percpu_base(union gic_base *base)
106 return *__this_cpu_ptr(base->percpu_base);
109 static void __iomem *gic_get_common_base(union gic_base *base)
111 return base->common_base;
114 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
116 return data->get_base(&data->dist_base);
119 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
121 return data->get_base(&data->cpu_base);
124 static inline void gic_set_base_accessor(struct gic_chip_data *data,
125 void __iomem *(*f)(union gic_base *))
130 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
131 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
132 #define gic_set_base_accessor(d, f)
135 static inline void __iomem *gic_dist_base(struct irq_data *d)
137 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
138 return gic_data_dist_base(gic_data);
141 static inline void __iomem *gic_cpu_base(struct irq_data *d)
143 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
144 return gic_data_cpu_base(gic_data);
147 static inline unsigned int gic_irq(struct irq_data *d)
153 * Routines to acknowledge, disable and enable interrupts
155 static void gic_mask_irq(struct irq_data *d)
157 u32 mask = 1 << (gic_irq(d) % 32);
159 raw_spin_lock(&irq_controller_lock);
160 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
161 if (gic_arch_extn.irq_mask)
162 gic_arch_extn.irq_mask(d);
163 raw_spin_unlock(&irq_controller_lock);
166 static void gic_unmask_irq(struct irq_data *d)
168 u32 mask = 1 << (gic_irq(d) % 32);
170 raw_spin_lock(&irq_controller_lock);
171 if (gic_arch_extn.irq_unmask)
172 gic_arch_extn.irq_unmask(d);
173 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
174 raw_spin_unlock(&irq_controller_lock);
177 static void gic_eoi_irq(struct irq_data *d)
179 if (gic_arch_extn.irq_eoi) {
180 raw_spin_lock(&irq_controller_lock);
181 gic_arch_extn.irq_eoi(d);
182 raw_spin_unlock(&irq_controller_lock);
185 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
188 static int gic_set_type(struct irq_data *d, unsigned int type)
190 void __iomem *base = gic_dist_base(d);
191 unsigned int gicirq = gic_irq(d);
192 u32 enablemask = 1 << (gicirq % 32);
193 u32 enableoff = (gicirq / 32) * 4;
194 u32 confmask = 0x2 << ((gicirq % 16) * 2);
195 u32 confoff = (gicirq / 16) * 4;
196 bool enabled = false;
199 /* Interrupt configuration for SGIs can't be changed */
203 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
206 raw_spin_lock(&irq_controller_lock);
208 if (gic_arch_extn.irq_set_type)
209 gic_arch_extn.irq_set_type(d, type);
211 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
212 if (type == IRQ_TYPE_LEVEL_HIGH)
214 else if (type == IRQ_TYPE_EDGE_RISING)
218 * As recommended by the spec, disable the interrupt before changing
221 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
222 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
226 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
229 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
231 raw_spin_unlock(&irq_controller_lock);
236 static int gic_retrigger(struct irq_data *d)
238 if (gic_arch_extn.irq_retrigger)
239 return gic_arch_extn.irq_retrigger(d);
241 /* the genirq layer expects 0 if we can't retrigger in hardware */
246 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
249 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
250 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
254 cpu = cpumask_any_and(mask_val, cpu_online_mask);
256 cpu = cpumask_first(mask_val);
258 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
261 raw_spin_lock(&irq_controller_lock);
262 mask = 0xff << shift;
263 bit = gic_cpu_map[cpu] << shift;
264 val = readl_relaxed(reg) & ~mask;
265 writel_relaxed(val | bit, reg);
266 raw_spin_unlock(&irq_controller_lock);
268 return IRQ_SET_MASK_OK;
273 static int gic_set_wake(struct irq_data *d, unsigned int on)
277 if (gic_arch_extn.irq_set_wake)
278 ret = gic_arch_extn.irq_set_wake(d, on);
284 #define gic_set_wake NULL
287 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
290 struct gic_chip_data *gic = &gic_data[0];
291 void __iomem *cpu_base = gic_data_cpu_base(gic);
294 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
295 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
297 if (likely(irqnr > 15 && irqnr < 1021)) {
298 irqnr = irq_find_mapping(gic->domain, irqnr);
299 handle_IRQ(irqnr, regs);
303 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
305 handle_IPI(irqnr, regs);
313 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
315 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
316 struct irq_chip *chip = irq_get_chip(irq);
317 unsigned int cascade_irq, gic_irq;
318 unsigned long status;
320 chained_irq_enter(chip, desc);
322 raw_spin_lock(&irq_controller_lock);
323 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
324 raw_spin_unlock(&irq_controller_lock);
326 gic_irq = (status & 0x3ff);
330 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
331 if (unlikely(gic_irq < 32 || gic_irq > 1020))
332 handle_bad_irq(cascade_irq, desc);
334 generic_handle_irq(cascade_irq);
337 chained_irq_exit(chip, desc);
340 static struct irq_chip gic_chip = {
342 .irq_mask = gic_mask_irq,
343 .irq_unmask = gic_unmask_irq,
344 .irq_eoi = gic_eoi_irq,
345 .irq_set_type = gic_set_type,
346 .irq_retrigger = gic_retrigger,
348 .irq_set_affinity = gic_set_affinity,
350 .irq_set_wake = gic_set_wake,
353 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
355 if (gic_nr >= MAX_GIC_NR)
357 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
359 irq_set_chained_handler(irq, gic_handle_cascade_irq);
362 static u8 gic_get_cpumask(struct gic_chip_data *gic)
364 void __iomem *base = gic_data_dist_base(gic);
367 for (i = mask = 0; i < 32; i += 4) {
368 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
376 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
381 static void __init gic_dist_init(struct gic_chip_data *gic)
385 unsigned int gic_irqs = gic->gic_irqs;
386 void __iomem *base = gic_data_dist_base(gic);
388 writel_relaxed(0, base + GIC_DIST_CTRL);
391 * Set all global interrupts to be level triggered, active low.
393 for (i = 32; i < gic_irqs; i += 16)
394 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
397 * Set all global interrupts to this CPU only.
399 cpumask = gic_get_cpumask(gic);
400 cpumask |= cpumask << 8;
401 cpumask |= cpumask << 16;
402 for (i = 32; i < gic_irqs; i += 4)
403 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
406 * Set priority on all global interrupts.
408 for (i = 32; i < gic_irqs; i += 4)
409 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
412 * Disable all interrupts. Leave the PPI and SGIs alone
413 * as these enables are banked registers.
415 for (i = 32; i < gic_irqs; i += 32)
416 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
418 writel_relaxed(1, base + GIC_DIST_CTRL);
421 static void gic_cpu_init(struct gic_chip_data *gic)
423 void __iomem *dist_base = gic_data_dist_base(gic);
424 void __iomem *base = gic_data_cpu_base(gic);
425 unsigned int cpu_mask, cpu = smp_processor_id();
429 * Get what the GIC says our CPU mask is.
431 BUG_ON(cpu >= NR_GIC_CPU_IF);
432 cpu_mask = gic_get_cpumask(gic);
433 gic_cpu_map[cpu] = cpu_mask;
436 * Clear our mask from the other map entries in case they're
439 for (i = 0; i < NR_GIC_CPU_IF; i++)
441 gic_cpu_map[i] &= ~cpu_mask;
444 * Deal with the banked PPI and SGI interrupts - disable all
445 * PPI interrupts, ensure all SGI interrupts are enabled.
447 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
448 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
451 * Set priority on PPI and SGI interrupts
453 for (i = 0; i < 32; i += 4)
454 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
456 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
457 writel_relaxed(1, base + GIC_CPU_CTRL);
460 void gic_cpu_if_down(void)
462 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
463 writel_relaxed(0, cpu_base + GIC_CPU_CTRL);
468 * Saves the GIC distributor registers during suspend or idle. Must be called
469 * with interrupts disabled but before powering down the GIC. After calling
470 * this function, no interrupts will be delivered by the GIC, and another
471 * platform-specific wakeup source must be enabled.
473 static void gic_dist_save(unsigned int gic_nr)
475 unsigned int gic_irqs;
476 void __iomem *dist_base;
479 if (gic_nr >= MAX_GIC_NR)
482 gic_irqs = gic_data[gic_nr].gic_irqs;
483 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
488 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
489 gic_data[gic_nr].saved_spi_conf[i] =
490 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
492 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
493 gic_data[gic_nr].saved_spi_target[i] =
494 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
496 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
497 gic_data[gic_nr].saved_spi_enable[i] =
498 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
502 * Restores the GIC distributor registers during resume or when coming out of
503 * idle. Must be called before enabling interrupts. If a level interrupt
504 * that occured while the GIC was suspended is still present, it will be
505 * handled normally, but any edge interrupts that occured will not be seen by
506 * the GIC and need to be handled by the platform-specific wakeup source.
508 static void gic_dist_restore(unsigned int gic_nr)
510 unsigned int gic_irqs;
512 void __iomem *dist_base;
514 if (gic_nr >= MAX_GIC_NR)
517 gic_irqs = gic_data[gic_nr].gic_irqs;
518 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
523 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
525 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
526 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
527 dist_base + GIC_DIST_CONFIG + i * 4);
529 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
530 writel_relaxed(0xa0a0a0a0,
531 dist_base + GIC_DIST_PRI + i * 4);
533 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
534 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
535 dist_base + GIC_DIST_TARGET + i * 4);
537 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
538 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
539 dist_base + GIC_DIST_ENABLE_SET + i * 4);
541 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
544 static void gic_cpu_save(unsigned int gic_nr)
548 void __iomem *dist_base;
549 void __iomem *cpu_base;
551 if (gic_nr >= MAX_GIC_NR)
554 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
555 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
557 if (!dist_base || !cpu_base)
560 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
561 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
562 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
564 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
565 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
566 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
570 static void gic_cpu_restore(unsigned int gic_nr)
574 void __iomem *dist_base;
575 void __iomem *cpu_base;
577 if (gic_nr >= MAX_GIC_NR)
580 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
581 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
583 if (!dist_base || !cpu_base)
586 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
587 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
588 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
590 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
591 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
592 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
594 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
595 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
597 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
598 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
601 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
605 for (i = 0; i < MAX_GIC_NR; i++) {
606 #ifdef CONFIG_GIC_NON_BANKED
607 /* Skip over unused GICs */
608 if (!gic_data[i].get_base)
615 case CPU_PM_ENTER_FAILED:
619 case CPU_CLUSTER_PM_ENTER:
622 case CPU_CLUSTER_PM_ENTER_FAILED:
623 case CPU_CLUSTER_PM_EXIT:
632 static struct notifier_block gic_notifier_block = {
633 .notifier_call = gic_notifier,
636 static void __init gic_pm_init(struct gic_chip_data *gic)
638 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
640 BUG_ON(!gic->saved_ppi_enable);
642 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
644 BUG_ON(!gic->saved_ppi_conf);
646 if (gic == &gic_data[0])
647 cpu_pm_register_notifier(&gic_notifier_block);
650 static void __init gic_pm_init(struct gic_chip_data *gic)
656 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
659 unsigned long flags, map = 0;
661 raw_spin_lock_irqsave(&irq_controller_lock, flags);
663 /* Convert our logical CPU mask into a physical one. */
664 for_each_cpu(cpu, mask)
665 map |= gic_cpu_map[cpu];
668 * Ensure that stores to Normal memory are visible to the
669 * other CPUs before they observe us issuing the IPI.
673 /* this always happens on GIC0 */
674 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
676 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
680 #ifdef CONFIG_BL_SWITCHER
682 * gic_send_sgi - send a SGI directly to given CPU interface number
684 * cpu_id: the ID for the destination CPU interface
685 * irq: the IPI number to send a SGI for
687 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
689 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
690 cpu_id = 1 << cpu_id;
691 /* this always happens on GIC0 */
692 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
696 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
698 * @cpu: the logical CPU number to get the GIC ID for.
700 * Return the CPU interface ID for the given logical CPU number,
701 * or -1 if the CPU number is too large or the interface ID is
702 * unknown (more than one bit set).
704 int gic_get_cpu_id(unsigned int cpu)
706 unsigned int cpu_bit;
708 if (cpu >= NR_GIC_CPU_IF)
710 cpu_bit = gic_cpu_map[cpu];
711 if (cpu_bit & (cpu_bit - 1))
713 return __ffs(cpu_bit);
717 * gic_migrate_target - migrate IRQs to another CPU interface
719 * @new_cpu_id: the CPU target ID to migrate IRQs to
721 * Migrate all peripheral interrupts with a target matching the current CPU
722 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
723 * is also updated. Targets to other CPU interfaces are unchanged.
724 * This must be called with IRQs locally disabled.
726 void gic_migrate_target(unsigned int new_cpu_id)
728 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
729 void __iomem *dist_base;
730 int i, ror_val, cpu = smp_processor_id();
731 u32 val, cur_target_mask, active_mask;
733 if (gic_nr >= MAX_GIC_NR)
736 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
739 gic_irqs = gic_data[gic_nr].gic_irqs;
741 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
742 cur_target_mask = 0x01010101 << cur_cpu_id;
743 ror_val = (cur_cpu_id - new_cpu_id) & 31;
745 raw_spin_lock(&irq_controller_lock);
747 /* Update the target interface for this logical CPU */
748 gic_cpu_map[cpu] = 1 << new_cpu_id;
751 * Find all the peripheral interrupts targetting the current
752 * CPU interface and migrate them to the new CPU interface.
753 * We skip DIST_TARGET 0 to 7 as they are read-only.
755 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
756 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
757 active_mask = val & cur_target_mask;
760 val |= ror32(active_mask, ror_val);
761 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
765 raw_spin_unlock(&irq_controller_lock);
768 * Now let's migrate and clear any potential SGIs that might be
769 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
770 * is a banked register, we can only forward the SGI using
771 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
772 * doesn't use that information anyway.
774 * For the same reason we do not adjust SGI source information
775 * for previously sent SGIs by us to other CPUs either.
777 for (i = 0; i < 16; i += 4) {
779 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
782 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
783 for (j = i; j < i + 4; j++) {
785 writel_relaxed((1 << (new_cpu_id + 16)) | j,
786 dist_base + GIC_DIST_SOFTINT);
793 * gic_get_sgir_physaddr - get the physical address for the SGI register
795 * REturn the physical address of the SGI register to be used
796 * by some early assembly code when the kernel is not yet available.
798 static unsigned long gic_dist_physaddr;
800 unsigned long gic_get_sgir_physaddr(void)
802 if (!gic_dist_physaddr)
804 return gic_dist_physaddr + GIC_DIST_SOFTINT;
807 void __init gic_init_physaddr(struct device_node *node)
810 if (of_address_to_resource(node, 0, &res) == 0) {
811 gic_dist_physaddr = res.start;
812 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
817 #define gic_init_physaddr(node) do { } while (0)
820 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
824 irq_set_percpu_devid(irq);
825 irq_set_chip_and_handler(irq, &gic_chip,
826 handle_percpu_devid_irq);
827 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
829 irq_set_chip_and_handler(irq, &gic_chip,
831 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
833 gic_routable_irq_domain_ops->map(d, irq, hw);
835 irq_set_chip_data(irq, d->host_data);
839 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
841 gic_routable_irq_domain_ops->unmap(d, irq);
844 static int gic_irq_domain_xlate(struct irq_domain *d,
845 struct device_node *controller,
846 const u32 *intspec, unsigned int intsize,
847 unsigned long *out_hwirq, unsigned int *out_type)
849 unsigned long ret = 0;
851 if (d->of_node != controller)
856 /* Get the interrupt number and add 16 to skip over SGIs */
857 *out_hwirq = intspec[1] + 16;
859 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
861 ret = gic_routable_irq_domain_ops->xlate(d, controller,
867 if (IS_ERR_VALUE(ret))
871 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
877 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
880 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
881 gic_cpu_init(&gic_data[0]);
886 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
887 * priority because the GIC needs to be up before the ARM generic timers.
889 static struct notifier_block gic_cpu_notifier = {
890 .notifier_call = gic_secondary_init,
895 static const struct irq_domain_ops gic_irq_domain_ops = {
896 .map = gic_irq_domain_map,
897 .unmap = gic_irq_domain_unmap,
898 .xlate = gic_irq_domain_xlate,
901 /* Default functions for routable irq domain */
902 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
908 static void gic_routable_irq_domain_unmap(struct irq_domain *d,
913 static int gic_routable_irq_domain_xlate(struct irq_domain *d,
914 struct device_node *controller,
915 const u32 *intspec, unsigned int intsize,
916 unsigned long *out_hwirq,
917 unsigned int *out_type)
923 const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
924 .map = gic_routable_irq_domain_map,
925 .unmap = gic_routable_irq_domain_unmap,
926 .xlate = gic_routable_irq_domain_xlate,
929 const struct irq_domain_ops *gic_routable_irq_domain_ops =
930 &gic_default_routable_irq_domain_ops;
932 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
933 void __iomem *dist_base, void __iomem *cpu_base,
934 u32 percpu_offset, struct device_node *node)
936 irq_hw_number_t hwirq_base;
937 struct gic_chip_data *gic;
938 int gic_irqs, irq_base, i;
939 int nr_routable_irqs;
941 BUG_ON(gic_nr >= MAX_GIC_NR);
943 gic = &gic_data[gic_nr];
944 #ifdef CONFIG_GIC_NON_BANKED
945 if (percpu_offset) { /* Frankein-GIC without banked registers... */
948 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
949 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
950 if (WARN_ON(!gic->dist_base.percpu_base ||
951 !gic->cpu_base.percpu_base)) {
952 free_percpu(gic->dist_base.percpu_base);
953 free_percpu(gic->cpu_base.percpu_base);
957 for_each_possible_cpu(cpu) {
958 u32 mpidr = cpu_logical_map(cpu);
959 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
960 unsigned long offset = percpu_offset * core_id;
961 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
962 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
965 gic_set_base_accessor(gic, gic_get_percpu_base);
968 { /* Normal, sane GIC... */
970 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
972 gic->dist_base.common_base = dist_base;
973 gic->cpu_base.common_base = cpu_base;
974 gic_set_base_accessor(gic, gic_get_common_base);
978 * Initialize the CPU interface map to all CPUs.
979 * It will be refined as each CPU probes its ID.
981 for (i = 0; i < NR_GIC_CPU_IF; i++)
982 gic_cpu_map[i] = 0xff;
985 * For primary GICs, skip over SGIs.
986 * For secondary GICs, skip over PPIs, too.
988 if (gic_nr == 0 && (irq_start & 31) > 0) {
991 irq_start = (irq_start & ~31) + 16;
997 * Find out how many interrupts are supported.
998 * The GIC only supports up to 1020 interrupt sources.
1000 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1001 gic_irqs = (gic_irqs + 1) * 32;
1002 if (gic_irqs > 1020)
1004 gic->gic_irqs = gic_irqs;
1006 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1008 if (of_property_read_u32(node, "arm,routable-irqs",
1009 &nr_routable_irqs)) {
1010 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1012 if (IS_ERR_VALUE(irq_base)) {
1013 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1015 irq_base = irq_start;
1018 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
1019 hwirq_base, &gic_irq_domain_ops, gic);
1021 gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
1022 &gic_irq_domain_ops,
1026 if (WARN_ON(!gic->domain))
1031 set_smp_cross_call(gic_raise_softirq);
1032 register_cpu_notifier(&gic_cpu_notifier);
1034 set_handle_irq(gic_handle_irq);
1037 gic_chip.flags |= gic_arch_extn.flags;
1044 static int gic_cnt __initdata;
1047 gic_of_init(struct device_node *node, struct device_node *parent)
1049 void __iomem *cpu_base;
1050 void __iomem *dist_base;
1057 dist_base = of_iomap(node, 0);
1058 WARN(!dist_base, "unable to map gic dist registers\n");
1060 cpu_base = of_iomap(node, 1);
1061 WARN(!cpu_base, "unable to map gic cpu registers\n");
1063 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1066 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1068 gic_init_physaddr(node);
1071 irq = irq_of_parse_and_map(node, 0);
1072 gic_cascade_irq(gic_cnt, irq);
1077 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1078 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1079 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1080 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1081 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1082 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);