2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Code to handle x86 style IRQs plus some generic interrupt stuff.
8 * Copyright (C) 1992 Linus Torvalds
9 * Copyright (C) 1994 - 2000 Ralf Baechle
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip.h>
16 #include <linux/irqdomain.h>
17 #include <linux/kernel.h>
18 #include <linux/of_irq.h>
19 #include <linux/spinlock.h>
20 #include <linux/syscore_ops.h>
21 #include <linux/irq.h>
23 #include <asm/i8259.h>
27 * This is the 'legacy' 8259A Programmable Interrupt Controller,
28 * present in the majority of PC/AT boxes.
29 * plus some generic x86 specific things if generic specifics makes
31 * this file should become arch/i386/kernel/irq.c when the old irq.c
32 * moves to arch independent land
35 static int i8259A_auto_eoi = -1;
36 DEFINE_RAW_SPINLOCK(i8259A_lock);
37 static void disable_8259A_irq(struct irq_data *d);
38 static void enable_8259A_irq(struct irq_data *d);
39 static void mask_and_ack_8259A(struct irq_data *d);
40 static void init_8259A(int auto_eoi);
41 static int (*i8259_poll)(void) = i8259_irq;
43 static struct irq_chip i8259A_chip = {
45 .irq_mask = disable_8259A_irq,
46 .irq_disable = disable_8259A_irq,
47 .irq_unmask = enable_8259A_irq,
48 .irq_mask_ack = mask_and_ack_8259A,
52 * 8259A PIC functions to handle ISA devices:
55 void i8259_set_poll(int (*poll)(void))
61 * This contains the irq mask for both 8259A irq controllers,
63 static unsigned int cached_irq_mask = 0xffff;
65 #define cached_master_mask (cached_irq_mask)
66 #define cached_slave_mask (cached_irq_mask >> 8)
68 static void disable_8259A_irq(struct irq_data *d)
70 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
74 raw_spin_lock_irqsave(&i8259A_lock, flags);
75 cached_irq_mask |= mask;
77 outb(cached_slave_mask, PIC_SLAVE_IMR);
79 outb(cached_master_mask, PIC_MASTER_IMR);
80 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
83 static void enable_8259A_irq(struct irq_data *d)
85 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
89 raw_spin_lock_irqsave(&i8259A_lock, flags);
90 cached_irq_mask &= mask;
92 outb(cached_slave_mask, PIC_SLAVE_IMR);
94 outb(cached_master_mask, PIC_MASTER_IMR);
95 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
98 int i8259A_irq_pending(unsigned int irq)
104 irq -= I8259A_IRQ_BASE;
106 raw_spin_lock_irqsave(&i8259A_lock, flags);
108 ret = inb(PIC_MASTER_CMD) & mask;
110 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
111 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
116 void make_8259A_irq(unsigned int irq)
118 disable_irq_nosync(irq);
119 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
124 * This function assumes to be called rarely. Switching between
125 * 8259A registers is slow.
126 * This has to be protected by the irq controller spinlock
127 * before being called.
129 static inline int i8259A_irq_real(unsigned int irq)
132 int irqmask = 1 << irq;
135 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
136 value = inb(PIC_MASTER_CMD) & irqmask;
137 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
140 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
141 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
142 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
147 * Careful! The 8259A is a fragile beast, it pretty
148 * much _has_ to be done exactly like this (mask it
149 * first, _then_ send the EOI, and the order of EOI
150 * to the two 8259s is important!
152 static void mask_and_ack_8259A(struct irq_data *d)
154 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
158 raw_spin_lock_irqsave(&i8259A_lock, flags);
160 * Lightweight spurious IRQ detection. We do not want
161 * to overdo spurious IRQ handling - it's usually a sign
162 * of hardware problems, so we only do the checks we can
163 * do without slowing down good hardware unnecessarily.
165 * Note that IRQ7 and IRQ15 (the two spurious IRQs
166 * usually resulting from the 8259A-1|2 PICs) occur
167 * even if the IRQ is masked in the 8259A. Thus we
168 * can check spurious 8259A IRQs without doing the
169 * quite slow i8259A_irq_real() call for every IRQ.
170 * This does not cover 100% of spurious interrupts,
171 * but should be enough to warn the user that there
172 * is something bad going on ...
174 if (cached_irq_mask & irqmask)
175 goto spurious_8259A_irq;
176 cached_irq_mask |= irqmask;
180 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
181 outb(cached_slave_mask, PIC_SLAVE_IMR);
182 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
183 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
185 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
186 outb(cached_master_mask, PIC_MASTER_IMR);
187 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
189 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
194 * this is the slow path - should happen rarely.
196 if (i8259A_irq_real(irq))
198 * oops, the IRQ _is_ in service according to the
199 * 8259A - not spurious, go handle it.
201 goto handle_real_irq;
204 static int spurious_irq_mask;
206 * At this point we can be sure the IRQ is spurious,
207 * lets ACK and report it. [once per IRQ]
209 if (!(spurious_irq_mask & irqmask)) {
210 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
211 spurious_irq_mask |= irqmask;
213 atomic_inc(&irq_err_count);
215 * Theoretically we do not have to handle this IRQ,
216 * but in Linux this does not cause problems and is
219 goto handle_real_irq;
223 static void i8259A_resume(void)
225 if (i8259A_auto_eoi >= 0)
226 init_8259A(i8259A_auto_eoi);
229 static void i8259A_shutdown(void)
231 /* Put the i8259A into a quiescent state that
232 * the kernel initialization code can get it
235 if (i8259A_auto_eoi >= 0) {
236 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
237 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
241 static struct syscore_ops i8259_syscore_ops = {
242 .resume = i8259A_resume,
243 .shutdown = i8259A_shutdown,
246 static int __init i8259A_init_sysfs(void)
248 register_syscore_ops(&i8259_syscore_ops);
252 device_initcall(i8259A_init_sysfs);
254 static void init_8259A(int auto_eoi)
258 i8259A_auto_eoi = auto_eoi;
260 raw_spin_lock_irqsave(&i8259A_lock, flags);
262 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
263 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
266 * outb_p - this has to work on a wide range of PC hardware.
268 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
269 outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
270 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
271 if (auto_eoi) /* master does Auto EOI */
272 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
273 else /* master expects normal EOI */
274 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
276 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
277 outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
278 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
279 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
282 * In AEOI mode we just have to mask the interrupt
285 i8259A_chip.irq_mask_ack = disable_8259A_irq;
287 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
289 udelay(100); /* wait for 8259A to initialize */
291 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
292 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
294 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
298 * IRQ2 is cascade interrupt to second interrupt controller
300 static struct irqaction irq2 = {
301 .handler = no_action,
303 .flags = IRQF_NO_THREAD,
306 static struct resource pic1_io_resource = {
308 .start = PIC_MASTER_CMD,
309 .end = PIC_MASTER_IMR,
310 .flags = IORESOURCE_BUSY
313 static struct resource pic2_io_resource = {
315 .start = PIC_SLAVE_CMD,
316 .end = PIC_SLAVE_IMR,
317 .flags = IORESOURCE_BUSY
320 static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq,
323 irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq);
328 static struct irq_domain_ops i8259A_ops = {
329 .map = i8259A_irq_domain_map,
330 .xlate = irq_domain_xlate_onecell,
334 * On systems with i8259-style interrupt controllers we assume for
335 * driver compatibility reasons interrupts 0 - 15 to be the i8259
336 * interrupts even if the hardware uses a different interrupt numbering.
338 struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
340 struct irq_domain *domain;
342 insert_resource(&ioport_resource, &pic1_io_resource);
343 insert_resource(&ioport_resource, &pic2_io_resource);
347 domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0,
350 panic("Failed to add i8259 IRQ domain");
352 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
356 void __init init_i8259_irqs(void)
358 __init_i8259_irqs(NULL);
361 static void i8259_irq_dispatch(struct irq_desc *desc)
363 struct irq_domain *domain = irq_desc_get_handler_data(desc);
364 int hwirq = i8259_poll();
370 irq = irq_linear_revmap(domain, hwirq);
371 generic_handle_irq(irq);
374 int __init i8259_of_init(struct device_node *node, struct device_node *parent)
376 struct irq_domain *domain;
377 unsigned int parent_irq;
379 domain = __init_i8259_irqs(node);
381 parent_irq = irq_of_parse_and_map(node, 0);
383 pr_err("Failed to map i8259 parent IRQ\n");
384 irq_domain_remove(domain);
388 irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
392 IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);