4 * Copyright (C) 2013 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/clk.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/err.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <linux/pm_runtime.h>
34 #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
36 #define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
37 #define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
38 #define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
39 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
40 /* SYS-CPU vs. RT-CPU */
41 #define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
42 #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
43 #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
44 #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
45 #define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
46 #define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
47 #define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
48 #define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
49 #define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
50 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
51 /* IRQn Configuration Register */
61 void __iomem *cpu_int_base;
62 struct irqc_irq irq[IRQC_IRQ_MAX];
63 unsigned int number_of_irqs;
64 struct platform_device *pdev;
65 struct irq_chip irq_chip;
66 struct irq_domain *irq_domain;
70 static void irqc_dbg(struct irqc_irq *i, char *str)
72 dev_dbg(&i->p->pdev->dev, "%s (%d:%d)\n",
73 str, i->requested_irq, i->hw_irq);
76 static void irqc_irq_enable(struct irq_data *d)
78 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
79 int hw_irq = irqd_to_hwirq(d);
81 irqc_dbg(&p->irq[hw_irq], "enable");
82 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
85 static void irqc_irq_disable(struct irq_data *d)
87 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
88 int hw_irq = irqd_to_hwirq(d);
90 irqc_dbg(&p->irq[hw_irq], "disable");
91 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
94 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
95 [IRQ_TYPE_LEVEL_LOW] = 0x01,
96 [IRQ_TYPE_LEVEL_HIGH] = 0x02,
97 [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
98 [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
99 [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
102 static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
104 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
105 int hw_irq = irqd_to_hwirq(d);
106 unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
109 irqc_dbg(&p->irq[hw_irq], "sense");
114 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
117 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
121 static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
123 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
124 int hw_irq = irqd_to_hwirq(d);
126 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
139 static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
141 struct irqc_irq *i = dev_id;
142 struct irqc_priv *p = i->p;
143 u32 bit = BIT(i->hw_irq);
145 irqc_dbg(i, "demux1");
147 if (ioread32(p->iomem + DETECT_STATUS) & bit) {
148 iowrite32(bit, p->iomem + DETECT_STATUS);
149 irqc_dbg(i, "demux2");
150 generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
157 * This lock class tells lockdep that IRQC irqs are in a different
158 * category than their parents, so it won't report false recursion.
160 static struct lock_class_key irqc_irq_lock_class;
162 static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
165 struct irqc_priv *p = h->host_data;
167 irqc_dbg(&p->irq[hw], "map");
168 irq_set_chip_data(virq, h->host_data);
169 irq_set_lockdep_class(virq, &irqc_irq_lock_class);
170 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
174 static const struct irq_domain_ops irqc_irq_domain_ops = {
175 .map = irqc_irq_domain_map,
176 .xlate = irq_domain_xlate_twocell,
179 static int irqc_probe(struct platform_device *pdev)
183 struct resource *irq;
184 struct irq_chip *irq_chip;
185 const char *name = dev_name(&pdev->dev);
189 p = kzalloc(sizeof(*p), GFP_KERNEL);
191 dev_err(&pdev->dev, "failed to allocate driver data\n");
197 platform_set_drvdata(pdev, p);
199 p->clk = devm_clk_get(&pdev->dev, NULL);
200 if (IS_ERR(p->clk)) {
201 dev_warn(&pdev->dev, "unable to get clock\n");
205 pm_runtime_enable(&pdev->dev);
206 pm_runtime_get_sync(&pdev->dev);
208 /* get hold of manadatory IOMEM */
209 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
211 dev_err(&pdev->dev, "not enough IOMEM resources\n");
216 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
217 for (k = 0; k < IRQC_IRQ_MAX; k++) {
218 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
223 p->irq[k].hw_irq = k;
224 p->irq[k].requested_irq = irq->start;
227 p->number_of_irqs = k;
228 if (p->number_of_irqs < 1) {
229 dev_err(&pdev->dev, "not enough IRQ resources\n");
234 /* ioremap IOMEM and setup read/write callbacks */
235 p->iomem = ioremap_nocache(io->start, resource_size(io));
237 dev_err(&pdev->dev, "failed to remap IOMEM\n");
242 p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
244 irq_chip = &p->irq_chip;
245 irq_chip->name = name;
246 irq_chip->irq_mask = irqc_irq_disable;
247 irq_chip->irq_unmask = irqc_irq_enable;
248 irq_chip->irq_set_type = irqc_irq_set_type;
249 irq_chip->irq_set_wake = irqc_irq_set_wake;
250 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
252 p->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
254 &irqc_irq_domain_ops, p);
255 if (!p->irq_domain) {
257 dev_err(&pdev->dev, "cannot initialize irq domain\n");
261 /* request interrupts one by one */
262 for (k = 0; k < p->number_of_irqs; k++) {
263 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
264 0, name, &p->irq[k])) {
265 dev_err(&pdev->dev, "failed to request IRQ\n");
271 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
276 free_irq(p->irq[k].requested_irq, &p->irq[k]);
278 irq_domain_remove(p->irq_domain);
282 pm_runtime_put(&pdev->dev);
283 pm_runtime_disable(&pdev->dev);
289 static int irqc_remove(struct platform_device *pdev)
291 struct irqc_priv *p = platform_get_drvdata(pdev);
294 for (k = 0; k < p->number_of_irqs; k++)
295 free_irq(p->irq[k].requested_irq, &p->irq[k]);
297 irq_domain_remove(p->irq_domain);
299 pm_runtime_put(&pdev->dev);
300 pm_runtime_disable(&pdev->dev);
305 static const struct of_device_id irqc_dt_ids[] = {
306 { .compatible = "renesas,irqc", },
309 MODULE_DEVICE_TABLE(of, irqc_dt_ids);
311 static struct platform_driver irqc_device_driver = {
313 .remove = irqc_remove,
315 .name = "renesas_irqc",
316 .of_match_table = irqc_dt_ids,
320 static int __init irqc_init(void)
322 return platform_driver_register(&irqc_device_driver);
324 postcore_initcall(irqc_init);
326 static void __exit irqc_exit(void)
328 platform_driver_unregister(&irqc_device_driver);
330 module_exit(irqc_exit);
332 MODULE_AUTHOR("Magnus Damm");
333 MODULE_DESCRIPTION("Renesas IRQC Driver");
334 MODULE_LICENSE("GPL v2");