2 * isac.c ISAC specific routines
4 * Author Karsten Keil <keil@isdn4linux.de>
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/irqreturn.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/mISDNhw.h>
30 #define DBUSY_TIMER_VALUE 80
33 #define ISAC_REV "2.0"
35 MODULE_AUTHOR("Karsten Keil");
36 MODULE_VERSION(ISAC_REV);
37 MODULE_LICENSE("GPL v2");
39 #define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off))
40 #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
41 #define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o))
42 #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
43 #define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o))
44 #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
47 ph_command(struct isac_hw *isac, u8 command)
49 pr_debug("%s: ph_command %x\n", isac->name, command);
50 if (isac->type & IPAC_TYPE_ISACX)
51 WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE);
53 WriteISAC(isac, ISAC_CIX0, (command << 2) | 3);
57 isac_ph_state_change(struct isac_hw *isac)
59 switch (isac->state) {
62 ph_command(isac, ISAC_CMD_DUI);
64 schedule_event(&isac->dch, FLG_PHCHANGE);
68 isac_ph_state_bh(struct dchannel *dch)
70 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
72 switch (isac->state) {
76 l1_event(dch->l1, HW_RESET_IND);
80 l1_event(dch->l1, HW_DEACT_CNF);
84 l1_event(dch->l1, HW_DEACT_IND);
88 l1_event(dch->l1, HW_POWERUP_IND);
91 if (dch->state <= 5) {
93 l1_event(dch->l1, ANYSIGNAL);
96 l1_event(dch->l1, LOSTFRAMING);
101 l1_event(dch->l1, INFO2);
105 l1_event(dch->l1, INFO4_P8);
109 l1_event(dch->l1, INFO4_P10);
112 pr_debug("%s: TE newstate %x\n", isac->name, dch->state);
116 isac_empty_fifo(struct isac_hw *isac, int count)
120 pr_debug("%s: %s %d\n", isac->name, __func__, count);
122 if (!isac->dch.rx_skb) {
123 isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC);
124 if (!isac->dch.rx_skb) {
125 pr_info("%s: D receive out of memory\n", isac->name);
126 WriteISAC(isac, ISAC_CMDR, 0x80);
130 if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) {
131 pr_debug("%s: %s overrun %d\n", isac->name, __func__,
132 isac->dch.rx_skb->len + count);
133 WriteISAC(isac, ISAC_CMDR, 0x80);
136 ptr = skb_put(isac->dch.rx_skb, count);
137 isac->read_fifo(isac->dch.hw, isac->off, ptr, count);
138 WriteISAC(isac, ISAC_CMDR, 0x80);
139 if (isac->dch.debug & DEBUG_HW_DFIFO) {
140 char pfx[MISDN_MAX_IDLEN + 16];
142 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ",
144 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
149 isac_fill_fifo(struct isac_hw *isac)
154 if (!isac->dch.tx_skb)
156 count = isac->dch.tx_skb->len - isac->dch.tx_idx;
165 pr_debug("%s: %s %d\n", isac->name, __func__, count);
166 ptr = isac->dch.tx_skb->data + isac->dch.tx_idx;
167 isac->dch.tx_idx += count;
168 isac->write_fifo(isac->dch.hw, isac->off, ptr, count);
169 WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa);
170 if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
171 pr_debug("%s: %s dbusytimer running\n", isac->name, __func__);
172 del_timer(&isac->dch.timer);
174 init_timer(&isac->dch.timer);
175 isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
176 add_timer(&isac->dch.timer);
177 if (isac->dch.debug & DEBUG_HW_DFIFO) {
178 char pfx[MISDN_MAX_IDLEN + 16];
180 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ",
182 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
187 isac_rme_irq(struct isac_hw *isac)
191 val = ReadISAC(isac, ISAC_RSTA);
192 if ((val & 0x70) != 0x20) {
194 pr_debug("%s: ISAC RDO\n", isac->name);
195 #ifdef ERROR_STATISTIC
200 pr_debug("%s: ISAC CRC error\n", isac->name);
201 #ifdef ERROR_STATISTIC
205 WriteISAC(isac, ISAC_CMDR, 0x80);
206 if (isac->dch.rx_skb)
207 dev_kfree_skb(isac->dch.rx_skb);
208 isac->dch.rx_skb = NULL;
210 count = ReadISAC(isac, ISAC_RBCL) & 0x1f;
213 isac_empty_fifo(isac, count);
214 recv_Dchannel(&isac->dch);
219 isac_xpr_irq(struct isac_hw *isac)
221 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
222 del_timer(&isac->dch.timer);
223 if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) {
224 isac_fill_fifo(isac);
226 if (isac->dch.tx_skb)
227 dev_kfree_skb(isac->dch.tx_skb);
228 if (get_next_dframe(&isac->dch))
229 isac_fill_fifo(isac);
234 isac_retransmit(struct isac_hw *isac)
236 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
237 del_timer(&isac->dch.timer);
238 if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) {
240 isac->dch.tx_idx = 0;
241 isac_fill_fifo(isac);
242 } else if (isac->dch.tx_skb) { /* should not happen */
243 pr_info("%s: tx_skb exist but not busy\n", isac->name);
244 test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags);
245 isac->dch.tx_idx = 0;
246 isac_fill_fifo(isac);
248 pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name);
249 if (get_next_dframe(&isac->dch))
250 isac_fill_fifo(isac);
255 isac_mos_irq(struct isac_hw *isac)
260 val = ReadISAC(isac, ISAC_MOSR);
261 pr_debug("%s: ISAC MOSR %02x\n", isac->name, val);
265 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
267 pr_info("%s: ISAC MON RX out of memory!\n",
271 WriteISAC(isac, ISAC_MOCR, isac->mocr);
276 if (isac->mon_rxp >= MAX_MON_FRAME) {
279 WriteISAC(isac, ISAC_MOCR, isac->mocr);
281 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
284 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0);
285 pr_debug("%s: ISAC MOR0 %02x\n", isac->name,
286 isac->mon_rx[isac->mon_rxp - 1]);
287 if (isac->mon_rxp == 1) {
289 WriteISAC(isac, ISAC_MOCR, isac->mocr);
295 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
297 pr_info("%s: ISAC MON RX out of memory!\n",
301 WriteISAC(isac, ISAC_MOCR, isac->mocr);
306 if (isac->mon_rxp >= MAX_MON_FRAME) {
309 WriteISAC(isac, ISAC_MOCR, isac->mocr);
311 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
314 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1);
315 pr_debug("%s: ISAC MOR1 %02x\n", isac->name,
316 isac->mon_rx[isac->mon_rxp - 1]);
318 WriteISAC(isac, ISAC_MOCR, isac->mocr);
323 WriteISAC(isac, ISAC_MOCR, isac->mocr);
325 WriteISAC(isac, ISAC_MOCR, isac->mocr);
327 ret = isac->monitor(isac->dch.hw, MONITOR_RX_0,
328 isac->mon_rx, isac->mon_rxp);
332 pr_info("%s: MONITOR 0 received %d but no user\n",
333 isac->name, isac->mon_rxp);
341 WriteISAC(isac, ISAC_MOCR, isac->mocr);
343 WriteISAC(isac, ISAC_MOCR, isac->mocr);
345 ret = isac->monitor(isac->dch.hw, MONITOR_RX_1,
346 isac->mon_rx, isac->mon_rxp);
350 pr_info("%s: MONITOR 1 received %d but no user\n",
351 isac->name, isac->mon_rxp);
358 if ((!isac->mon_tx) || (isac->mon_txc &&
359 (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) {
361 WriteISAC(isac, ISAC_MOCR, isac->mocr);
363 WriteISAC(isac, ISAC_MOCR, isac->mocr);
364 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
366 ret = isac->monitor(isac->dch.hw,
367 MONITOR_TX_0, NULL, 0);
375 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
377 ret = isac->monitor(isac->dch.hw,
378 MONITOR_TX_0, NULL, 0);
385 WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]);
386 pr_debug("%s: ISAC %02x -> MOX0\n", isac->name,
387 isac->mon_tx[isac->mon_txp - 1]);
391 if ((!isac->mon_tx) || (isac->mon_txc &&
392 (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) {
394 WriteISAC(isac, ISAC_MOCR, isac->mocr);
396 WriteISAC(isac, ISAC_MOCR, isac->mocr);
397 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
399 ret = isac->monitor(isac->dch.hw,
400 MONITOR_TX_1, NULL, 0);
408 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
410 ret = isac->monitor(isac->dch.hw,
411 MONITOR_TX_1, NULL, 0);
418 WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]);
419 pr_debug("%s: ISAC %02x -> MOX1\n", isac->name,
420 isac->mon_tx[isac->mon_txp - 1]);
423 val = 0; /* dummy to avoid warning */
428 isac_cisq_irq(struct isac_hw *isac) {
431 val = ReadISAC(isac, ISAC_CIR0);
432 pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val);
434 pr_debug("%s: ph_state change %x->%x\n", isac->name,
435 isac->state, (val >> 2) & 0xf);
436 isac->state = (val >> 2) & 0xf;
437 isac_ph_state_change(isac);
440 val = ReadISAC(isac, ISAC_CIR1);
441 pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val);
446 isacsx_cic_irq(struct isac_hw *isac)
450 val = ReadISAC(isac, ISACX_CIR0);
451 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
452 if (val & ISACX_CIR0_CIC0) {
453 pr_debug("%s: ph_state change %x->%x\n", isac->name,
454 isac->state, val >> 4);
455 isac->state = val >> 4;
456 isac_ph_state_change(isac);
461 isacsx_rme_irq(struct isac_hw *isac)
466 val = ReadISAC(isac, ISACX_RSTAD);
467 if ((val & (ISACX_RSTAD_VFR |
471 != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) {
472 pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val);
473 #ifdef ERROR_STATISTIC
474 if (val & ISACX_RSTAD_CRC)
479 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
480 if (isac->dch.rx_skb)
481 dev_kfree_skb(isac->dch.rx_skb);
482 isac->dch.rx_skb = NULL;
484 count = ReadISAC(isac, ISACX_RBCLD) & 0x1f;
487 isac_empty_fifo(isac, count);
488 if (isac->dch.rx_skb) {
489 skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1);
490 pr_debug("%s: dchannel received %d\n", isac->name,
491 isac->dch.rx_skb->len);
492 recv_Dchannel(&isac->dch);
498 mISDNisac_irq(struct isac_hw *isac, u8 val)
502 pr_debug("%s: ISAC interrupt %02x\n", isac->name, val);
503 if (isac->type & IPAC_TYPE_ISACX) {
504 if (val & ISACX__CIC)
505 isacsx_cic_irq(isac);
506 if (val & ISACX__ICD) {
507 val = ReadISAC(isac, ISACX_ISTAD);
508 pr_debug("%s: ISTAD %02x\n", isac->name, val);
509 if (val & ISACX_D_XDU) {
510 pr_debug("%s: ISAC XDU\n", isac->name);
511 #ifdef ERROR_STATISTIC
514 isac_retransmit(isac);
516 if (val & ISACX_D_XMR) {
517 pr_debug("%s: ISAC XMR\n", isac->name);
518 #ifdef ERROR_STATISTIC
521 isac_retransmit(isac);
523 if (val & ISACX_D_XPR)
525 if (val & ISACX_D_RFO) {
526 pr_debug("%s: ISAC RFO\n", isac->name);
527 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
529 if (val & ISACX_D_RME)
530 isacsx_rme_irq(isac);
531 if (val & ISACX_D_RPF)
532 isac_empty_fifo(isac, 0x20);
535 if (val & 0x80) /* RME */
537 if (val & 0x40) /* RPF */
538 isac_empty_fifo(isac, 32);
539 if (val & 0x10) /* XPR */
541 if (val & 0x04) /* CISQ */
543 if (val & 0x20) /* RSC - never */
544 pr_debug("%s: ISAC RSC interrupt\n", isac->name);
545 if (val & 0x02) /* SIN - never */
546 pr_debug("%s: ISAC SIN interrupt\n", isac->name);
547 if (val & 0x01) { /* EXI */
548 val = ReadISAC(isac, ISAC_EXIR);
549 pr_debug("%s: ISAC EXIR %02x\n", isac->name, val);
550 if (val & 0x80) /* XMR */
551 pr_debug("%s: ISAC XMR\n", isac->name);
552 if (val & 0x40) { /* XDU */
553 pr_debug("%s: ISAC XDU\n", isac->name);
554 #ifdef ERROR_STATISTIC
557 isac_retransmit(isac);
559 if (val & 0x04) /* MOS */
565 EXPORT_SYMBOL(mISDNisac_irq);
568 isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb)
570 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
571 struct dchannel *dch = container_of(dev, struct dchannel, dev);
572 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
574 struct mISDNhead *hh = mISDN_HEAD_P(skb);
580 spin_lock_irqsave(isac->hwlock, flags);
581 ret = dchannel_senddata(dch, skb);
582 if (ret > 0) { /* direct TX */
583 id = hh->id; /* skb can be freed */
584 isac_fill_fifo(isac);
586 spin_unlock_irqrestore(isac->hwlock, flags);
587 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
589 spin_unlock_irqrestore(isac->hwlock, flags);
591 case PH_ACTIVATE_REQ:
592 ret = l1_event(dch->l1, hh->prim);
594 case PH_DEACTIVATE_REQ:
595 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
596 ret = l1_event(dch->l1, hh->prim);
606 isac_ctrl(struct isac_hw *isac, u32 cmd, u_long para)
613 spin_lock_irqsave(isac->hwlock, flags);
614 if (!(isac->type & IPAC_TYPE_ISACX)) {
615 /* TODO: implement for IPAC_TYPE_ISACX */
616 if (para & 1) /* B1 */
618 else if (para & 2) /* B2 */
620 /* we only support IOM2 mode */
621 WriteISAC(isac, ISAC_SPCR, tl);
623 WriteISAC(isac, ISAC_ADF1, 0x8);
625 WriteISAC(isac, ISAC_ADF1, 0x0);
627 spin_unlock_irqrestore(isac->hwlock, flags);
630 pr_debug("%s: %s unknown command %x %lx\n", isac->name,
631 __func__, cmd, para);
638 isac_l1cmd(struct dchannel *dch, u32 cmd)
640 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
643 pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state);
646 spin_lock_irqsave(isac->hwlock, flags);
647 ph_command(isac, ISAC_CMD_AR8);
648 spin_unlock_irqrestore(isac->hwlock, flags);
651 spin_lock_irqsave(isac->hwlock, flags);
652 ph_command(isac, ISAC_CMD_AR10);
653 spin_unlock_irqrestore(isac->hwlock, flags);
656 spin_lock_irqsave(isac->hwlock, flags);
657 if ((isac->state == ISAC_IND_EI) ||
658 (isac->state == ISAC_IND_DR) ||
659 (isac->state == ISAC_IND_RS))
660 ph_command(isac, ISAC_CMD_TIM);
662 ph_command(isac, ISAC_CMD_RS);
663 spin_unlock_irqrestore(isac->hwlock, flags);
666 skb_queue_purge(&dch->squeue);
668 dev_kfree_skb(dch->tx_skb);
673 dev_kfree_skb(dch->rx_skb);
676 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
677 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
678 del_timer(&dch->timer);
681 spin_lock_irqsave(isac->hwlock, flags);
682 ph_command(isac, ISAC_CMD_TIM);
683 spin_unlock_irqrestore(isac->hwlock, flags);
685 case PH_ACTIVATE_IND:
686 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
687 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
690 case PH_DEACTIVATE_IND:
691 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
692 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
696 pr_debug("%s: %s unknown command %x\n", isac->name,
704 isac_release(struct isac_hw *isac)
706 if (isac->type & IPAC_TYPE_ISACX)
707 WriteISAC(isac, ISACX_MASK, 0xff);
709 WriteISAC(isac, ISAC_MASK, 0xff);
710 if (isac->dch.timer.function != NULL) {
711 del_timer(&isac->dch.timer);
712 isac->dch.timer.function = NULL;
719 l1_event(isac->dch.l1, CLOSE_CHANNEL);
720 mISDN_freedchannel(&isac->dch);
724 dbusy_timer_handler(struct isac_hw *isac)
729 if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
730 spin_lock_irqsave(isac->hwlock, flags);
731 rbch = ReadISAC(isac, ISAC_RBCH);
732 star = ReadISAC(isac, ISAC_STAR);
733 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
734 isac->name, rbch, star);
735 if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */
736 test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags);
738 /* discard frame; reset transceiver */
739 test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags);
740 if (isac->dch.tx_idx)
741 isac->dch.tx_idx = 0;
743 pr_info("%s: ISAC D-Channel Busy no tx_idx\n",
745 /* Transmitter reset */
746 WriteISAC(isac, ISAC_CMDR, 0x01);
748 spin_unlock_irqrestore(isac->hwlock, flags);
753 open_dchannel(struct isac_hw *isac, struct channel_req *rq)
755 pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__,
756 isac->dch.dev.id, __builtin_return_address(1));
757 if (rq->protocol != ISDN_P_TE_S0)
759 if (rq->adr.channel == 1)
760 /* E-Channel not supported */
762 rq->ch = &isac->dch.dev.D;
763 rq->ch->protocol = rq->protocol;
764 if (isac->dch.state == 7)
765 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
766 0, NULL, GFP_KERNEL);
770 static const char *ISACVer[] =
771 {"2086/2186 V1.1", "2085 B1", "2085 B2",
775 isac_init(struct isac_hw *isac)
781 err = create_l1(&isac->dch, isac_l1cmd);
787 isac->dch.timer.function = (void *) dbusy_timer_handler;
788 isac->dch.timer.data = (long)isac;
789 init_timer(&isac->dch.timer);
791 if (isac->type & IPAC_TYPE_ISACX) {
792 /* Disable all IRQ */
793 WriteISAC(isac, ISACX_MASK, 0xff);
794 val = ReadISAC(isac, ISACX_STARD);
795 pr_debug("%s: ISACX STARD %x\n", isac->name, val);
796 val = ReadISAC(isac, ISACX_ISTAD);
797 pr_debug("%s: ISACX ISTAD %x\n", isac->name, val);
798 val = ReadISAC(isac, ISACX_ISTA);
799 pr_debug("%s: ISACX ISTA %x\n", isac->name, val);
801 WriteISAC(isac, ISACX_TR_CONF0, 0x00);
802 /* enable transmitter */
803 WriteISAC(isac, ISACX_TR_CONF2, 0x00);
804 /* transparent mode 0, RAC, stop/go */
805 WriteISAC(isac, ISACX_MODED, 0xc9);
806 /* all HDLC IRQ unmasked */
807 val = ReadISAC(isac, ISACX_ID);
808 if (isac->dch.debug & DEBUG_HW)
809 pr_notice("%s: ISACX Design ID %x\n",
810 isac->name, val & 0x3f);
811 val = ReadISAC(isac, ISACX_CIR0);
812 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
813 isac->state = val >> 4;
814 isac_ph_state_change(isac);
815 ph_command(isac, ISAC_CMD_RS);
816 WriteISAC(isac, ISACX_MASK, IPACX__ON);
817 WriteISAC(isac, ISACX_MASKD, 0x00);
818 } else { /* old isac */
819 WriteISAC(isac, ISAC_MASK, 0xff);
820 val = ReadISAC(isac, ISAC_STAR);
821 pr_debug("%s: ISAC STAR %x\n", isac->name, val);
822 val = ReadISAC(isac, ISAC_MODE);
823 pr_debug("%s: ISAC MODE %x\n", isac->name, val);
824 val = ReadISAC(isac, ISAC_ADF2);
825 pr_debug("%s: ISAC ADF2 %x\n", isac->name, val);
826 val = ReadISAC(isac, ISAC_ISTA);
827 pr_debug("%s: ISAC ISTA %x\n", isac->name, val);
829 val = ReadISAC(isac, ISAC_EXIR);
830 pr_debug("%s: ISAC EXIR %x\n", isac->name, val);
832 val = ReadISAC(isac, ISAC_RBCH);
833 if (isac->dch.debug & DEBUG_HW)
834 pr_notice("%s: ISAC version (%x): %s\n", isac->name,
835 val, ISACVer[(val >> 5) & 3]);
836 isac->type |= ((val >> 5) & 3);
839 if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */
840 pr_info("%s: only support IOM2 mode but adf2=%02x\n",
841 isac->name, isac->adf2);
845 WriteISAC(isac, ISAC_ADF2, isac->adf2);
846 WriteISAC(isac, ISAC_SQXR, 0x2f);
847 WriteISAC(isac, ISAC_SPCR, 0x00);
848 WriteISAC(isac, ISAC_STCR, 0x70);
849 WriteISAC(isac, ISAC_MODE, 0xc9);
850 WriteISAC(isac, ISAC_TIMR, 0x00);
851 WriteISAC(isac, ISAC_ADF1, 0x00);
852 val = ReadISAC(isac, ISAC_CIR0);
853 pr_debug("%s: ISAC CIR0 %x\n", isac->name, val);
854 isac->state = (val >> 2) & 0xf;
855 isac_ph_state_change(isac);
856 ph_command(isac, ISAC_CMD_RS);
857 WriteISAC(isac, ISAC_MASK, 0);
863 mISDNisac_init(struct isac_hw *isac, void *hw)
865 mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh);
867 isac->dch.dev.D.send = isac_l1hw;
868 isac->init = isac_init;
869 isac->release = isac_release;
870 isac->ctrl = isac_ctrl;
871 isac->open = open_dchannel;
872 isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
873 isac->dch.dev.nrbchan = 2;
876 EXPORT_SYMBOL(mISDNisac_init);
879 waitforCEC(struct hscx_hw *hx)
884 starb = ReadHSCX(hx, IPAC_STARB);
891 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr,
894 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr);
899 waitforXFW(struct hscx_hw *hx)
904 starb = ReadHSCX(hx, IPAC_STARB);
905 if ((starb & 0x44) == 0x40)
911 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr,
914 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr);
918 hscx_cmdr(struct hscx_hw *hx, u8 cmd)
920 if (hx->ip->type & IPAC_TYPE_IPACX)
921 WriteHSCX(hx, IPACX_CMDRB, cmd);
924 WriteHSCX(hx, IPAC_CMDRB, cmd);
929 hscx_empty_fifo(struct hscx_hw *hscx, u8 count)
933 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count);
934 if (!hscx->bch.rx_skb) {
935 hscx->bch.rx_skb = mI_alloc_skb(hscx->bch.maxlen, GFP_ATOMIC);
936 if (!hscx->bch.rx_skb) {
937 pr_info("%s: B receive out of memory\n",
939 hscx_cmdr(hscx, 0x80); /* RMC */
943 if ((hscx->bch.rx_skb->len + count) > hscx->bch.maxlen) {
944 pr_debug("%s: overrun %d\n", hscx->ip->name,
945 hscx->bch.rx_skb->len + count);
946 skb_trim(hscx->bch.rx_skb, 0);
947 hscx_cmdr(hscx, 0x80); /* RMC */
950 p = skb_put(hscx->bch.rx_skb, count);
952 if (hscx->ip->type & IPAC_TYPE_IPACX)
953 hscx->ip->read_fifo(hscx->ip->hw,
954 hscx->off + IPACX_RFIFOB, p, count);
956 hscx->ip->read_fifo(hscx->ip->hw,
957 hscx->off, p, count);
959 hscx_cmdr(hscx, 0x80); /* RMC */
961 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
962 snprintf(hscx->log, 64, "B%1d-recv %s %d ",
963 hscx->bch.nr, hscx->ip->name, count);
964 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
969 hscx_fill_fifo(struct hscx_hw *hscx)
974 if (!hscx->bch.tx_skb)
976 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx;
979 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx;
981 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0;
982 if (count > hscx->fifo_size) {
983 count = hscx->fifo_size;
986 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, count,
987 hscx->bch.tx_idx, hscx->bch.tx_skb->len);
988 hscx->bch.tx_idx += count;
990 if (hscx->ip->type & IPAC_TYPE_IPACX)
991 hscx->ip->write_fifo(hscx->ip->hw,
992 hscx->off + IPACX_XFIFOB, p, count);
995 hscx->ip->write_fifo(hscx->ip->hw,
996 hscx->off, p, count);
998 hscx_cmdr(hscx, more ? 0x08 : 0x0a);
1000 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
1001 snprintf(hscx->log, 64, "B%1d-send %s %d ",
1002 hscx->bch.nr, hscx->ip->name, count);
1003 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
1008 hscx_xpr(struct hscx_hw *hx)
1010 if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len)
1013 if (hx->bch.tx_skb) {
1014 /* send confirm, on trans, free on hdlc. */
1015 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags))
1016 confirm_Bsend(&hx->bch);
1017 dev_kfree_skb(hx->bch.tx_skb);
1019 if (get_next_bframe(&hx->bch))
1025 ipac_rme(struct hscx_hw *hx)
1030 if (hx->ip->type & IPAC_TYPE_IPACX)
1031 rstab = ReadHSCX(hx, IPACX_RSTAB);
1033 rstab = ReadHSCX(hx, IPAC_RSTAB);
1034 pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab);
1035 if ((rstab & 0xf0) != 0xa0) {
1036 /* !(VFR && !RDO && CRC && !RAB) */
1037 if (!(rstab & 0x80)) {
1038 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1039 pr_notice("%s: B%1d invalid frame\n",
1040 hx->ip->name, hx->bch.nr);
1043 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1044 pr_notice("%s: B%1d RDO proto=%x\n",
1045 hx->ip->name, hx->bch.nr,
1048 if (!(rstab & 0x20)) {
1049 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1050 pr_notice("%s: B%1d CRC error\n",
1051 hx->ip->name, hx->bch.nr);
1053 hscx_cmdr(hx, 0x80); /* Do RMC */
1056 if (hx->ip->type & IPAC_TYPE_IPACX)
1057 count = ReadHSCX(hx, IPACX_RBCLB);
1059 count = ReadHSCX(hx, IPAC_RBCLB);
1060 count &= (hx->fifo_size - 1);
1062 count = hx->fifo_size;
1063 hscx_empty_fifo(hx, count);
1064 if (!hx->bch.rx_skb)
1066 if (hx->bch.rx_skb->len < 2) {
1067 pr_debug("%s: B%1d frame to short %d\n",
1068 hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len);
1069 skb_trim(hx->bch.rx_skb, 0);
1071 skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1);
1072 recv_Bchannel(&hx->bch, 0);
1077 ipac_irq(struct hscx_hw *hx, u8 ista)
1079 u8 istab, m, exirb = 0;
1081 if (hx->ip->type & IPAC_TYPE_IPACX)
1082 istab = ReadHSCX(hx, IPACX_ISTAB);
1083 else if (hx->ip->type & IPAC_TYPE_IPAC) {
1084 istab = ReadHSCX(hx, IPAC_ISTAB);
1085 m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB;
1087 exirb = ReadHSCX(hx, IPAC_EXIRB);
1088 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1091 } else if (hx->bch.nr & 2) { /* HSCX B */
1092 if (ista & (HSCX__EXA | HSCX__ICA))
1093 ipac_irq(&hx->ip->hscx[0], ista);
1094 if (ista & HSCX__EXB) {
1095 exirb = ReadHSCX(hx, IPAC_EXIRB);
1096 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1099 istab = ista & 0xF8;
1100 } else { /* HSCX A */
1101 istab = ReadHSCX(hx, IPAC_ISTAB);
1102 if (ista & HSCX__EXA) {
1103 exirb = ReadHSCX(hx, IPAC_EXIRB);
1104 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1107 istab = istab & 0xF8;
1109 if (exirb & IPAC_B_XDU)
1110 istab |= IPACX_B_XDU;
1111 if (exirb & IPAC_B_RFO)
1112 istab |= IPACX_B_RFO;
1113 pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab);
1115 if (!test_bit(FLG_ACTIVE, &hx->bch.Flags))
1118 if (istab & IPACX_B_RME)
1121 if (istab & IPACX_B_RPF) {
1122 hscx_empty_fifo(hx, hx->fifo_size);
1123 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1124 /* receive transparent audio data */
1126 recv_Bchannel(&hx->bch, 0);
1130 if (istab & IPACX_B_RFO) {
1131 pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr);
1132 hscx_cmdr(hx, 0x40); /* RRES */
1135 if (istab & IPACX_B_XPR)
1138 if (istab & IPACX_B_XDU) {
1139 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1143 pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name,
1144 hx->bch.nr, hx->bch.tx_idx);
1146 hscx_cmdr(hx, 0x01); /* XRES */
1151 mISDNipac_irq(struct ipac_hw *ipac, int maxloop)
1153 int cnt = maxloop + 1;
1155 struct isac_hw *isac = &ipac->isac;
1157 if (ipac->type & IPAC_TYPE_IPACX) {
1158 ista = ReadIPAC(ipac, ISACX_ISTA);
1159 while (ista && cnt--) {
1160 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1161 if (ista & IPACX__ICA)
1162 ipac_irq(&ipac->hscx[0], ista);
1163 if (ista & IPACX__ICB)
1164 ipac_irq(&ipac->hscx[1], ista);
1165 if (ista & (ISACX__ICD | ISACX__CIC))
1166 mISDNisac_irq(&ipac->isac, ista);
1167 ista = ReadIPAC(ipac, ISACX_ISTA);
1169 } else if (ipac->type & IPAC_TYPE_IPAC) {
1170 ista = ReadIPAC(ipac, IPAC_ISTA);
1171 while (ista && cnt--) {
1172 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1173 if (ista & (IPAC__ICD | IPAC__EXD)) {
1174 istad = ReadISAC(isac, ISAC_ISTA);
1175 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1176 if (istad & IPAC_D_TIN2)
1177 pr_debug("%s TIN2 irq\n", ipac->name);
1178 if (ista & IPAC__EXD)
1179 istad |= 1; /* ISAC EXI */
1180 mISDNisac_irq(isac, istad);
1182 if (ista & (IPAC__ICA | IPAC__EXA))
1183 ipac_irq(&ipac->hscx[0], ista);
1184 if (ista & (IPAC__ICB | IPAC__EXB))
1185 ipac_irq(&ipac->hscx[1], ista);
1186 ista = ReadIPAC(ipac, IPAC_ISTA);
1188 } else if (ipac->type & IPAC_TYPE_HSCX) {
1190 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off);
1191 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista);
1193 ipac_irq(&ipac->hscx[1], ista);
1194 istad = ReadISAC(isac, ISAC_ISTA);
1195 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1197 mISDNisac_irq(isac, istad);
1198 if (0 == (ista | istad))
1203 if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */
1206 pr_debug("%s: %d irqloops cpu%d\n", ipac->name,
1207 maxloop - cnt, smp_processor_id());
1208 if (maxloop && !cnt)
1209 pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name,
1210 maxloop, smp_processor_id());
1213 EXPORT_SYMBOL(mISDNipac_irq);
1216 hscx_mode(struct hscx_hw *hscx, u32 bprotocol)
1218 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name,
1219 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr);
1220 if (hscx->ip->type & IPAC_TYPE_IPACX) {
1221 if (hscx->bch.nr & 1) { /* B1 and ICA */
1222 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80);
1223 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88);
1224 } else { /* B2 and ICB */
1225 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81);
1226 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88);
1228 switch (bprotocol) {
1229 case ISDN_P_NONE: /* init */
1230 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */
1231 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */
1232 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */
1233 hscx_cmdr(hscx, 0x41);
1234 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1235 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1238 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */
1239 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */
1240 hscx_cmdr(hscx, 0x41);
1241 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1242 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1245 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */
1246 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */
1247 hscx_cmdr(hscx, 0x41);
1248 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1249 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1252 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1254 return -ENOPROTOOPT;
1256 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */
1257 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1258 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1259 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1260 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1261 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1262 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1263 switch (bprotocol) {
1265 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1266 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1267 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1268 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1269 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1270 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1271 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1274 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1275 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1276 hscx_cmdr(hscx, 0x41);
1277 WriteHSCX(hscx, IPAC_MASKB, 0);
1278 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1281 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1282 WriteHSCX(hscx, IPAC_CCR1, 0x8a);
1283 hscx_cmdr(hscx, 0x41);
1284 WriteHSCX(hscx, IPAC_MASKB, 0);
1285 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1288 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1290 return -ENOPROTOOPT;
1292 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */
1293 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1294 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1295 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1296 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1297 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1298 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1299 switch (bprotocol) {
1301 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1302 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1303 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1304 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1305 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1306 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1307 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1310 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1311 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1312 hscx_cmdr(hscx, 0x41);
1313 WriteHSCX(hscx, IPAC_MASKB, 0);
1314 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1317 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1318 WriteHSCX(hscx, IPAC_CCR1, 0x8d);
1319 hscx_cmdr(hscx, 0x41);
1320 WriteHSCX(hscx, IPAC_MASKB, 0);
1321 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1324 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1326 return -ENOPROTOOPT;
1330 hscx->bch.state = bprotocol;
1335 hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
1337 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1338 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1340 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1346 spin_lock_irqsave(hx->ip->hwlock, flags);
1347 ret = bchannel_senddata(bch, skb);
1348 if (ret > 0) { /* direct TX */
1349 id = hh->id; /* skb can be freed */
1352 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1353 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1354 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1356 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1358 case PH_ACTIVATE_REQ:
1359 spin_lock_irqsave(hx->ip->hwlock, flags);
1360 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1361 ret = hscx_mode(hx, ch->protocol);
1364 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1366 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1369 case PH_DEACTIVATE_REQ:
1370 spin_lock_irqsave(hx->ip->hwlock, flags);
1371 mISDN_clear_bchannel(bch);
1372 hscx_mode(hx, ISDN_P_NONE);
1373 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1374 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1379 pr_info("%s: %s unknown prim(%x,%x)\n",
1380 hx->ip->name, __func__, hh->prim, hh->id);
1389 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1394 case MISDN_CTRL_GETOP:
1397 /* Nothing implemented yet */
1398 case MISDN_CTRL_FILL_EMPTY:
1400 pr_info("%s: unknown Op %x\n", __func__, cq->op);
1408 hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1410 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1411 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1415 pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg);
1418 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1419 if (test_bit(FLG_ACTIVE, &bch->Flags)) {
1420 spin_lock_irqsave(hx->ip->hwlock, flags);
1421 mISDN_freebchannel(bch);
1422 hscx_mode(hx, ISDN_P_NONE);
1423 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1425 skb_queue_purge(&bch->rqueue);
1428 ch->protocol = ISDN_P_NONE;
1430 module_put(hx->ip->owner);
1433 case CONTROL_CHANNEL:
1434 ret = channel_bctrl(bch, arg);
1437 pr_info("%s: %s unknown prim(%x)\n",
1438 hx->ip->name, __func__, cmd);
1444 free_ipac(struct ipac_hw *ipac)
1446 isac_release(&ipac->isac);
1449 static const char *HSCXVer[] =
1450 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
1451 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
1456 hscx_init(struct hscx_hw *hx)
1460 WriteHSCX(hx, IPAC_RAH2, 0xFF);
1461 WriteHSCX(hx, IPAC_XBCH, 0x00);
1462 WriteHSCX(hx, IPAC_RLCR, 0x00);
1464 if (hx->ip->type & IPAC_TYPE_HSCX) {
1465 WriteHSCX(hx, IPAC_CCR1, 0x85);
1466 val = ReadHSCX(hx, HSCX_VSTR);
1467 pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val);
1468 if (hx->bch.debug & DEBUG_HW)
1469 pr_notice("%s: HSCX version %s\n", hx->ip->name,
1470 HSCXVer[val & 0x0f]);
1472 WriteHSCX(hx, IPAC_CCR1, 0x82);
1473 WriteHSCX(hx, IPAC_CCR2, 0x30);
1474 WriteHSCX(hx, IPAC_XCCR, 0x07);
1475 WriteHSCX(hx, IPAC_RCCR, 0x07);
1479 ipac_init(struct ipac_hw *ipac)
1483 if (ipac->type & IPAC_TYPE_HSCX) {
1484 hscx_init(&ipac->hscx[0]);
1485 hscx_init(&ipac->hscx[1]);
1486 val = ReadIPAC(ipac, IPAC_ID);
1487 } else if (ipac->type & IPAC_TYPE_IPAC) {
1488 hscx_init(&ipac->hscx[0]);
1489 hscx_init(&ipac->hscx[1]);
1490 WriteIPAC(ipac, IPAC_MASK, IPAC__ON);
1491 val = ReadIPAC(ipac, IPAC_CONF);
1492 /* conf is default 0, but can be overwritten by card setup */
1493 pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name,
1495 WriteIPAC(ipac, IPAC_CONF, ipac->conf);
1496 val = ReadIPAC(ipac, IPAC_ID);
1497 if (ipac->hscx[0].bch.debug & DEBUG_HW)
1498 pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val);
1500 /* nothing special for IPACX to do here */
1501 return isac_init(&ipac->isac);
1505 open_bchannel(struct ipac_hw *ipac, struct channel_req *rq)
1507 struct bchannel *bch;
1509 if (rq->adr.channel > 2)
1511 if (rq->protocol == ISDN_P_NONE)
1513 bch = &ipac->hscx[rq->adr.channel - 1].bch;
1514 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1515 return -EBUSY; /* b-channel can be only open once */
1516 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1517 bch->ch.protocol = rq->protocol;
1523 channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq)
1528 case MISDN_CTRL_GETOP:
1529 cq->op = MISDN_CTRL_LOOP;
1531 case MISDN_CTRL_LOOP:
1532 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
1533 if (cq->channel < 0 || cq->channel > 3) {
1537 ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel);
1540 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op);
1548 ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1550 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1551 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1552 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
1553 struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac);
1554 struct channel_req *rq;
1557 pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg);
1561 if (rq->protocol == ISDN_P_TE_S0)
1562 err = open_dchannel(isac, rq);
1564 err = open_bchannel(ipac, rq);
1567 if (!try_module_get(ipac->owner))
1568 pr_info("%s: cannot get module\n", ipac->name);
1571 pr_debug("%s: dev(%d) close from %p\n", ipac->name,
1572 dch->dev.id, __builtin_return_address(0));
1573 module_put(ipac->owner);
1575 case CONTROL_CHANNEL:
1576 err = channel_ctrl(ipac, arg);
1579 pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd);
1586 mISDNipac_init(struct ipac_hw *ipac, void *hw)
1592 if (ipac->isac.dch.debug & DEBUG_HW)
1593 pr_notice("%s: ipac type %x\n", ipac->name, ipac->type);
1594 if (ipac->type & IPAC_TYPE_HSCX) {
1595 ipac->isac.type = IPAC_TYPE_ISAC;
1596 ipac->hscx[0].off = 0;
1597 ipac->hscx[1].off = 0x40;
1598 ipac->hscx[0].fifo_size = 32;
1599 ipac->hscx[1].fifo_size = 32;
1600 } else if (ipac->type & IPAC_TYPE_IPAC) {
1601 ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC;
1602 ipac->hscx[0].off = 0;
1603 ipac->hscx[1].off = 0x40;
1604 ipac->hscx[0].fifo_size = 64;
1605 ipac->hscx[1].fifo_size = 64;
1606 } else if (ipac->type & IPAC_TYPE_IPACX) {
1607 ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX;
1608 ipac->hscx[0].off = IPACX_OFF_ICA;
1609 ipac->hscx[1].off = IPACX_OFF_ICB;
1610 ipac->hscx[0].fifo_size = 64;
1611 ipac->hscx[1].fifo_size = 64;
1615 mISDNisac_init(&ipac->isac, hw);
1617 ipac->isac.dch.dev.D.ctrl = ipac_dctrl;
1619 for (i = 0; i < 2; i++) {
1620 ipac->hscx[i].bch.nr = i + 1;
1621 set_channelmap(i + 1, ipac->isac.dch.dev.channelmap);
1622 list_add(&ipac->hscx[i].bch.ch.list,
1623 &ipac->isac.dch.dev.bchannels);
1624 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM);
1625 ipac->hscx[i].bch.ch.nr = i + 1;
1626 ipac->hscx[i].bch.ch.send = &hscx_l2l1;
1627 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl;
1628 ipac->hscx[i].bch.hw = hw;
1629 ipac->hscx[i].ip = ipac;
1630 /* default values for IOM time slots
1631 * can be overwriten by card */
1632 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03;
1635 ipac->init = ipac_init;
1636 ipac->release = free_ipac;
1638 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1639 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1642 EXPORT_SYMBOL(mISDNipac_init);
1647 pr_notice("mISDNipac module version %s\n", ISAC_REV);
1652 isac_mod_cleanup(void)
1654 pr_notice("mISDNipac module unloaded\n");
1656 module_init(isac_mod_init);
1657 module_exit(isac_mod_cleanup);