4 * Author Karsten Keil <keil@isdn4linux.de>
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/mISDNhw.h>
27 #include <linux/slab.h>
31 #include <linux/isdn/hdlc.h>
33 #define NETJET_REV "2.0"
61 struct isdnhdlc_vars hsend;
62 struct isdnhdlc_vars hrecv;
67 #define TX_INIT 0x0001
68 #define TX_IDLE 0x0002
70 #define TX_UNDERRUN 0x0100
71 #define RX_OVERRUN 0x0100
76 struct list_head list;
78 char name[MISDN_MAX_IDLEN];
86 spinlock_t lock; /* lock HW */
88 struct tiger_dma send;
89 struct tiger_dma recv;
90 struct tiger_ch bc[2];
99 static LIST_HEAD(Cards);
100 static DEFINE_RWLOCK(card_lock); /* protect Cards */
105 _set_debug(struct tiger_hw *card)
107 card->isac.dch.debug = debug;
108 card->bc[0].bch.debug = debug;
109 card->bc[1].bch.debug = debug;
113 set_debug(const char *val, struct kernel_param *kp)
116 struct tiger_hw *card;
118 ret = param_set_uint(val, kp);
120 read_lock(&card_lock);
121 list_for_each_entry(card, &Cards, list)
123 read_unlock(&card_lock);
128 MODULE_AUTHOR("Karsten Keil");
129 MODULE_LICENSE("GPL v2");
130 MODULE_VERSION(NETJET_REV);
131 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
132 MODULE_PARM_DESC(debug, "Netjet debug mask");
135 nj_disable_hwirq(struct tiger_hw *card)
137 outb(0, card->base + NJ_IRQMASK0);
138 outb(0, card->base + NJ_IRQMASK1);
143 ReadISAC_nj(void *p, u8 offset)
145 struct tiger_hw *card = p;
149 card->auxd |= (offset >> 4) & 3;
150 outb(card->auxd, card->base + NJ_AUXDATA);
151 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
156 WriteISAC_nj(void *p, u8 offset, u8 value)
158 struct tiger_hw *card = p;
161 card->auxd |= (offset >> 4) & 3;
162 outb(card->auxd, card->base + NJ_AUXDATA);
163 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
167 ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
169 struct tiger_hw *card = p;
172 outb(card->auxd, card->base + NJ_AUXDATA);
173 insb(card->base + NJ_ISAC_OFF, data, size);
177 WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
179 struct tiger_hw *card = p;
182 outb(card->auxd, card->base + NJ_AUXDATA);
183 outsb(card->base + NJ_ISAC_OFF, data, size);
187 fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill)
189 struct tiger_hw *card = bc->bch.hw;
190 u32 mask = 0xff, val;
192 pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name,
193 bc->bch.nr, fill, cnt, idx, card->send.idx);
194 if (bc->bch.nr & 2) {
200 val = card->send.start[idx];
203 card->send.start[idx++] = val;
204 if (idx >= card->send.size)
210 mode_tiger(struct tiger_ch *bc, u32 protocol)
212 struct tiger_hw *card = bc->bch.hw;
214 pr_debug("%s: B%1d protocol %x-->%x\n", card->name,
215 bc->bch.nr, bc->bch.state, protocol);
218 if (bc->bch.state == ISDN_P_NONE)
220 fill_mem(bc, 0, card->send.size, 0xff);
221 bc->bch.state = protocol;
222 /* only stop dma and interrupts if both channels NULL */
223 if ((card->bc[0].bch.state == ISDN_P_NONE) &&
224 (card->bc[1].bch.state == ISDN_P_NONE)) {
226 outb(card->dmactrl, card->base + NJ_DMACTRL);
227 outb(0, card->base + NJ_IRQMASK0);
229 test_and_clear_bit(FLG_HDLC, &bc->bch.Flags);
230 test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags);
236 test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags);
237 bc->bch.state = protocol;
239 bc->free = card->send.size/2;
241 bc->txstate = TX_INIT | TX_IDLE;
243 if (!card->dmactrl) {
245 outb(card->dmactrl, card->base + NJ_DMACTRL);
246 outb(0x0f, card->base + NJ_IRQMASK0);
250 test_and_set_bit(FLG_HDLC, &bc->bch.Flags);
251 bc->bch.state = protocol;
253 bc->free = card->send.size/2;
255 bc->txstate = TX_INIT | TX_IDLE;
256 isdnhdlc_rcv_init(&bc->hrecv, 0);
257 isdnhdlc_out_init(&bc->hsend, 0);
259 if (!card->dmactrl) {
261 outb(card->dmactrl, card->base + NJ_DMACTRL);
262 outb(0x0f, card->base + NJ_IRQMASK0);
266 pr_info("%s: %s protocol %x not handled\n", card->name,
270 card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR);
271 card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR);
272 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
273 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
274 pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n",
275 card->name, __func__,
276 inb(card->base + NJ_DMACTRL),
277 inb(card->base + NJ_IRQMASK0),
278 inb(card->base + NJ_IRQSTAT0),
285 nj_reset(struct tiger_hw *card)
287 outb(0xff, card->base + NJ_CTRL); /* Reset On */
290 /* now edge triggered for TJ320 GE 13/07/00 */
291 /* see comment in IRQ function */
292 if (card->typ == NETJET_S_TJ320) /* TJ320 */
293 card->ctrlreg = 0x40; /* Reset Off and status read clear */
295 card->ctrlreg = 0x00; /* Reset Off and status read clear */
296 outb(card->ctrlreg, card->base + NJ_CTRL);
299 /* configure AUX pins (all output except ISAC IRQ pin) */
302 outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL);
303 outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1);
304 outb(card->auxd, card->base + NJ_AUXDATA);
308 inittiger(struct tiger_hw *card)
312 card->dma_p = pci_alloc_consistent(card->pdev, NJ_DMA_SIZE,
315 pr_info("%s: No DMA memory\n", card->name);
318 if ((u64)card->dma > 0xffffffff) {
319 pr_info("%s: DMA outside 32 bit\n", card->name);
322 for (i = 0; i < 2; i++) {
323 card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC);
324 if (!card->bc[i].hsbuf) {
325 pr_info("%s: no B%d send buffer\n", card->name, i + 1);
328 card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC);
329 if (!card->bc[i].hrbuf) {
330 pr_info("%s: no B%d recv buffer\n", card->name, i + 1);
334 memset(card->dma_p, 0xff, NJ_DMA_SIZE);
336 card->send.start = card->dma_p;
337 card->send.dmastart = (u32)card->dma;
338 card->send.dmaend = card->send.dmastart +
339 (4 * (NJ_DMA_TXSIZE - 1));
340 card->send.dmairq = card->send.dmastart +
341 (4 * ((NJ_DMA_TXSIZE / 2) - 1));
342 card->send.size = NJ_DMA_TXSIZE;
344 if (debug & DEBUG_HW)
345 pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p"
346 " size %zu u32\n", card->name,
347 card->send.dmastart, card->send.dmairq,
348 card->send.dmaend, card->send.start, card->send.size);
350 outl(card->send.dmastart, card->base + NJ_DMA_READ_START);
351 outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ);
352 outl(card->send.dmaend, card->base + NJ_DMA_READ_END);
354 card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2);
355 card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2);
356 card->recv.dmaend = card->recv.dmastart +
357 (4 * (NJ_DMA_RXSIZE - 1));
358 card->recv.dmairq = card->recv.dmastart +
359 (4 * ((NJ_DMA_RXSIZE / 2) - 1));
360 card->recv.size = NJ_DMA_RXSIZE;
362 if (debug & DEBUG_HW)
363 pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p"
364 " size %zu u32\n", card->name,
365 card->recv.dmastart, card->recv.dmairq,
366 card->recv.dmaend, card->recv.start, card->recv.size);
368 outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START);
369 outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ);
370 outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END);
375 read_dma(struct tiger_ch *bc, u32 idx, int cnt)
377 struct tiger_hw *card = bc->bch.hw;
382 if (bc->lastrx == idx) {
383 bc->rxstate |= RX_OVERRUN;
384 pr_info("%s: B%1d overrun at idx %d\n", card->name,
388 if (!bc->bch.rx_skb) {
389 bc->bch.rx_skb = mI_alloc_skb(bc->bch.maxlen, GFP_ATOMIC);
390 if (!bc->bch.rx_skb) {
391 pr_info("%s: B%1d receive out of memory\n",
392 card->name, bc->bch.nr);
397 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) {
398 if ((bc->bch.rx_skb->len + cnt) > bc->bch.maxlen) {
399 pr_debug("%s: B%1d overrun %d\n", card->name,
400 bc->bch.nr, bc->bch.rx_skb->len + cnt);
401 skb_trim(bc->bch.rx_skb, 0);
404 p = skb_put(bc->bch.rx_skb, cnt);
408 for (i = 0; i < cnt; i++) {
409 val = card->recv.start[idx++];
412 if (idx >= card->recv.size)
418 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
419 stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i,
420 bc->bch.rx_skb->data, bc->bch.maxlen);
421 if (stat > 0) /* valid frame received */
422 p = skb_put(bc->bch.rx_skb, stat);
423 else if (stat == -HDLC_CRC_ERROR)
424 pr_info("%s: B%1d receive frame CRC error\n",
425 card->name, bc->bch.nr);
426 else if (stat == -HDLC_FRAMING_ERROR)
427 pr_info("%s: B%1d receive framing error\n",
428 card->name, bc->bch.nr);
429 else if (stat == -HDLC_LENGTH_ERROR)
430 pr_info("%s: B%1d receive frame too long (> %d)\n",
431 card->name, bc->bch.nr, bc->bch.maxlen);
436 if (debug & DEBUG_HW_BFIFO) {
437 snprintf(card->log, LOG_SIZE, "B%1d-recv %s %d ",
438 bc->bch.nr, card->name, stat);
439 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET,
442 recv_Bchannel(&bc->bch, 0);
444 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
447 if (!bc->bch.rx_skb) {
448 bc->bch.rx_skb = mI_alloc_skb(bc->bch.maxlen,
450 if (!bc->bch.rx_skb) {
451 pr_info("%s: B%1d receive out of memory\n",
452 card->name, bc->bch.nr);
462 recv_tiger(struct tiger_hw *card, u8 irq_stat)
465 int cnt = card->recv.size / 2;
467 /* Note receive is via the WRITE DMA channel */
468 card->last_is0 &= ~NJ_IRQM0_WR_MASK;
469 card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK);
471 if (irq_stat & NJ_IRQM0_WR_END)
474 idx = card->recv.size - 1;
476 if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags))
477 read_dma(&card->bc[0], idx, cnt);
478 if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags))
479 read_dma(&card->bc[1], idx, cnt);
482 /* sync with current DMA address at start or after exception */
484 resync(struct tiger_ch *bc, struct tiger_hw *card)
486 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
487 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
488 if (bc->free > card->send.size / 2)
489 bc->free = card->send.size / 2;
490 /* currently we simple sync to the next complete free area
491 * this hast the advantage that we have always maximum time to
494 if (card->send.idx < ((card->send.size / 2) - 1))
495 bc->idx = (card->recv.size / 2) - 1;
497 bc->idx = card->recv.size - 1;
498 bc->txstate = TX_RUN;
499 pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name,
500 __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx);
503 static int bc_next_frame(struct tiger_ch *);
506 fill_hdlc_flag(struct tiger_ch *bc)
508 struct tiger_hw *card = bc->bch.hw;
515 pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name,
516 __func__, bc->bch.nr, bc->free, bc->txstate,
517 bc->idx, card->send.idx);
518 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
520 count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i,
521 bc->hsbuf, bc->free);
522 pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name,
526 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
527 for (i = 0; i < count; i++) {
528 if (bc->idx >= card->send.size)
530 v = card->send.start[bc->idx];
532 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
533 card->send.start[bc->idx++] = v;
535 if (debug & DEBUG_HW_BFIFO) {
536 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
537 bc->bch.nr, card->name, count);
538 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
543 fill_dma(struct tiger_ch *bc)
545 struct tiger_hw *card = bc->bch.hw;
552 count = bc->bch.tx_skb->len - bc->bch.tx_idx;
555 pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n", card->name,
556 __func__, bc->bch.nr, count, bc->free, bc->bch.tx_idx,
557 bc->bch.tx_skb->len, bc->txstate, bc->idx, card->send.idx);
558 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
560 p = bc->bch.tx_skb->data + bc->bch.tx_idx;
561 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
562 count = isdnhdlc_encode(&bc->hsend, p, count, &i,
563 bc->hsbuf, bc->free);
564 pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name,
565 bc->bch.nr, i, count);
570 if (count > bc->free)
572 bc->bch.tx_idx += count;
575 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
576 for (i = 0; i < count; i++) {
577 if (bc->idx >= card->send.size)
579 v = card->send.start[bc->idx];
581 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
582 card->send.start[bc->idx++] = v;
584 if (debug & DEBUG_HW_BFIFO) {
585 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
586 bc->bch.nr, card->name, count);
587 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
595 bc_next_frame(struct tiger_ch *bc)
597 if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len)
600 if (bc->bch.tx_skb) {
601 /* send confirm, on trans, free on hdlc. */
602 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags))
603 confirm_Bsend(&bc->bch);
604 dev_kfree_skb(bc->bch.tx_skb);
606 if (get_next_bframe(&bc->bch))
615 send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc)
619 bc->free += card->send.size / 2;
620 if (bc->free >= card->send.size) {
621 if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) {
622 pr_info("%s: B%1d TX underrun state %x\n", card->name,
623 bc->bch.nr, bc->txstate);
624 bc->txstate |= TX_UNDERRUN;
626 bc->free = card->send.size;
628 ret = bc_next_frame(bc);
630 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
634 pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name,
635 bc->bch.nr, bc->free, bc->idx, card->send.idx);
636 if (!(bc->txstate & (TX_IDLE | TX_INIT))) {
637 fill_mem(bc, bc->idx, bc->free, 0xff);
638 if (bc->free == card->send.size)
639 bc->txstate |= TX_IDLE;
645 send_tiger(struct tiger_hw *card, u8 irq_stat)
649 /* Note send is via the READ DMA channel */
650 if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) {
651 pr_info("%s: tiger warn write double dma %x/%x\n",
652 card->name, irq_stat, card->last_is0);
655 card->last_is0 &= ~NJ_IRQM0_RD_MASK;
656 card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK);
658 for (i = 0; i < 2; i++) {
659 if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags))
660 send_tiger_bc(card, &card->bc[i]);
665 nj_irq(int intno, void *dev_id)
667 struct tiger_hw *card = dev_id;
668 u8 val, s1val, s0val;
670 spin_lock(&card->lock);
671 s0val = inb(card->base | NJ_IRQSTAT0);
672 s1val = inb(card->base | NJ_IRQSTAT1);
673 if ((s1val & NJ_ISACIRQ) && (s0val == 0)) {
675 spin_unlock(&card->lock);
678 pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val);
680 if (!(s1val & NJ_ISACIRQ)) {
681 val = ReadISAC_nj(card, ISAC_ISTA);
683 mISDNisac_irq(&card->isac, val);
688 outb(s0val, card->base | NJ_IRQSTAT0);
692 /* set bits in sval to indicate which page is free */
693 card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR);
694 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
695 if (card->recv.dmacur < card->recv.dmairq)
696 s0val = 0x08; /* the 2nd write area is free */
698 s0val = 0x04; /* the 1st write area is free */
700 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
701 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
702 if (card->send.dmacur < card->send.dmairq)
703 s0val |= 0x02; /* the 2nd read area is free */
705 s0val |= 0x01; /* the 1st read area is free */
707 pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name,
708 s1val, s0val, card->last_is0,
709 card->recv.idx, card->send.idx);
710 /* test if we have a DMA interrupt */
711 if (s0val != card->last_is0) {
712 if ((s0val & NJ_IRQM0_RD_MASK) !=
713 (card->last_is0 & NJ_IRQM0_RD_MASK))
714 /* got a write dma int */
715 send_tiger(card, s0val);
716 if ((s0val & NJ_IRQM0_WR_MASK) !=
717 (card->last_is0 & NJ_IRQM0_WR_MASK))
718 /* got a read dma int */
719 recv_tiger(card, s0val);
722 spin_unlock(&card->lock);
727 nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
730 struct bchannel *bch = container_of(ch, struct bchannel, ch);
731 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
732 struct tiger_hw *card = bch->hw;
733 struct mISDNhead *hh = mISDN_HEAD_P(skb);
739 spin_lock_irqsave(&card->lock, flags);
740 ret = bchannel_senddata(bch, skb);
741 if (ret > 0) { /* direct TX */
742 id = hh->id; /* skb can be freed */
745 spin_unlock_irqrestore(&card->lock, flags);
746 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
747 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
749 spin_unlock_irqrestore(&card->lock, flags);
751 case PH_ACTIVATE_REQ:
752 spin_lock_irqsave(&card->lock, flags);
753 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
754 ret = mode_tiger(bc, ch->protocol);
757 spin_unlock_irqrestore(&card->lock, flags);
759 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
762 case PH_DEACTIVATE_REQ:
763 spin_lock_irqsave(&card->lock, flags);
764 mISDN_clear_bchannel(bch);
765 mode_tiger(bc, ISDN_P_NONE);
766 spin_unlock_irqrestore(&card->lock, flags);
767 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
778 channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq)
781 struct tiger_hw *card = bc->bch.hw;
784 case MISDN_CTRL_GETOP:
787 /* Nothing implemented yet */
788 case MISDN_CTRL_FILL_EMPTY:
790 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
798 nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
800 struct bchannel *bch = container_of(ch, struct bchannel, ch);
801 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
802 struct tiger_hw *card = bch->hw;
806 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
809 test_and_clear_bit(FLG_OPEN, &bch->Flags);
810 if (test_bit(FLG_ACTIVE, &bch->Flags)) {
811 spin_lock_irqsave(&card->lock, flags);
812 mISDN_freebchannel(bch);
813 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
814 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
815 mode_tiger(bc, ISDN_P_NONE);
816 spin_unlock_irqrestore(&card->lock, flags);
818 ch->protocol = ISDN_P_NONE;
820 module_put(THIS_MODULE);
823 case CONTROL_CHANNEL:
824 ret = channel_bctrl(bc, arg);
827 pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd);
833 channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq)
838 case MISDN_CTRL_GETOP:
839 cq->op = MISDN_CTRL_LOOP;
841 case MISDN_CTRL_LOOP:
842 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
843 if (cq->channel < 0 || cq->channel > 3) {
847 ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel);
850 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
858 open_bchannel(struct tiger_hw *card, struct channel_req *rq)
860 struct bchannel *bch;
862 if (rq->adr.channel > 2)
864 if (rq->protocol == ISDN_P_NONE)
866 bch = &card->bc[rq->adr.channel - 1].bch;
867 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
868 return -EBUSY; /* b-channel can be only open once */
869 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
870 bch->ch.protocol = rq->protocol;
876 * device control function
879 nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
881 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
882 struct dchannel *dch = container_of(dev, struct dchannel, dev);
883 struct tiger_hw *card = dch->hw;
884 struct channel_req *rq;
887 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
891 if (rq->protocol == ISDN_P_TE_S0)
892 err = card->isac.open(&card->isac, rq);
894 err = open_bchannel(card, rq);
897 if (!try_module_get(THIS_MODULE))
898 pr_info("%s: cannot get module\n", card->name);
901 pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id,
902 __builtin_return_address(0));
903 module_put(THIS_MODULE);
905 case CONTROL_CHANNEL:
906 err = channel_ctrl(card, arg);
909 pr_debug("%s: %s unknown command %x\n",
910 card->name, __func__, cmd);
917 nj_init_card(struct tiger_hw *card)
922 spin_lock_irqsave(&card->lock, flags);
923 nj_disable_hwirq(card);
924 spin_unlock_irqrestore(&card->lock, flags);
926 card->irq = card->pdev->irq;
927 if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) {
928 pr_info("%s: couldn't get interrupt %d\n",
929 card->name, card->irq);
934 spin_lock_irqsave(&card->lock, flags);
936 ret = card->isac.init(&card->isac);
939 ret = inittiger(card);
942 mode_tiger(&card->bc[0], ISDN_P_NONE);
943 mode_tiger(&card->bc[1], ISDN_P_NONE);
945 spin_unlock_irqrestore(&card->lock, flags);
951 nj_release(struct tiger_hw *card)
957 spin_lock_irqsave(&card->lock, flags);
958 nj_disable_hwirq(card);
959 mode_tiger(&card->bc[0], ISDN_P_NONE);
960 mode_tiger(&card->bc[1], ISDN_P_NONE);
961 card->isac.release(&card->isac);
962 spin_unlock_irqrestore(&card->lock, flags);
963 release_region(card->base, card->base_s);
967 free_irq(card->irq, card);
968 if (card->isac.dch.dev.dev.class)
969 mISDN_unregister_device(&card->isac.dch.dev);
971 for (i = 0; i < 2; i++) {
972 mISDN_freebchannel(&card->bc[i].bch);
973 kfree(card->bc[i].hsbuf);
974 kfree(card->bc[i].hrbuf);
977 pci_free_consistent(card->pdev, NJ_DMA_SIZE,
978 card->dma_p, card->dma);
979 write_lock_irqsave(&card_lock, flags);
980 list_del(&card->list);
981 write_unlock_irqrestore(&card_lock, flags);
982 pci_clear_master(card->pdev);
983 pci_disable_device(card->pdev);
984 pci_set_drvdata(card->pdev, NULL);
990 nj_setup(struct tiger_hw *card)
992 card->base = pci_resource_start(card->pdev, 0);
993 card->base_s = pci_resource_len(card->pdev, 0);
994 if (!request_region(card->base, card->base_s, card->name)) {
995 pr_info("%s: NETjet config port %#x-%#x already in use\n",
996 card->name, card->base,
997 (u32)(card->base + card->base_s - 1));
1001 ASSIGN_FUNC(nj, ISAC, card->isac);
1006 static int __devinit
1007 setup_instance(struct tiger_hw *card)
1012 snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1);
1013 write_lock_irqsave(&card_lock, flags);
1014 list_add_tail(&card->list, &Cards);
1015 write_unlock_irqrestore(&card_lock, flags);
1018 card->isac.name = card->name;
1019 spin_lock_init(&card->lock);
1020 card->isac.hwlock = &card->lock;
1021 mISDNisac_init(&card->isac, card);
1023 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1024 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1025 card->isac.dch.dev.D.ctrl = nj_dctrl;
1026 for (i = 0; i < 2; i++) {
1027 card->bc[i].bch.nr = i + 1;
1028 set_channelmap(i + 1, card->isac.dch.dev.channelmap);
1029 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM);
1030 card->bc[i].bch.hw = card;
1031 card->bc[i].bch.ch.send = nj_l2l1B;
1032 card->bc[i].bch.ch.ctrl = nj_bctrl;
1033 card->bc[i].bch.ch.nr = i + 1;
1034 list_add(&card->bc[i].bch.ch.list,
1035 &card->isac.dch.dev.bchannels);
1036 card->bc[i].bch.hw = card;
1038 err = nj_setup(card);
1041 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
1045 err = nj_init_card(card);
1048 pr_notice("Netjet %d cards installed\n", nj_cnt);
1056 static int __devinit
1057 nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1061 struct tiger_hw *card;
1063 if (pdev->subsystem_vendor == 0x8086 &&
1064 pdev->subsystem_device == 0x0003) {
1065 pr_notice("Netjet: Digium X100P/X101P not handled\n");
1069 if (pdev->subsystem_vendor == 0x55 &&
1070 pdev->subsystem_device == 0x02) {
1071 pr_notice("Netjet: Enter!Now not handled yet\n");
1075 card = kzalloc(sizeof(struct tiger_hw), GFP_ATOMIC);
1077 pr_info("No kmem for Netjet\n");
1083 err = pci_enable_device(pdev);
1089 printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n",
1092 pci_set_master(pdev);
1094 /* the TJ300 and TJ320 must be detected, the IRQ handling is different
1095 * unfortunately the chips use the same device ID, but the TJ320 has
1096 * the bit20 in status PCI cfg register set
1098 pci_read_config_dword(pdev, 0x04, &cfg);
1099 if (cfg & 0x00100000)
1100 card->typ = NETJET_S_TJ320;
1102 card->typ = NETJET_S_TJ300;
1104 card->base = pci_resource_start(pdev, 0);
1105 card->irq = pdev->irq;
1106 pci_set_drvdata(pdev, card);
1107 err = setup_instance(card);
1109 pci_set_drvdata(pdev, NULL);
1115 static void __devexit nj_remove(struct pci_dev *pdev)
1117 struct tiger_hw *card = pci_get_drvdata(pdev);
1122 pr_info("%s drvdata already removed\n", __func__);
1125 /* We cannot select cards with PCI_SUB... IDs, since here are cards with
1126 * SUB IDs set to PCI_ANY_ID, so we need to match all and reject
1127 * known other cards which not work with this driver - see probe function */
1128 static struct pci_device_id nj_pci_ids[] __devinitdata = {
1129 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300,
1130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1133 MODULE_DEVICE_TABLE(pci, nj_pci_ids);
1135 static struct pci_driver nj_driver = {
1138 .remove = __devexit_p(nj_remove),
1139 .id_table = nj_pci_ids,
1142 static int __init nj_init(void)
1146 pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV);
1147 err = pci_register_driver(&nj_driver);
1151 static void __exit nj_cleanup(void)
1153 pci_unregister_driver(&nj_driver);
1156 module_init(nj_init);
1157 module_exit(nj_cleanup);